CA1092836A - Electronic timepiece with selective display of various time functions - Google Patents

Abstract

ABSTRACT
An electronic timepiece comprises a time standard oscillator, at least first, secondary and additional time counting means for counting time signals derived from said oscillator, means for controlling the addi-tional time counting means to operate as chronograph time counting means, a common display, and means, operable at will and comprising a plurality of selecting gate circuits each controllable to select, as its output, one of a plurality of inputs, one from each of the time counting means for selecting the count in any one of said time counting means for display by said common display. Preferably, each of said time counting means com-prises a seconds counter, a minutes counter and a 24 hour counter and each selecting gate circuit comprises a plurality of sets of transmission gates each set being connected to receive BCD bit outputs from the respective counters, each in one of the time counting means, and means for selectively rendering said sets conductive, one at a time to transmit the input signals thereto to output terminals.

Description

~0~92836 This invention relates to an electronic timepiece -particularly a digital wristwatch - which has capability for selecting and displaying a number of different time functions.
An electronic timepiece has time-measuring circuits, control circuits and a display device. With developing technology, the physical size of the electronic components of the watch has decreased,- largely due to increasing use of integrated circuits and related technology. Thus, surplus space has become available and it has beconle feasible to incorporate the electronics for more than one time-measuring function into an electronic timepiece with-out detrimentally affecting the size of the instrument.
E~owever, it is detrimental to both the size and conven-ience of the instrument if more than one display device is used. If the various time functions are displayed sep-arately, using separate circuits and display devices, the physical size of each display device clearly becomes smaller, thus making its reading more difficult and giving rise to the possibility of errors. Also, there are manu-facturing and assembly problems associated with trying to fit more than one display into one timepiece,without increasing the size of the instrument.
Therefore, an object of the present invention is to provide an electronic timepiece with circuitry which enables the selective display of various time functions, without the necessity for more than one display. For example, the user can obtain a readout of his local time or the time of another region or country. I~sofar as the user's local time is concerned, it is desirable that ,, 10~:2836 this be given on a 12-hour display, whereas the secondary time is preferably shown on a 24-hour display to avoid the necessity for knowing whether the displayed time of the other region or country is in the "AM" or "PM" part of the day or night.
Another function which may readily be incorporated into the time-piece of the present invention is a chronograph (elapsed-time) function, by which sporting events, for example, may be timed. As will hereinafter become apparent, a large variety of time-measuring functions may be combined in various ways to provide great flexibility.
Thus, according to the present invention, there is provided an electronic timepiece comprising a time standard oscillator, at least first, secondary and additional time counting means for counting time signals derived from said oscillator means for controlling said additional time counting means to operate as chronograph time counting means, a common display, and means, operable at will and comprising a plurality of selecting gate circuits each controllable to select, as its output, one of a plurality of inputs, one from each of the time counting means for selecting the count in any one of said time counting means for display by said common display.
According to a preferred embodiment, the timepiece comprises, in combination; an oscillator circuit for generating a repetitive time standard signal having a repetition rate defining a time base; a dividing circuit connected to receive said time standard signal for dividing the same to develop a repetitive output signal having a repetition rate re-presenting passage of time; a primary time counter of the 24 hour type connected for counting the output signal of said dividing circuit for developing a count representative of time and which advances with the passage of time; a secondary time counter of the 24 hour type connected for counting the output signal of said dividing circuit for developing a count represent-ative of time and which advances with the passage of time; a third time . .

~09;2fl36 counter of the 24 hour type comprlsed of a plurality of individual counters in cascade for counting the output signal of said dividing circuit; means for applying the output signal of sald dividing circuit to selected ones of said counters comprising said third time counter at a certain time and for terminating application of the output signal of said dividlng circuit to operate said third counter in a chronograph mode; a time correcting circuit cooperative with said primary and secondary time counters for setting the respective counts of said primary and secondary time counters; a display circuit responsive to the count of a respective one of said counters for displaying a time represented by the count; and time selecting means for selectively applying the count of a respective one of said counters to said display circuit for displaying a selected time and for operating the timepiece in a timekeeping mode or a chronograph mode.

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The invention will now be described further by way of example only and with reference to the accompanying drawings, wherein:
Figure 1 is a b].ock diagram of a basic electronic timepiece including a 24-hour counting function;
- Figure 2 is a schematic diagram of the 24-hours counter of Figure l;
Figure 3 is a waveform diagram illustrating the operation of the circuit of Figure 2;
, 10 Figure 4 is a block diagram of an electronic time-piece according to the present invention incorporating a 24-hour actual-time function; and a 12-hour actual-tin~e function;
Figure 5 is a schematic diagram of the display selecting circuit employed in the circuit of Figure 4;
: Figure 6 is a waveform diagram illustrating the operation of the circuit of Figure 5;
Figure 7 is a schematic diagram of a gate circuit :: as used in the circuit of Figure 4;
E'igure 8 is a block diagram of an electronic time-piece according to the present invention incorporating an ; actual-time counting function and an elapsed-time counting function;
Figure 9 is a schematic circuit diagram of the control circuit of Figure 8;
Figure 10 is a waveform diagram illustrating the ; operation of the circuit of Figure 9;
Figure 11 is a block diagram of an electronic timepiece according to the present invention incorporating : -3-'' ' lQ~2B36 first and second 24-hour actual-time functions and an elapsed-time function;
- Figure 12 is a schematic diagram of the display selecting circuit used in Figure ll;
Figure 13 is a waveform diagram illustrating the operation of the cir-cuit of Figure 12; and Figure 14 is a schematic diagram of a gate circuit used in the circuit of Figure ll.
Referring now to the drawings, and particularly to Figure l, reference numeral l is an oscillation circuit using a solid vibrator or the like and emitt-ing an oscilla-tion signal of relatively high frequency. The oscillation signal from said oscillation circuit 1 is divided into time-standard reference signals of appropriate frequency (1 Hz in this embodiment) by a frequency-dividing circuit

2 consisting of a plurality of frequency-dividing stages. The reference signals are fed to a seconds counter 4, a minutes counter 5, and a 24-hour counter 6.
The output from the seconds counter 4, to which said reference signal is applied, is applied to a decoder/driver 7. The output is also applied to the minutes counter 5, which counts the input pulses and, after sixty pulses applies a minute pulse to the decoder/driver. Similarly, the hours counter 6 applies an hour pulse to the decoder/driver upon completicn of sixty pulses from the counter 5. The hours counter counts up to twenty-four pulses. The decorder/driver 7 to which are applied the counting contents of the respective counters 4, 5, 6 of the time counter bloc]~ 3 converts the outputs of these counters into signals which are suitable to feed the display device 8 and carries out a predetermined amplification .

lO~,B36 of said signals and applies them to said display device.
Said display device 8 then performs the time display in response to the output of the decoder/driver 7.
Figure 2 is a logic circuit diagram which shows a preferred example of the counter 6 of Fig. 1. The counter has six flip-flop circuits (hereinafter referred to as "FF"), 18, 19, 20, 21, 22 and 23. The carrier signal, that is ONE-level time pulses, given out from the minute counter 5 (shown in Fig. 1) is fed to the clock terminals C18 and C20 of FF18 and FF20 and also to one of the input terminals of NOR circuit 28. The output terminal Q18 f FF18 is connected to one of the input terminals of NOR
circuit 24 having two input terminals, the output side of which is connected to the data terminal D18 of FF18 and also connected to the output terminal 6A. The inverted output terminal Q18 is connected to the clock terminal C19 of FFl9 and to one of the input termînals of NOR circuit 25, having two input terminals the output side of which is connected to the data terminal D20 of FF20. The output terminal Q19 of FF19 is connected to the output terminal 6B and the inverted output terminal Ql9 is connected to the data terminal Dlg and also to the remaining input terminal of NOR circuit 25.
The output terminal Q20 of FF20 is connected to the remaining input terminal of NOR circuit 24 and also to the output terminal 6C. The inverted output terminal Q20 is connected to the clock terminal C21 of FF21 and also to one of the input terminals of NOR circuit 26, having two input terminals.

The output terminal Q21 of FF21 is connected to the output terminal 6D. The inverted output terminal Q21 is connected to the data terminal D21 and also to the clock terminal C22 of FF22.
The output terminal Q22 of FF22 is connected to the output terminal 6E. The inverted output terminal Q22 is connected to the data terminal D22 and also to the clock terminal C23 of FF23.
The output terminal Q23 of FF23 is connected to the output terminal 10F. The inverted output terminal Q23 is connected to the data terminal D23 and also to the remaining input terminal of NOR circuit 26.
The output side of NOR circuit 26 is connected to one of the input terminals of NOR circuit 27, having two input terminals. The output side of NOR circuit 27 is connected to the remaining input terminal of NOR circuit 28. The output side of NOR circuit 28 is connected to the remaining input terminal of NOR circuit 27 and also to the RESET terminals of FF18 to FF23, respectively. However, the output of each flip-flop FF18 through FF23 changes when the signal is applied to the clock terminal.
The action of the hour counter 6 is explained hereinafter with reference to the waveform diagram of Fig. 3. In Fig. 3, the suffix "a" after the numerical symbol given against each waveform shows the voltage level of each respective part of the circuit of Fig. 2 and the numerical symbol 5a denotes the carrier signal having a cylic period of 1 hour and pulse width of 0.5 seconds, derived from the minute counter 5 of Fig. 1.
Before the first pulse of the carrier signal, from the minute counter 5 is applied, at zero hours, the :

lOgZ836 output of FF18 and that of FF20 are both at "logic.0", and the output of NOR circuit 24 appli~d to the data terminal D18 of FF18 is at "logic 1". Therefore, when the first pulse is applied from the minute counter 5, the output of FF18 changes to "logic 1" and the inverted output changes to "logic 0". With these changes, the output of NOR circuit 24 changes to "logic 0". On the other hand, since the inverted output of FF19 is at "logic 1" at the initiation of the pulse from the minute counter 5, the output of NOR circuit 25 is at "logic 0". Therefoxe, the output of FF20 stays at "logic 0" when the above-mentioned pulse is applied.
When the next pulse is applied from the minute counter 5, the output of FF18 changes to "logic 0" because the output of NOR circuit 24 is at "logic O", and the inverted output changes to "logic 1". In response to this change of the inverted output of FF18 from "logic 0" to "logic 1", the output of FFl9 changes to "logic 1" and the inverted output changes from "logic 1" to "logic 0". On the other hand, since the data terminal D20 at the time when the above-mentioned second pulse is applied is at "logic 0", the output of FF20 remains at "logic 0".
Next, when the third pulse is applied from the minute counter 5, the output of FF18 changes to "logic 1"
and the output of NOR Circuit 24 changes to "logic 0". At this time, the data terminal D20 of FF20 - that is, the output of NOR circuit 25 - changes to "logic 1" and the output of FF20 remains at "logic 0".
When the fourth pulse is applied from the minute counter 5, the output of FF18 changes to "logic 0" and the : .

10~836 - inverted output changes to "logic 1". Accordingly, the output of FFl9 changes to "logic 0" and the output of FF20 changes to "logic 0" for the first time.
When the fifth pulse is applied from the minute counter 5, the output of FF20 changes to "logic 0" while the output of FF18 and that of FF19 remains the same.
Therefore, the inverted output of FF20 changes from "logic 0" to "logic 1" and, accordingly, the output of FF21 changes from "logic 0" to "logic 1" for the first time.
From the sixth to twenty-third pulses applied from the minute counter 5, the above-described sequence is repeated in FF18, FF19 and FF20. The output of FF21 changes at the instant when the inverted output of FF20 changes from "logic 0" to "logic 1", and the output of FF20 changes at the instant when the inverted output of FF21 changes from "logic 0" to "logic 1". Furthermore, the output of FF23 changes at the instant when the inverted output of FF23 changes from "logic 0" to "logic 1".
Consequently, the condition of each output of FF18 through FF23, between the time when the 23rd pulse from the minute counter 5 is applied and the time when the 2~th pulse is applied, is that the output of FF18 is "logic 1", the output of FFl9 is "logic 1", the output of FF20 is "logic 0", the output of each of FF21 and FF22 is "logic 0", and the output of FF23 is "logic 1". The output of NOR
circuit 24 is "logic 0" and the output of NOR circuit 25 is "logic 1". The output of NOR circuit 26, to which the inVerted output of FF20 and the inverted output of ~F23 are applied, is "logic 0" and the output of NOR circuit 28, to which the output of NOR circuit 27 and the pulsé from the minute counter 5 are applied, is "logic 0".
However, though the inverted output of FF20 changes to "logic 0" when the 24th pulse is applied from the minute counter 5, the output of NOR circuit 26 changes to "logic 1", since the inverted output of FF23 remains at "logic 0".
Therefore, the output of NOR circuit 27 changes to "logic 0", and the output of NOR circuit 28 becomes "logic 1" at the end of the 24th pulse and this output resets each of FF18 through FF23. The output of NOR circuit 28, which resets each of FF18 through FF23, changes to "logic 0" when the next pulse - that is 25th pulse - is applied, and the reset condition of each of FF18 to FF23 is released. The sub-sequent actions are repetitive of the above-described sequence.
Thus, 2~ hour measurement is made by having the output of FF18 to FF21, that the counting contents of 1 hour digit from the output terminals 6A to 6D, supplied and also by having the output of FF22 and FF23, that is the enumerated data of 10 hour digit from the output terminals 6E and 6F, supplied. Furthermore, the enumerated data derived from FF18 to FF23 are not, in general, in BCD code, and the conversion of this enumerated data, for instance, into a display signal of 7 segments for display purposes can be made easily.
Referring now to the embodiment of Figure 4, there is shown a dual time-measuring function circuit - the first unction measuring actual time on a 12-hour basis and the second function measuring actual time on a 24-hour basis.

~09~836 In Figure 4, the oscillation output signal produced by the oscillating circuit 101 is converted to a time-standard reference signal by the frequency dividing circuit 2, as described with reference to Fig. 1. The time-standard signal given out from the frequency dividing circuit 2 is applied to a first time counter block 103 comprised of a seconds counter 104, minutes counter 105 and 12-hours counter 106. The standard signal is applied to a secondary time counter block 107 comprised of a seconds counter 108, minutes counter 109 and 24-hours counter 110. Both the seconds counters 104 and 108 count by tens to sixty to supply output signals both for display and to feed the respective minutes counters 105 and 109. The counters 105 and 109 also count by tens to sixty to supply display signals and to feed the respective hours counters 106 and 110. The counter 106 counts to 12 and the counter 110 counts to 24. Adjustment of time or the setting of time is made independently for the first and secondary time counter blocks 103 and 107 by a time adjusting and setting circuit, indicated by the symbol 111.
The counting contents given out as BCD code from the seconds counter 104 of the first time counter block are fed to a gate circuit 112 and the carrier signal is fed to the minutes counter 105. The counting contents given out as BCD code from the minutes counter 105 is fed to a gate circuit 113 and the carrier signal is fed to the hours counter 106. The counting contents given out from the hour counter 106 are fed to a gate circuit 114.
The counting contents given out as BCD code from the seconds counter 108 of the secondary time counter block 107 are fed to the gate circuit 112 and the carrier signal . , ` .

10~92836 is fed to the minutes counter 109. The counting contents given out as BCD code from the minutes counter 109 are fed to the gate circuit 113 and the carrier signal is fed to the hours counter 110. The counting contents given out from the hours counter 110 are fed to the gate circuit 114.
The gate circuit 112 selects one of the data signals it receives from the respective seconds counter 104 or 108 of the first and secondary time counter block 103 or 107, according to the selecting signal applied from the display selecting circuit 115, which will be explained in detail later, and the selected data is fed to a decoder/
driver 116. Similarly, the gate circuit 113 selects one of `the counting content signals it receives from the respective minutes counter 115 or 119 of the first and secondary time counter block 103 or 107, according to the above-mentioned selecting signal, and feeds it to the decoder driver 116.
The gate circuit 11~, similarly, selects one of the counting content signals of the respective hours counter 106 or 110, and feeds it to the decoder driver 116. The counting countent of the first or secondary time counter block 103 or 107, selectively fed to the decoder 116, is changed to a code signal suitable for time display by the display device 117 and is fed to the display device 117 after being amplified to the necessary degree. The display device then displays the time according to the counting contents it receives.
Fig. 5 is a circuit diagram which shows a specific example of the display selecting circuit 115, sh~wn in Fig. 4. The symbol 129 indicates a switch which is manually operated when the display is to be made by selecting the . ~

lO~Z~33~;

counting contents of either the first time counter 103 or the secondaxy time counter 107 (shown in Fig. 4). The terminal 129A of this switch is connected to a high tension connection 130 of the power supply (not shown) and the other terminal 129s is connected to the clock terminal C32 of flip-flop FF132, through a chattering-preventing circuit 131. The output terminal Q32 of FF132 is connected to the first output terminal 115A of the display selecting circuit 115 and the inverted output terminal Q32 is con-nected to the second output terminal 115B.
The action of the display selecting circuit 115 of such construction is explained by referring to the waveform diagram of Fig. 6. In Fig. 6, the suffix "a"
after the numerical symbol given against each waveform shows the voltage level of the respective part of the cir-cuit of Fig. 4.
Assume the output of FF132 was "logic 0" at the time when power is applied to the measuring circuits, including the above described display selecting circuits 115. A switch signal will be produced by operation of the switch 129 and the switch signal - which is free of chattering due to the circuit 131 - is applied to C32 of FF132. The switch signal is represented by waveform 131a.
By application of the first switch signal, the output of FF132 changes to "logic 1" and the inverted output changes to "logic 0". By application of the next switch signal, the output of FF132 changes to "logic 0" and the inverted output changes to "logic 1". In this way, by operation of the switch 129, signals of reciprocally different logic values appear at the output terminals 115A and 115B, respectively, of the display selecting circuit 115 and these 10~2836 signals are fed to the gate circuits 112, 113 and 114 (shown in Fig. 4) as the display selecting signals.
Fig. 7 is a circuit diagram which shows a specific example of the gate circuit 112 shown in Fig. 4. The input terminals, denoted by the symbols 112A and 112B, are connected to the corresponding output terminals 115A and 115B of the display selecting circuit 115f shown in Fig. 5.
The input terminal 112A is connected to the input side of an inverter 133 and also to the gate electrode at each N-channel side of seven transmission gates (herein-after referred to as "TG"), 134, 135, 136, 137, 138, 139 and 140. The output side of the inverter 133 is connected to the gate electrode at each P-channel side of the above-mentioned transmission gates.
The input terminal 112B is connected to the input side of an inverter 141 and also to the gate electrode at each N-channel side of transmission gates 142, 143, 144, 145, 146, 147 and 148. The output side of the inverter 141 is connected to the gate electrode at each P-channel side of transmission gates 142 through 148. And each input terminal of transmission gates 134 through 140, is connected with the output terminals (7 bits) from which the counting contents of the seconds counter 14, shown in Fig. 4, are applied. Each input terminal of transmission gates 142 to 148, is connected with the output terminals (7 bits) from which the counting contents of the seconds counter 18, shown in Fig. 4, are applied.
The output terminals of TG134 and TG142 are c~nnected to the output terminal 112C of the gate circult 112. The output terminals of TG135 and TG143 are connected 10~;2836 to the output terminal 112D. The output terminals of TG136 and TG144 are connected to the output terminal 112E. The output terminals of TG137 and TG145 are connected to the output terminal 112F. The output terminals of TG138 and TG146 are connected to the output terminal 112G. The output terminals of TG139 and TG147 are connected to the output terminal 112H. The output terminals of TG140 and TG148 are connected the output terminal 112I.
When the selected signal of "logic 1" is fed to the input terminal 112A and the selected signal of "logic 0"
is fed to the input terminal 112B, TG134 through TG140 go to the "ON" condition and transmit the counting contents of the seconds counter 14 to the output terminals 112C through 112I. On the other hand, when the selected signal of "logic 0" is fed to the input terminal 112A and the selected signal of "logic 1" is fed to the input terminal 112B, TG134 through TG140 to to the "OFF" condition and TG142 through TG148 go to the "ON" condition. Then the counting contents of the seconds counter 18 are applied to the output terminals 112C through 112I, via TG142 through TG148. Since the selected signal from the display selecting circuit 115, shown in Fig. 5, is applied to the above-mentioned input terminals 112A and 112B, the counting contents of both seconds counters 14 and 18 will not be applied at the same time to the output terminals 112C
through 112I. The construction of the gate circuit 113, shown in Fig. 4, is the same as that of the gate circuit 112. rrhe construction of the gate circuit 114 is similar to the gate circuit 112, but is equipped with transmission ~ates coxresponding in number to the number of output bits of the hours counters 116 and 110.

Thus, the electronic time-piece of this invention 1~)9~336 embodies the first actual time counter 103 which has 12-hours measuring function and the secondary actual time counter 107 which has 24-hours measuring function and the counting contents of these time counters can be displayed selectively on the display device 117 by the operation of the switch of the display selecting circuit 115. Therefore, if the actual-time measurement of time of one's own country is made by the first time counter 103 and that of a certain prescribed region or country is made by the secondary time counter 107, the domestic time can be seen by the 12-hour display in purely conventional manner and the actual time of the prescribed region or country can be seen on a 24-hour display (which does not require knowing whether the secondary time is "AM" or "PM") and can be selected instantly by operation of the switch of the display selecting circuit 115. Also, since the display of the two counting functions can be made selectively by the single display device 117, it has become possible to simplify the mechanism of the display device 117 and to make the display numerals larger than would be the case if more than one display were used, which makes the time reading more accurate.
Fig. 8 is a block diagram showing a further embodiment of the invention. Reference numeral 201 is an oscillation circuit and reference numeral 202 is a fre-quency dividing circuit similar to the elements 101 and 102 of Fig. 4. The reference signal output from the fre~uency dividing circuit 202 is applied to an actual-time counter block 203 comprised of a seconds counter 204, a minutes counter 205 and an hours counter 206.

1~2~336 The reference signal from circuit 202 is also applied to a chronograph counter block 208 consisting of a control circuit 209, a seconds counter 210, a minutes counter 211, and an hours counter 212. Counters 206 and 212 may be 24-hours counters (for example, as shown in Fig. 2) or 12-hours counters.
The counting contents output from seconds counter 204 of said time counter 203 is transmitted to a ON-OFF
controlled gate circuit 214 by means of a display select circuit 213, which is described hereinbelow as to detail, and the output from counter 203 is also fed to the minutes counter 205. The counting contents output from the minutes counter 205 is transmitted to a gate circuit 215 controlled by the display select circuit 213 and the minutes counter output is also applied to the hours counter 206. The output from the hours counter 206 is transmitted to a gate circuit 216 controlled by the display select circuit 213.
The time counter block 203 is settable by means of a time-setting circuit 207.
. The control circuit 209 controlling the chrono-graph 208, which is hereinafter described in more detail, permits the applied reference signal to be controlled by a switching operation so as to be passed through the seconds counter 210. By this switching operation, the control circuit 209 generates reset pulses for resetting all the counters 210, 211, and 212. The counting contents output from the seconds counter 210 is fed to the gate circuit 214 and also to the minutes counter 211. The counting aontents output from the minutes counter is transmitted to the gate circuit 215 and to the hours counter 212. The 10~;2836 counting contents output from the hours counter 212 is applied to the gate circuit 216.
The gate circuit 214 selects either one of the counting contents fed from the seconds counters 214, 210 in response to a selecting signal emitted from the display select circuit 213 and transmits the selected counting contents to a decoder/driver 217. Similarly, the gate circuit 215 selects either one of the fed counting contents of respective minute counters 205, 211 of the time counter 203 and the chronograph 208 in accordance with the above-mentioned selecting signal and the selected counting contents are transmitted to the decoder/driver 217. A
gate circuit 216 also selects either one of the counting contents of the respective hours counters of the time counter block 203 and the chronograph block 208 and transmits the selected counting contents to the decoder/
driver 217. Each counting content of the time counter 203 and the chronograph 208 selectively supplied to the decoder/drivèr 217 is transformed into a signal suitable for displaying the time by a display device 218, and said signal is subjected to a predetermined amplification and transmitted to the display device. Said display device 218 then displays actual or elapsed (chronograph) time, according to counting contents applied thereto.
~ig. 9 is a circuit diagram of an embodiment of the control circuit 209 for controlling the chronograph 208. Reference numeral 230 is a switch for operating the chronograph manually. Input terminal 230A of switch 230 is connected to a high potential terminal 231 of a ~upply voltage supply source. 'rhe other terminal 230B is 10~836 connected to an input of a chattering preventing clrcuit 232. The output side of the chattering preventing circuit 232 is connected to respective clock terminals C33, C34, C35 of flip-flops FF233, FF234, FF235 and also to an input terminal of an inverter 236. Output terminal Q33 of FF233 is connected to a data terminal D34 of FF234 and also to an input terminal of a three-input NOR circuit 237 and output terminal 209A of the control circuit 209. Output pulses from theterminal 209A reset the respective counters 210, 211, 212 of the chronograph (see Fig. 8).
Output terminal Q34 of FF234 is connected to a data terminal D35 of FF235 and also to one input terminal of the above-said NOR circuit 237 and to one input terminal of two-input AND circuit 238 having two inputs. Output terminal Q35 of FF235 is connected to a data terminal D33 of FF233 and at the same time to the remaining input ter-minal of NOR circuit 237. To the other input terminal of NOR circuit 238, a reference signal of 1 Hz is input from the frequency dividing circuit. The output side of AND
circuit 238 is connected to the output terminal 209B of the control circuit 209. Signals applied from this output terminal 209B become the counting signals for the respective counters 210, 211, 212.
The output side of NOR circuit 237 is connected to one input terminal of two-input NOR circuit 239. The output side of this NOR circuit 239 is connected to one input terminal of two-input NOR circuit 240. The output terminal of inverter 36 is connected to the remaining input terminal of circuit 240. The output side of NOR circult ~40 1~
connected to the other input terminal of NOR circuit 239 109~836 and simultaneously to a SET terminal S33 of FF233.
The operation of the control circuit 209 will be explained hereinbelow with reference to the waveform diagram of Fig. 10. Reference numeral 202a is a pulse signal of 1 Hz fed to AND circuit 238 from the frequency dividing circuit 202 (see Fig. 8).
When power is applied to a clock circuit including the control circuit 209, each output of FF33, 34, 35 is logic "0". Accordingly, the output of NOR circuit 237 to which each said output is applied is logic "1". Before switch 230 is closed, the output of chattering preventing circuit 232 is logic ~0~O Consequently, one input side of NOR circuit 240 through inverter 236 is logic "1", and the output is logic "0". When switch 230 is closed, one pulse is output from the chattering preventing circuit 232 and, at the same time, the output of NOR circuit 240 is changed to logic "1", FF33 is set and the output thereof is changed to logic "1". The output of FF33 resets, through the output terminal 209A of the control circuit 209, all the respective counters 210~ 211, 212 of Fig. 8. When the next pulse is output from the chattering preventing circuit 232, the output of FF33 is converted to logic "0" and, simultaneously, the output of FF34 is converted to logic "1". Since a pulse signal of 1 Hz is also applied to the input of AND circuit 238, a pulse signal of 1 Hz is output from circuit 238. Said signal is counted by the respective counters 210, 211, 212 of Fig. 8, the reset condition of which is released by the change in output of FF234.
When the third pulse is applied from the chattering preventing circuit 232, the output of FF234 is converted ~109~:836 into logic "0", and no 1 Hz signal from AND circuit 238 is output. The third pulse changes the output of FF35 to logic "1".
By the operation of the switch 230, a fourth pulse is output from the chattering preventing circuit 232, and the output of NOR circuit 237 remains at logic "0". However, since the data terminal D33 of FF233, that is to say, the output of FF235, is logic "1", the output of FF233 changes to logic "1". The output of F233, as when said first pulse is output, resets the respective counters 210, 211, 212. Thereafter, the outputs of FF234, 235 become successively logic "1" and the above-described sequence is repeated. In this manner, in the control circuit 209, the outputs of FF233 to 235 are changed in order. In the chronograph, when the output of FF233 is logic "1", all of the respective counters 210 to 212 are reset. Whilst the output of FF234 is logic "1", time counting is carr:ied out by said counters 210 to 212 in accordance with the reference signal of 1 Hz. The time counting ceases when the output of FF235 changes to logic "1" .
Figure 11 shows an embodiment of the invention using two 24-hour actual-time functions and a 24-hour chronograph (elapsed-time) function. Referring to Figure 11, the signal produced by the oscillating circuit 301 is converted to the time-standard frequency signal of 1 Hz by the frequency dividing circuit 302 comprised of multiple frequency dividing stages. The standard signal given out from the frequency dividing circuit 302 is fed to the first time counter block 303 comprised of seconds counter 304, ~0~336 minutes counter 305 and 24-hours counter 306. The time-standard frequency signal is also fed to the secondary time counter block 307 comprised of seconds counter 308, minutes counter 309 and 24-hours counter 310. The time-standard frequency signal is also fed to the chronograph composed of control circuit 313, seconds counter 314, minutes counter 315 and 24-hours counter 316. The time adjustment and setting of the above-mentioned first and secondary time counter blocks 303 and 307 are made by the time adjusting and setting circuit 311.
The counting contents produced as BCD code, from the seconds counter 304 of the first time counter block 303, mentioned above, are fed to the gate circuit 317 and the carrier signal is fed to the minutes counter 305. The counting contents produced as BCD code, from the minutes counter 305, are fed to the gate circuit 318 and the carrier signal is fed to the hours counter 306. The counted contents produced from the hours counter 306 are fed to the gate circuit 319.
The counting contents produced as BCD code from the seconds counter 308 of the secondary time counter are fed to the gate circuit 317 and the carrier signal is fed to the minutes counter 309. The counting contents produced as BCD code from the minutes counter 309 are fed to the gate circuit 318 and the carrier signal is fed to the hours counter 310. The counting contents produced by the hours counter 310 are fed to the gate circuit 319.
The control circuit 313, which controls the chronograph 312, feeds, upon closing of a switch, the time-standard frequency signal to the seconds counter 314 .~

' ~ ~', and at the same time, generates the reset pulse to.reset each of the counters, 314, 315 and 316, by closing oper-ation of the afore-mentioned switch. The standard pulse emitted from this control circuit 313 is fed to the second counter 314, and the counting contents produced by the seconds counter 14 are fed to the gate circuit 317. The carrier signal of the seconds counter 314 is fed to the minutes counter 315 and the counting contents produced by the minutes counter 315 are fed to the gate circuit 318.
The carrier signal of the minutes counter 315 is fed to the hours counter 316 and the counting contents produced by the hours counter 316 are fed to the gate circuit 319.
In the gate circuit 317, only one of the counting contents among the counting contents supplied from the seconds counters 304 and 308 of the above-mentioned first and secondary counter blocks 303 and 307 and from the seconds counter 314 of the chronograph 312 is selected by the selecting signal from the display selecting circuit 320 and is fed to the decoder/driver 321. Similarly, in the gate circuit 318, only one of the counting contents among the counting contents supplied from the minutes counters 305, 309 and 315 of the first and secondary time counter blocks 303 and 307 and the chronograph 312 is selected by the selecting signal mentioned above, and is fed to the decoder/driver 321. In the gate circuit 319, only one of the counting contents, among the counting contents supplied from the hour counters 306, 310 and 316 of the first and secondary time counter blocks 303 and 307 and the chrono-graph 312 is selected by the selecting signal mentioned above and is fed to the decoder/driver 321. The selected lO9Z83~i one of the counting contents of the first and secondary time counters and chronograph, is fed to the decoder/
driver 321 and converted to a code signal, suitable for displaying of time by the display device 322. The display device 322 carries out the display operation according tG
the counting contents supplied.
Fig. 12 is a circuit diagram which shows a specific example of the display selecting circuit 320, shown in Fig. 11, and the symbol 345 denotes a switch which is used for selecting the display of counting contents of any one of the first time counter, secondary time counter or chrono-graph of Fig. 11. The input to switch 345 is connected to the high tension terminal 346 of the power supply and the , other end is connected to the input side of a chattering preventing circuit 347. The output side of the chattering preventing circuit 347 is connected to each of the clock ' 48' C49 and C50 of FF348' 349 and 350 res-pectively and also to the input terminal of an invertor 351. The output terminal Q48 of FF348 is connected to data terminal D49 and to one of three input terminals of NOR
circuit 352 and also to the first output terminal 320A of the display selecting circuit 320. The output terminal Q49 is connected to the data terminal D50 of FF350 and to one of the two remaining terminals of NOR circuit 352 and furthermore to the second output terminal 320B of the dis-play selecting circuit 320. The output terminal Q50 of FF350 is connected to the data terminal D48 of FF348 and to the remaining input terminal of NOR circuit 352 and furthermore to the third output terminal 320C of the display selecting circuit 320.

~: .

~09~36 The output side of NOR circuit 352 is connected to one of two input terminals of NOR circuit 353 and the output side of NOR circuit 353 is connected to one input terminal of NOR circuit 354, of which the other input terminal is connected to the output side of the inverter 351. The output side of NOR circuit 354 is connected to the remaining input terminal of NOR circuit 353 and to the SET terminal S48 of FF348.
The operation of the display selecting circuit 320 of such construction is explained by referring to the voltage waveform diagram shown in Fig. 13.
When power is applied to the timepiece circuit, including the display selecting circuit 320, the output of each of FF348, 349 and 350 is at "logic 0". Therefore, the output of NOR circuit 352, to which the output of each of FF348, 349 and 350 is applied, is "logic 1". And before the switch 345 is closed, the output of the chattering pre-venting circuit 347 is "logic 0" and the output side of the inverter 351 is at "logic 1". Thus, it can be seen that the output of NOR circuit 354 is "logic 0". When the switch is closed subsequently, the first pulse will be given out from the chattering preventing circuit 347 and the output of NOR 354 simultaneously changes to "logic 1".

Accordingly, FF348 is set and its output becomes "logic 1".
This output of FF348 appears at the first output terminal 320~.
Next, when the second pulse is emitted from the chattering preventing circuit 347 by closing the switch 34S, the output applied to the data terminal D49 - that is, the output of FF348 ~ was at "logic 1" level. Now, the output of FF349 goes to "logic 1", and the output of FF348 changes to "logic 0". The output of FF349 appears at the second output terminal 320s.
Next, when the third pulse is emitted from the chattering preventing circuit 347 by closing the switch 345, the output which is applied to the data terminal D50 ~
that is the output of FF349 - was at "logic 1" level. Now, the output of FF350 goes to "logic 1", and the output of FF349 changes to "logic 0". The output of FF350 appears at the third terminal 320C.
Next, when the fourth pulse is emitted from the chattering preventing circuit 347 by closing the switch 345, the output of FF348 changes to "logic 1" because the output which is applied to the data terminal D48 ~ that is the output of FF350 ~ was "logic 1", in spite of the output of NOR circuit 350 being "logic 0". That is to say there is no output from NOR circuit 354 when the output of any one of FF348 to 350 is "logic 1". The subsequent events will be repetitive of the foregoing by virtue of the ring counter FF348 to 350, and the "logic 1" signal is supplied successively to the output terminals 320A to 320C.
Fig. 14 is a circuit diagram showing a specific example of the gate circuit 317, shown in Fig. 11. Since the construction and action of other gate circuits 318 and 319, shown in Fig. 11, are the same as those of the gate circuit 317, only the latter will be explained in detail.
The symbols 317A, 317B and 317C, shown in Fig. 14, are the input terminals corresponding to the output ter-~inals of the display selecting circuit 320, and the first output terminal 320A of the display selecting circuit is l~9Z836 connected to the input terminal 317A. The output terminal 320B is connected to the input terminal 317B and the output terminal 320C to the input terminal 317C. The above-mentioned input terminal 317A is connected, through inverter 355, to the P-channel gate electrode of each of sevèn transmission gates (hereinafter referred to as "TG") 356, 357, 358, 359, 360, 361 and 362. The input terminal 317A is also connected directly to the N-channel gate electrodes of TG356 through 362. In the same way, the input terminal 317B is connected, through inverter 363, to the P-channel gate electrodes of TG364 through 370. The input terminal 317B is also con-nected directly to the N-channel gate electrode of TG364 through 370. Furthermore, the input terminal 317C is connected, through inverter 371, to the P-channel gate electrodes of TG372 through 378. The input terminal 317C is also connected directly to the N-channel gate electrodes of TG372 through 378. The seven-bit output of the seconds counter 304, which is included in the first counter block 303 (shown in Flg. 11), is applied to each of TG356 through 362. The seven-bit output of the seconds counter 308 which is included in the secondary counter block 307 is applied to each of TG364 through 370.
Furthermore, the seven-bit output of the seconds counter 314, which is included in the chronograph 12, is applied to each of TG372 to 378. The output side of each of TG356, 364 and .
372 is connected to the output terminal 317D; the output side of each of TG357, 365 and 373 is connected to the output terminal 317E; the output side of each of TG358, 366 and 374 is connected to the output terminal 317F; the output side of each of TG359, 367 and 375 is connected to the output terminal 317G; the output side of each of TG360, 368 and 376 is connected to the output terminal 317H; the output ' 109~.,836 side of each of TG361, 369 and 377 is connected to the output terminal 317I; and the output side of each of TG362, 370 and 378 is connected to the output terminal 317J. In the gate circuit 317 of such construction, when a signal of "logic 1" is applied to the input terminal 317A, TG356 through 362 all go to the ON condition and the counting contents of the seconds counter 304 are applied to the output terminals 317D to 317J. Next, when "logic 1" signal is applied to the input terminal 317B, TG364 through 370 all go to the "ON" condition and the counting contents of the seconds counter 308 are applied to the output terminals 317D
to 317J. Furthermore, when a "logic 1" signal is applied to the input terminal 317C, TG372 through 378 all go to the "ON"
condition and the counting contents of the seconds counter 314 are applied to the output terminals 317D through 317J.
However, since a "logic 1" signal is fed successively to the input terminals 317A through 317C in response to closing of the switch 345 of the display selecting circuit, shown in Fig. 12, there is no possibility that the counting contents of more than two counters will simultaneously be fed to the output terminals 317D to 317J.
Thus, the counting contents of the counter selected in response to the operation of the switch of the display selecting circuit 320 is applied, through the above-mentioned output terminals 317D to 317J, to the decoder/driver 321, shown in Fig. 11. While the above-mentioned gate circuit 317 is equipped with seven transmission gates corresponding to the number of output bits of each of the counters 304, 308 and 314, the gate circuit 319 is e~uipped with eighteen transmission gates - six to a set - because the number of , 109Z:836 output bits of each 24-hours counter 306, 310 and ~16 is six.

.. ..

Claims (2)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An electronic timepiece comprising a time standard oscillator for generating an oscillating signal; frequency dividing means for converting said oscillating signal to a time standard frequency signal; at least first, secondary and additional time counting means comprising a plurality of counter blocks, each said block respectively comprising seconds, minutes and hours counters, the input to each said seconds counter being a signal of said time standard frequency, the input to each said minutes counter being derived from the associated said seconds counter and the input to said hours counter being derived from the associated said minutes counter; means for controlling said additional time counting means to operate as chronograph time counting means; and a plurality of selecting gate circuits, each controllable to select, as its output, one of a plurality of in-puts, each said input derived from said seconds, minutes and hours counter means;
control circuit means connected to said gate circuits for applying a control signal thereto to selectively cause each said gate circuit to provide an output representative of a selected said counter block; and said output from said each gate circuit feeding a decoder/driver circuit means having an output drivingly connected to a common display means for presenting a display representative of the contents of said selected counter block.

2. An electronic timepiece comprising, in combination; an oscillator circuit for generating a repetitive time standard signal having a repetition rate defining a time base; a dividing circuit connected to receive said time standard signal for dividing the same to develop a repetitive output signal having a repetition rate representing passage of time; a primary time counter of the 24 hour type connected for counting the output signal of said dividing circuit for developing a count representative of time and which advances with the passage of time; a secondary time counter of the 24 hour type connected for counting the output signal of said dividing circuit for developing a count representative of time and which advances with the passage of time; a third time counter of the 24 hour type comprised of a plurality of individual counters in cascade for counting the output signal of said dividing circuit; means for applying the output signal of said dividing circuit to selected ones of said counters comprising said third time counter at a certain time and for terminating application of the output signal of said dividing circuit to operate said third counter in a chronograph mode; a time correcting circuit cooperative with said primary and secondary time counters for setting the respective counts of said primary and secondary time counters;
a display circuit responsive to the count of a respective one of said counters for displaying a time represented by the count; and time selecting means for selectively applying the count of a respective one of said counters to said display circuit for displaying a selected time and for operating the timepiece in a time keeping mode or a chronograph mode.