CA1075825A

CA1075825A - Circuit board and method of making

Info

Publication number: CA1075825A
Application number: CA274,360A
Authority: CA
Inventors: Rollin W. Mettler; John H. Mettler; John Impey
Original assignee: CIRCUIT-WISE
Current assignee: CIRCUIT-WISE
Priority date: 1976-04-22
Filing date: 1977-03-21
Publication date: 1980-04-15
Also published as: IT1086737B; DE2715875A1; FR2349255A1; JPS52151866A

Abstract

ABSTRACT

A circuit board comprising a dielectric insulating substrate molded in its finished form with a surface recessed to correspond to the desired circuitry, the recess being filled with conductive metal which is chemically and/or mechanically bonded to the surfaces of the recess. The substrate may be provided with holes filled or lined with conductive metal, and the surface of the circuit may be coated with protective materials, easily removable or otherwise. The process of making the board includes molding the board to its finished form, including a recess in one or more surfaces corresponding to the desired circuitry, with connecting holes if needed; treating the entire surface in preparation for plating; applying a plating resist to the raised land areas of the board; plating the board with copper or other conductive metal to the desired thickness (e.g., into the recess).

Description

~075~25 The inven~ion relates to a circuit board comprising a substrate having conductive metal e~bedded in at least one surEace thereof in the form of one or more circuits, and to the process of making such a board S wherein the substra-te of the board is molded to its ~inished form including recesses corresponding to the desired circuit arrangement and holes, if desired, the land areas between the recesses being covered with a plating resist and the board then being plated to deposit the conductive metal in the recasses and holes, if any, followed by suitable surface treatments.
Traditionally, printed circuit boards have been manufactured utilizing a metal clad laminate substrate.
In an early form, thin sheets of copper foil (.001"-.005") were glued to a phenolic base material, a positive image of the desired circuit was applied to the surface of the copper to serve as an etching resist and the exposed copper was etched away. The resist material was then remove~, holes were drilled or punched as needed and the product was finished by cleaning and applying a water dip lacquer for protec-tion, while retaining solderability. As a natural development of this process copper circuits were applied similarly to both sides of a common substrate.
There was subsequently developed the so-called "plated-through process tl wherein a two sided substrate was drilled, subjected to elec~roless metallic deposi-tion (includ:ing plating through the holes), imprinted with a negative image serving as a plating resist and then electro:Lytically plated with copper followed by ~ ` .

~ . . ~
.
- - . ... . ~ : . .

~75~3~5 tin-leacl or any other finish sul~able as an etch resis-t or protective coatincJ. The pla-ting resist was removed and the board etched to remove the metal covered thereby, while the tin-lead plating acted as an etching resist, to protect the desired circuit elements.
In a simpli~ied version of this process the substrate is activate~, a negative image resist is applied and the circuitry is plated on electrolessly; this being known as an "additive process", for use when a plated-through boarcl is required.
One of the difficulties with the plated-through process is that the apertures in the board must be as smooth and clean as possible in order to maintain the integrity of the plating. Attempts to pieree neatly any ~ 15 and/or all of the substrate material currently available -~ have failed and, while drilling the holes is practical and economical, many customers require openings other than perfect circles for assembly purposes.
In those markets which use massive quantities of plated-through boards, the aforementioned problems have caused considerable difficulty. In addition, in boards such as these, the cost of the substrate amounts to 25% of the cost of the finished product or higher, and are subject to delamination and cracking.
Other known proeesses for manufaeturing eircuit boards, particularly those having a substrate of di-electric material and a eonductive cireuit inlaid in a surface thereof include forming the circuit pattern on a temporary support, embedding it in a substrate and then removlng the support; or plating a moldable 75~5 substrate with metal, embossing the circuit design on the plated substrate and removing the excess metal, or usiny a variety of other e~pedients, all of whlch procedures present one or more disadvantages such as expense, poor adherence, difficult quality control and the like.
Accordingly, it is an object of the present invention to provide a process o making circuit boards by steps which are simple, easy to control with great accuracy, and economy.
It ls a further ob3ect of the invention to provide an inlaid circuit board wherein the circuit elements are bonded chemically and mechanically to the substrate.
It is another object of the invention to provide certain improvements in the form, construction and arrangement of the several parts and in the steps of the process whereby the above named and other objects may effectively be attained The invention accordingly comprises the several steps and the relation of one or more of such steps with respect to each of the others, and the article possessing the features, properties, and the relation of elements, which are exemplified in the following detailed disclosure, and the scope of the invention will be indicated in the claims.
In accordance with a further aspect of the present invention, there is provided the process of making a circuit board which includes, in this sequence, providing a mold having on at least one surface thereof a raised pattern corresponding to the desired circuit pattern and a depressed fla~ land area defining said raised circuit pattern area, molding a dielectric material to form a substrate having a surface recessed in a pattern corresponding to the desired circuit pattern and a flat land area defining the recessed pattern area, applying a plating resist to said land area, and depositing conductive s '' ~0751!~

metal on said recessed pa~tern area to form th~ desired circuit pattern.
In accordance with a further aspect of the present invention, there is provided the process of making a circuit board which includes, providing a mold having on at least one surface thereof a pattern in relief corresponding to the desired circuitry, molding a dielectric material by means of said mold to form a substra-te having a surface recessed in a pattern corresponding to the desired circuitry and a flat land area defining the recessed pattern area, applying a plating resist to said land area, and plating the substrate electrolessly with conductive metal, whereby said recessed pattern area is at least partially filled with conductive metal constituting the desired circuitry, In accordance with a further aspect of the present invention, there is provided the process of makin~ a circuit board which includes, providing a mold having on at least one surface thereof a pattern in relief corresponding to the desired circuitry, molding a dielectric material by means of said mold to form a substrate having a surface recessed in a pattern corresponding to the desired circuitry and a flat land area defining the recessed pattern area, roughening the surface of the substrate, actïvating chemically the surface of the sub-strate, applying a plating resist to said flat land area, leav-ing the recessed circuitry exposed, plating the substrate electrolessly with conductive metal to at least partially fill the recessed pattern area, applying an epoxy solder resist to selected areas of the circuitry, and applying a protective coating to other areas to insure solderability.
A practical embodiment of the invention is shown in the accompanying drawing, wherein:

~3a -, i -: , ~L~75~Z5 FIG. 1 is a flow charl: illustrating schematically the steps for producing a circuit board, FIG. 2 is a detail plan view of a portion of a : ~ - 3b -. . . , ~ ;

. . . . . .. . . ..

~L~75~ZS

typical circuit board, parts being broken away, FIG. 3 is a section taken on the line ~ III of Fig. 2, at one stage in the process, FIGS. 4 and 5 are similar sections showing conditions at other stages of the process.
Referring to the drawinq, and particularly the steps of the method as outlined in the flow chart, FIG. 1:
A. A mold is made corresponding to -the customer's mechanical drawing, the circuit areas being in relief and posts or pins ~eing provided for forming holes of any desired size or shape.
B. The board substrate is molded, using any appro-priate non-conductive material such as filled phenolics or polyphenylene sulfide, for example, having regard for conditions both of use and of manufacture, producing a substrate with the circuit areas depressed and holes, as required~
C. The board is sand blasted, for example, with 240 grit aluminum oxide at 40 psi, and/or chemically roughened (with preferably both) in preparation for plating, the roughness may suitably be on the order of 25 micro-inches. Chemical roughening can be accomplished by degreasing the board with a chlorinated solvent, such as t~ichloroethylene or the like, soaking in an alka~ine soak cleaner/surfactant, such as Enthone's* PC453, or the li~e, followed by rinsing in water and drying, soaking in a solution of dimethylformamide and ethy~ene glycol, followed by rinsing, soaking in a solution of methyl-ethyl ketone and trichloroethylene, * A Tradename of Enthone, Inc., 1900 Frontage Road, West Haven Conn. 06516 , ':

followed again by rinsing, ancl finally exposiny th~ board to an aqueous solution of sulfuric acid and chromium trioxide, with a final water rinse.
D. In preparation for subsequent applications, the board surface is activated chemically. ~s an exarnple, but not limitation, the board may be chemically activated ~y the fol-lowing, or like, steps:
l. soaking in a surfactant, such as MacDermid's*
PA-3, followed by rinsing in water,

2. soaking in a solu-tion of stannous chloride having a colloidal or non-colloidal suspension of palladium chloride, such as Shipley1s Cataprep followed by rinsing in water,

3. soaking in a solution of fluoboric acid with surfactants, such as Shipley's** Accelerator l9 or MacDermid's 9071, followed by rinsing in water;
and

4. baking at about lOO~C for about 30 minutes.
E. A plating resist, such as photosensitive or W
curable polymers, for example Riston, KPR***, or the like, is applied to the raised lands of the board, leaving the de-pressed circuit areas exposed.
F. The board is plated, preferably by electroless deposition, with a conduc-tive material such as copper (alone or over nickel) to the desired thickness, e.g., into the recessed areas and holes. As an example, but not limitation, the board may be plated by the following, or like, steps:
1. optionally, pre-soaking in a solution of fluoboric acid with surfactants, such as * A Tradename of MacDermid Inc., 526 ~Iuntingdon Avenue, Water-bury, Conn. 06720 ** A Tradename of Shipley Inc. 49 Walnut Park, Wellesley, Mass *** A Trademark of Dupont Corp., Wilmington, Delaware 19898 . - - . . . . .
: .

~0758~5 Shipley's ~ccelerator 19 or MaeDermids 9071, Eollowed by rinsing in water;
2. immersing in an elec:troless niekel plating solution, for example, a solution of nickel phosphate with wetting agents and niekel chloride, such as MaeDermid's Eleetroless Niekel 9340, followed by rinsing in water; and 3. immersing in an electroless eopper plating solution, for example a solution of eopper sulfate, formaldehyde, stabilizers, and wetting agent-grain refiners and hydroxide, such as MacDermid 9042, until the desired ; thickness of copper is obtained.
G. The coating and cleaning steps inelude applying an epoxy solder resist to eircuit areas where no solder connection is to be made, eleaning exposed eopper areas, for example by abrasion with pumiee, aluminum oxide, n~lon abrasives or the like, and protecting said areas with a water base laequer, or diluted malie aeid or non-aetive Rosin flux, to provide for solderability. The exposed eopper areas may also be cleaned chemically before applieation of the proteetive water base laequer or the like by the following, or like, steps:
1. soaking in hot alkaline solution, 2. rinsing in eold water 3. soaking in a mild ammonia persulfate dip . rinsing in eold water

5. soaking in 10% sulfurie aeid solution

6. rinsing in eold water, and

7. drying.

107~82~

The board, ~t that pcint, is ready for inspection, packing and shipment. Identification and~or explanatory indicia may convenientl~ be for~ed on the mold, to appear on the finished board as copper plated areas.
Certain significant stages of the process are illustrated in Fig. 2 to 5.
As shown in Fig. 4, a substrate 11 of thermo-plastic insulating dielectric material has been molded into a form having depressed or recessed areas 12 correspondin~ to the paths of the desired circuits and holes 13, 14 have been formed simultaneously, in any desired sizes, shapes and locations. One or both surfaces of the substrate should be recessed in the - areas adjacent each hole, as indicated at 15 and 16, to provide for the annular circuit paths shown in Fig. 2. The non-recessed areas of the surface lie in a common plane and constitute raised lands 17, 18. The substrate has substantially the appearance of Fig. 4 through the steps B, C and D described above. After the - 20 chemical activation of -the surface (step D) a plat ng resist 20, 21 is applied in any convenient manner, to the raised land areas 17, 18 and to the back surface 19, as shown in Fig. 5 (step E), and the substrate is then plated (step F) to deposit copper in the recessed circuit areas 12, and in and around the holes 13, 14, as indicated at 22, 23 and 24, Fig. 3. Recesses around certain holes on the back of the substrate are a~so filled with copper, 25, 26, to provide areas for connecting the circuits to other elements at those points. The plating resist need not be removedl the : , -,:

1~7~8Z~

coatincJ ar.d clealling steps (G) vary in different areas, as explained above, ancl axe not specifically illustrated.
The mold may be single or multiple cavity and may be desigllecl to form depxessed circuit paths in both surEaces of the substrate as well as in one sur~ace.
The holes have a smooth finish, not rough and torn as with punched holes.
The material or the substrate must be able to withstand soldering heat as well as meeting all other requirements; phenolic based plastics are considered ; to be particularly suitable and may be used alone or laminated with other materials.
The plating resist can be applied (step E) in various ways including roller coating or curtain coating. However, in certain cases, a silk screening method might be advisable.
In a modified method, step E (plating resist) is omitted and the entire surface of the substrate is electrolessly plated with metal (step F) ~ollowed by milling or sanding off enough metal to expose the land areas while leaving the metal in the depressed circuit areas and holes, if any. The thickness of the metal constituting the circuits can be built up, if desired, by electroless or electrolytic plating.
In either form of construction the metal consti-tuting the circuit or circuits is securely bonded in pre-formed recesses or depressions and in the molded holes, if any. As suggested above, the conductive circuits may be made with a first electroless nickel plating followed by electroless copper plating until the .
~, 7S13~

desired thickness is obtained.
~ hile circuit boards are conventionally ~lat and rectangular, boards made a.s disclosed herein co~ld, if desired, be made in other shapes including circular, arcuate, or cylindrical shapes. Reference to land areas as "fla-t" is in-tended to include the non-recessed areas of boards having any desired cross-sectional contour. Mention of a circuit includes a plurality of circuits.
Example As an illustrative example of a preferred embodiment of the present invention, a circuit board substrate made of General Electric`s Genal*, which is a filled phenolic material, was molded to correspond to the desired mechanical drawing of the circuit, so that the circuit areas were depressed and appropriate holes of the desired shape and size were provided therein.
The circuit board substrate was then sandblasted with 240 grit aluminum oxide at 40 psi to obtain a structure on the surface of approximately 25 micro-inches. It was then degreased with trichloroethylene to remove dust and grease and allowed to air-dry.
Next, the circuit board substrate was cleaned by soaking for about 5 minutes in a 15% to 20% solution of Enthone's PC453, at about 65C. After a one minute rinse in water, it was dried completely~
The circui board substrate was then soaked for about 5 minutes in a solution comprising about 61% dimethyl-formamide and about 39% ethylene glycol at about 35C, followed by a one minute rinse in water.

* A Trademark of General Electric Corp., 1350 South 2nd Street, Coshocton, Ohio 43812 _g_ 1(3 75825 Next, it was soaked for about 4 minut~s in a solution of about 40% methyl-ethyl-ketone and about 60% trichloroethylene at a temperature of about 30"C, follo~ed by a one minute rinse in water.
The circuit board subst:rate was then immersed in a solution comprised of about S0% sulfuric acid, about 7% chromium trioxide (1 molar) and about 43% distilled water, at a temp-erature of acout 75C, followed by a one minute rinse in water whereafter, it was immersed in an aqueous rinse solution com-prising sodium carbonate (5 molar) for about 5 minutes at about 35C, followed by a one minute rinse in water.
Next, the circuit board substrate was chemically activated, as followso 1) five minute immersion in MacDermid's PA-3 at 2) one minute rinse in water, 3) two minute immersion in Cataprep* at between 43C to 49C, 4) five minute immersion in Cataprep 44 at 43C to 49C, 5) one minute rinse in water, 6) two minute immersion in Shipley's Accelerator 19 at about 22C, 7) one minute rinse in water, and

8) thirty minute bake at about 100C, just prior to imaging.
The activated circuit board was then imaged by application of a plating resist, which was applied to the raised lands of the board, leaving the depressed * A Trademark of Shipley Inc., 49 Walnut Park, Wellesley, Mass ; 02181 --10-- .

~07~8Z5 circuit areas exposecl.
Next, the imaged circuit board was reactivated by immersion for about 15 minu-tes in MacDermid's 9071 at abou-t 22~C, followed by a one minute rinse in wa-ter, and subsequent immersion for approximately 15 minu-tes in MacDermid's Electroless Nickel 9340 at about 32C, followed by one minute rinse in water.
he circuit board was then plated with copper by immersion in MacDermid's 9042 until the desired thickness of copper was obtained.
Finally, -the e~posed copper areas were cleaned by soaking in hot alkaline solution, rinsing in cold water, soaking in a mild ammonium persulfate dip, rinsing in water, soaking in 10% sulfuric acid solution, rinsing in cold water and drying. Thereafter, ; a protective coating of water-dip lacquer was applied.
It will be understood that various changes may be made in the form, construction and arrangement of the several parts and in the steps of the method without departing from the spirit and scope of the invention, and it is accordingly intended that all matter contained in the above description or shown in the accompanying drawing shall be interpreted as illustrative and not in a limiting sense.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. The process of making a circuit board which includes in this sequence, providing a mold having on at least one surface there-of a raised pattern corresponding to the desired circuit pattern and a depressed flat land area defining said raised circuit pattern area, molding a dielectric material to form a substrate having a surface recessed in a pattern corresponding to the desired circuit pattern and a flat land area defining the re-cessed pattern area, applying a plating resist to said land area, and depositing conductive metal on said recessed pattern area to form the desired circuit pattern.

2. The process according to claim 1 which includes roughening the surface of the substrate before applying the plating resist.

3. The process according to claim 2 wherein the roughening is effected by sand blasting.

4. The process according to claim 2 wherein the roughening is effected by a chemical treatment.

5. The process according to claim 2 wherein the roughening is effected by sand blasting and by a chemical treatment.

6. The process according to claim 1 which includes activating chemically the surface of the substrate before applying the plating resist.

7. The process according to claim 2 which includes activating chemically the surface of the substrate after roughening it and before applying the plating resist.

8. The process according to claim 7 which includes applying a solder resist to portions of the circuit areas and cleaning and coating other circuit areas.

9. The process of making a circuit board which includes, providing a mold having on at least one surface thereof a pattern in relief corresponding to the desired circuitry, molding a dielectric material by means of said mold to form a substrate having a surface recessed in a pattern corresponding to the desired circuitry and a flat land area defining the recessed pattern area, applying a plating resist to said land area, and plating the substrate electrolessly with conductive metal, whereby said recessed pattern area is at least partially filled with conductive metal constituting the desired circuitry.

10. The process of making a circuit board which includes, providing a mold having on at least one surface thereof a pattern in relief corresponding to the desired circuitry, molding a dielectric material by means of said mold to form a substrate having a surface recessed in a pattern corresponding to the desired circuitry and a flat land area defining the recessed pattern area, roughening the surface of the substrate, activating chemically the surface of the substrate, applying a plating resist to said flat land area, leaving the recessed circuitry exposed, plating the substrate electrolessly with conductive metal to at least partially fill the recessed pattern area, applying an epoxy solder resist to selected areas of the circuitry, and applying a protective coating to other areas to insure solderability.