CA1066813A - Method of generating addresses to a paged memory - Google Patents

Method of generating addresses to a paged memory

Info

Publication number
CA1066813A
CA1066813A CA245,917A CA245917A CA1066813A CA 1066813 A CA1066813 A CA 1066813A CA 245917 A CA245917 A CA 245917A CA 1066813 A CA1066813 A CA 1066813A
Authority
CA
Canada
Prior art keywords
memory
address
page
page table
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA245,917A
Other languages
English (en)
French (fr)
Inventor
Garvin W. Patterson
Marion G. Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1066813A publication Critical patent/CA1066813A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA245,917A 1975-03-26 1976-02-17 Method of generating addresses to a paged memory Expired CA1066813A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/562,330 US3976978A (en) 1975-03-26 1975-03-26 Method of generating addresses to a paged memory

Publications (1)

Publication Number Publication Date
CA1066813A true CA1066813A (en) 1979-11-20

Family

ID=24245840

Family Applications (1)

Application Number Title Priority Date Filing Date
CA245,917A Expired CA1066813A (en) 1975-03-26 1976-02-17 Method of generating addresses to a paged memory

Country Status (8)

Country Link
US (1) US3976978A (cg-RX-API-DMAC10.html)
JP (1) JPS51120633A (cg-RX-API-DMAC10.html)
BE (1) BE840020A (cg-RX-API-DMAC10.html)
CA (1) CA1066813A (cg-RX-API-DMAC10.html)
DE (1) DE2612054A1 (cg-RX-API-DMAC10.html)
FR (1) FR2305793A1 (cg-RX-API-DMAC10.html)
GB (1) GB1547382A (cg-RX-API-DMAC10.html)
HK (1) HK37580A (cg-RX-API-DMAC10.html)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092715A (en) * 1976-09-22 1978-05-30 Honeywell Information Systems Inc. Input-output unit having extended addressing capability
JPS5448449A (en) * 1977-09-26 1979-04-17 Hitachi Ltd Virtual addressing sustem
US4161026A (en) * 1977-11-22 1979-07-10 Honeywell Information Systems Inc. Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes
US4218741A (en) * 1978-06-23 1980-08-19 International Business Machines Corporation Paging mechanism
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
FR2445988A1 (fr) * 1979-01-02 1980-08-01 Honeywell Inf Systems Dispositif d'adressage perfectionne d'un systeme de traitement de donnees
JPS5734251A (en) * 1980-08-07 1982-02-24 Toshiba Corp Address conversion and generating system
US4410941A (en) * 1980-12-29 1983-10-18 Wang Laboratories, Inc. Computer having an indexed local ram to store previously translated virtual addresses
US4374417A (en) * 1981-02-05 1983-02-15 International Business Machines Corp. Method for using page addressing mechanism
US4455604A (en) * 1981-05-22 1984-06-19 Data General Corporation Digital data processing system having addressing means for translating operands into descriptors identifying data, plural multilevel microcode control means, and ability to execute a plurality of internal language dialects
US4428045A (en) 1981-09-11 1984-01-24 Data General Corporation Apparatus for specifying and resolving addresses of operands in a digital data processing system
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
US4926316A (en) * 1982-09-29 1990-05-15 Apple Computer, Inc. Memory management unit with overlapping control for accessing main memory of a digital computer
US4538223A (en) * 1982-09-29 1985-08-27 Microdata Corporation Computer operand address computation
US4524415A (en) * 1982-12-07 1985-06-18 Motorola, Inc. Virtual machine data processor
US4779191A (en) * 1985-04-12 1988-10-18 Gigamos Systems, Inc. Method and apparatus for expanding the address space of computers
US4821171A (en) * 1985-05-07 1989-04-11 Prime Computer, Inc. System of selective purging of address translation in computer memories
US5317717A (en) * 1987-07-01 1994-05-31 Digital Equipment Corp. Apparatus and method for main memory unit protection using access and fault logic signals
JPH0289132A (ja) * 1988-09-26 1990-03-29 Nec Corp 論理アドレス生成方式
JP2778623B2 (ja) * 1995-07-21 1998-07-23 日本電気株式会社 プリフェッチ制御装置
US5813027A (en) * 1996-03-08 1998-09-22 Vlsi Technology, Inc. Method for storing and transferring wave table audio samples using a DSP cache, a link list structure, and compression
JP4226816B2 (ja) * 2001-09-28 2009-02-18 株式会社東芝 マイクロプロセッサ
US7299460B2 (en) * 2003-05-29 2007-11-20 Nec Corporation Method and computer program for converting an assembly language program for one processor to another
US7590819B2 (en) * 2005-05-09 2009-09-15 Lsi Logic Corporation Compact memory management unit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3270324A (en) * 1963-01-07 1966-08-30 Ibm Means of address distribution
US3510847A (en) * 1967-09-25 1970-05-05 Burroughs Corp Address manipulation circuitry for a digital computer
NL6815506A (cg-RX-API-DMAC10.html) * 1968-10-31 1970-05-04
US3854126A (en) * 1972-10-10 1974-12-10 Digital Equipment Corp Circuit for converting virtual addresses into physical addresses
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
FR130806A (cg-RX-API-DMAC10.html) * 1973-11-21

Also Published As

Publication number Publication date
HK37580A (en) 1980-07-18
FR2305793B1 (cg-RX-API-DMAC10.html) 1980-11-07
DE2612054A1 (de) 1976-10-14
JPS5757783B2 (cg-RX-API-DMAC10.html) 1982-12-06
FR2305793A1 (fr) 1976-10-22
GB1547382A (en) 1979-06-20
BE840020A (fr) 1976-07-16
US3976978A (en) 1976-08-24
JPS51120633A (en) 1976-10-22

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