CA1058766A - Programmable calculator with external magnetic record member - Google Patents

Abstract

IMPROVED PROGRAMMABLE CALCULATOR

Abstract of the Disclosure A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit with a section capable of being defined by plug-in read-only memory modules and stored programs added by the user, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the calculator, and a solid state output display unit capable of displaying three lines of numeric information. An output printer unit capable of printing out every alphabetic and numeric character and many other symbols individually and in messages may also be included with the other input and output units.

Description

~os8766 Background of the Invention This invention relates generally to calculators and improvements therein and more particularly to programmable calculators that may be controlled both manually from the keyboard input unit and automatically by a stored program loaded into the calculator from the keyboard input unit or an external record member.
Conventional programmable calculators generally have less capability and flexibility than is required to meet the needs of many users. For example, they typically cannot be readily expanded and adapted by the user to separately in-crease the amount of program and data storage memory or to perform special keyboard functions oriented toward the en-vironment of the user. They also typically cannot perform indirectly addressed numeric data register transfers and arithmetic without utilizing available working registers for addresses rather than data. This seriously limits their ability to efficiently perform complex operations such as file manipulations or matrix arithmetic. Moreover, they typically have a very limited capability for performing

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.,, direct arithmetic between working and storage memory re-gisters and little or no capability for performing indirect arithmetic between working and storage memory registers.
In some conventional programmable calculators a pro-gram stored within the calculator can be recorded onto an external magnetic record member and can later be reloaded back into the calculator from the magnetic record member.
~owever, data and programs stored within these calculators typically cannot be separately recorded onto an external ~agnetic record member and later separately reloaded back into the calculator therefrom. Moreover, these calculators have no provision for ma~ing a program secure when it is recorded onto an external magnetic record member. Any user may there~ore re-record the program or obtain an indication of the individual program steps once the program is reloaded into the calculator.
Conventional programmable calculators with self-contained output printer units typically have a very limited alpha capability of only a few selected characters confined to certain columns o~ the printer. They are therefore typi-cally unable to print out both a numeric and a distinct mnemonic representation of every program step of every pro-gram stored within the calculator. Furthermore, they are typically unable to print out labels ior inputs to and out-puts from the calculator or messages informing the user how to run programs with which he may be unfamiliar. Such ~eatures would be very help~ul to the user both in editing programs and in ~implifying their use.
In some conventional programmable calculators a pro-gram stored within the calculator may be edited by single stepping forward through the program while viewing an output ~058766 display representing the last-encountered program step and its associated address and, in one case, also the presently-encountered program step and its associated address. How-ever, these calculators typically cannot single step back-ward through the program or display the next program step to be encountered and its associated address. Moreover, they typically have no provision for inserting program steps into the program without reloading portions of the program and no provision for finding every occurrence of any de-signated program step. Such features would also be veryhelpful to the user in editing programs.
Conventional computer systems have or may be pro-grammed to have much more capability than conventional pro-grammable calculators. However, they are larger, more ex-pensive, and less efficient in calculating elementary mathematical functions than conventional programmable cal-culators. Moreover, a skilled programmer is typically required to utilize them. Due to th0se factors, conventional computer systems are best suited for handling large amounts of data or making highly iterative or very complex mathema-tical calculations.

Summary of the Invention An object of an aspect of this invention is to provide an improved programmable calculator that has more capability and flexibility than conventional programmable calculators and that is smaller, less expensive, more efficient in cal-culating elementary mathematical functions, and easier to ~tilize than conventional computer systems.
An object of an aspect of this invention is to provide a programmable calculator in which the amount of program . ~
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~ 058~766 and data storage memory available to the user may be sepa-rately expanded and in which additional program and data storage memory made available to the user is automatically accommodated by the calculator and the user informed when he has exceeded the capacity of either the program or data storage memory.
An object of an aspect of this inven~ion is to provide a programmable calculator in which the functions performed by the calculator may be readily expanded by the user and oriented toward the environment of the user and in which the added functions are automatically accommodated by the cal-culator.
An object of an aspect of this invention is to provide a programmable calculator in which the user may define key-board functions to be performed by the calculator and may protect them from subsequently being inadvertently altered or destroyed.
An object of an aspect of this invention is to provide a programmable calculator capable of employing extensive in- -direct addressing to permit efficient manipulation of files and matrix operations.
An object of an aspect of this invention is to provide a programmable calculator in which thè user may employ either absolute or symbolic addressing and in which program jumps or subroutine calls may be made to absolute or symbolic ad-dresses.
An object of an aspect of this invention is to provide a programmable calculator capable of performing both direct and indirect storage, recall, and exchange between working and storage memory registers.

~(~58766 An object of an aspect of this invention is to provide a programmable calculator capable of performing both direct and indirect arithmetic bidirectionally between working and storage memory registers.
An object of an aspect of this invention is to provide a programmable calculator capable of performing serial binary arithmetic, parallel-by-digit binary-coded-decimal arithmetic, and logic operations.
An object of an aspect of this invention is to provide a programmable calculator in which either programs or data stored within the calculator may be separately recorded on an external magnetic record member and, subsequently, sepa-rately reloaded back into the calculator therefrom.
An object of an aspect of this invention is to provide a programmable calculator in which the user may designate any program stored within the calculator as being secure when it is recorded onto an external magnetic record member for subsequent re-entry into the calculator and in which the user is prevented from re-recording any secure program or obtaining any indication of its individual program steps once it is reloaded into the calculator.
An object of an aspect of this invention is to provide a programmable calculator capable of printing out every alphabetic and numeric character and many other symbols in-dividually and in messages.
An object of an aspect of this invention is to provide a programmable calculator capable of printing out both a numeric and a mnemonic representation of each keyboard entry in a key-log listing.
An object of an aspect of this invention is to provide a 105137~6 programmable calculator capable of printing out a numeric representation of each numeric keyboard entry and calculated numeric result and a mark distinguishing each numeric key-board entry from each calculated numeric result.
An object of an aspect of this invention is to provide a programmable calculator capable of printing out both a numeric and mnemonic representation of each step in a program stored within the calculator and a numeric indication of the address of each program step in a program listing.
An object of an aspect of this invention is to provide a programmable calculator capable of editing programs stored within the calculator more efficiently than conventional programmable calculators.
An object of an aspect of this invention is to provide a programmable calculator in which the user may single step either forward or backward through an internally stored program in a program entering mode to check the program and may single step forward through the program in a program-controlled operating mode to check the program execution.
An object of an aspect of this invention is to provide a programmable calculator in which the last program step en-countered, the program step presently encountered, and the next program step to be encountered, while single stepping either forward or backward through a program stored within the calculator, may be displayed.
An object of an aspect of this invention is to provide a programmable calculator in which the user may insert program steps and automatically locate every occurrence of a de-signated program step in a program stored within the calculator.

~)587~6 other and incidental objects of this invention will become apparent from a reading of this specification and an inspection of the accompanying drawings.
In accordance with one aspect of this invention there is provided a programmable calculator comprising: keyboard input means for entering information, including programs and control commands, into the calculator; memory means for storing information, including programs, that has been entered into the calculator; processing means, coupled to said keyboard input means and memory means, for processing information stored in the memory means to perform selected functions; magnetic reading and recording means for selectively loading a program stored on an external magnetic record member in the mèmory means and recording a program stored in the memory means onto an external magnetic record member; and output means, coupled to the processing means, for selectively providing an indication of the results of information processed by the processing means and a printed listing of a program stored in the memory means; the keyboard input means including program recording control means for designating a program stored in the memory means as being a secure program when that program is recorded onto an external magnetic record member; the processing means including logic means for recognizing a program loaded into the memory means from an external magnetic record member as being a secure program and for subsequently inhibiting the listing and re-recording of that secure program.

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~(~5~37f~6 Disclosed hereinafter is an embodiment in which there is employed a keyboard input unit, a magnetic card reading and recording unit, a solid state output display unit, an output printer unit, an input~output control unit, a memory unit and a central processing unit to provide an adaptable programmable calculator having manual operating, automatic operating, program entering, magnetic card reading, magnetic card recording, and alphameric printing modes.
The keyboard input unit includes a group of data keys for entering numeric data into the calculator, a group of control keys for controlling the va rious modes and operations of the calculator and the format of the output display, and a group of definable keys for controlling additional functions that may be added by the user. All of the data keys and nearly all of the control keys may also be employed for programming the calculator, many of the control keys being provided solely for this purpose. The keyboard input unit also includes a group of indicator lights for informing the user of the status of the calculator. These indicator ;
lights and all of the keys are mounted on a front panel of a housing for the calculator.
The magnetic card reading and recording unit includes a reading and recording head, a drive mechanism for driving a magnetic card from an input receptacle in the front panel of the calculator housing past the reading and recording head to an output receptacle in the front panel, and reading and recording drive circuits coupled to the reading and -8a-10587~i6 recording head for bidirectionally transferring information between the magnetic card and the calculator as determined by the control keys of the keyboard input unit. It also in-cludes a pair of detectors and an associated control circuit for disabling the recording drive circuit whenever a notch is detected in the leading edge of the magnetic card to pre-vent information recorded on the magnetic card from being inadvertently destroyed. Such a notch may be provided in any magnetic card the user desires to protect by simply pushing out a perforated portion thereo~.
The solid state output display unit includes three rows of light emitting diode arrays and associated drive circuits for selectively displaying three separate lines of numeric information. Numeric data may be displayed in either a fixed or a ~loating point format as determined by the con-trol keys of the keyboard input unit.
The output printer unit includes a stationary thermal printing head with a row of resistive heating ele-ments, a drive circuit for selectively energizing each heating element, and a stepping mechanism for driving a strip of thermal-sensitive recording paper past the stationary thermal printing head in seven steps for each line of alphameric in-formation to be printed out. Every alphabetic and numeric character and many other symbols may be printed out indivi-dually or in messages as determined by the control keys o~
the keyboard input unit or by a program stored within the calculator.
The input-output control unit includes a sixteen-bit uni-versal shift register serving as an input-output register into which in~ormation may be transferred serially from the central ~5~766 processing unit or in parallel from the keyboard input and magnetic card reading and recording units and from which in-formation may be transferred serially to the central pro-cessing unit or in parallel to the keyboard indicator lights and to the solid state output display, magnetic card reading and recording, and output printer units. It also includes control logic responsive to the central processing unit for controlling the transfer of information between these units.
The input-output control unit may also be employed to per-form the same functions between the central processing unit and peripheral units including, for example, a digitizer, a marked card reader, an X-Y plotter, a magnetic tape unit, and a typewriter. A plurality o$ peripheral units may be con-nected at the same time to the input-output control unit by simply plugging interface modules associated with the selected peripheral units into receptacles provided therefore in a rear panel of the calculator housing.
The memory unit may employ both direct and indirect decimal and symbolic addressing. It includes a modular random-access read-write memory having a program storage section for storing a plurality of program steps and having a separate data storage section including a plurality of working registers, a plurality of associated display re-gisters, and a plurality of storage registers for manipulating and storing data. These program and data storage sections of the read-write memory may be separately expanded without increasing the overall dimensions of the calculator by the addition of program storage modules or by the alteration of the data storage memory control. Additional read-write memory made available to the user is automatically accommodated 05137~6 by the calculator, and the user is automatically in~ormed when the program or data storage capacity o~ the read-wrlte memory has been exceeded.
The memory unit also includes a modular read-only memory in which routines and subroutines of basic instruc-tions for per~orming the various functions of the calculator are stored. These routines and subroutines o~ the read-only memory may be expanded and adapted by the user to per-~orm additional ~unctions oriented toward the speci~ic needs o~ the user. This is accomplished by simpiy plugging ad-ditional read-only memory modules into receptacles provided therefor in the top panel o~ the calculator housing; Added read-only memory modules are automatically accommodated by the calculator and may be associated with the de~inable keys of the keyboard input unit or employed to e~pand the opera-tions associated with other ~eys. An overlay is employed with each added read-only memory module associated with the de~inable ~eys o~ the ~eyboard input unit to ldentify the additional functions that may then be per~ormed by the cal-culator.
Plug-in read-only memory modules including, for e~ample, an alpha module, a mathematics module, a statistics module, a definable ~unctions module, a~d a typ~writer module may be added to the read-only memorr. The alpha module en-ables the calculator to ~rint out every alphabetic character individually or in messages. ~t employs addresslng enabling it to rede~ine most o~ the ~eys o~ the keyboard input unit so that it may be employed at the same time as other plug-in read-only memory modules. The mathematics module enables the calculator to per~orm trigonometric ~unctions, coordinate 1()58766 transformations, vector arithmetic, and many other mathe-matical functions. Similarly, the statistics module enables the calculator to perform random number generations, ac- `-cumulations of sums, sums of products and sums of squares for up to five variables, linear and multiple linear re-gressions, and many other statistical functions. It also permits the use of a correct key, included among the de-finable keys of the keyboard input unit, to automatically delete data from a statistical analysis. The definable functions module enables the user to store programs of his own choosing in the program storage section of the read-write memory, associate them with some of the definable keys of the keyboard input unit, and protect them from sub-sequently being inadvertently altered or destroyed. It also permits the use of an insert key and a find key, in-cluded among the definable keys of the keyboard input unit, to insert program steps in a program stored in the read-write memory and to find every occurrence of any designated program step in the stored program. The typewriter module enables the calculator to control the entire keyboard of a properly interfaced typewriter.
The memory unit further includes a pair of recir-culating sixteen-bit serial shift registers. One of these registers serves as a memory address register for serially receiving information from an arithmetic-logic unit included in the central processing unit, for parallel addressing any memory location designated by the received information, and for serially transferring the received information back to the arithmetic-logic unit, The other of these registers serves as a memory access register for serially receiving 1~5~7~G

information from the arithmetic-logic unit, for writing in-formation in parallel into any addressed memory location, for reading information in parallel from any addressed memory location, and for serially transferring information to the arithmetic-logic unit. It also serves as a four-bit parallel shift register for transferring four bits of binary-coded-decimal information in parallel to the arithmetic-logic unit.
The central processing unit includes ~our recir-culating sixteen-bit serial shift registers, a four-bit serial shift register, the arithmetic logic unit, a programmabl~e clock, and a microprocessor Two of these sixteen-bit s~erial shi~t registers serve as accumulator registers for serially receiving information from and serially transferring in-~ormation to the arithmetic-logic unit. The accumulator re-gister employed is designated by a control flip-flop. One of the accumulator registers also serves as a four-bit paral-lel shift register for receiving four bits o~ binary coded-decimal information in parallel from and trans~erring four bits oi such information in parallel to the arithmetic-logic unit.
The two remaining sixteen-bit serial shift regis'cers serve as a program counter register and a qualifier register, re-spectively. They are also employed ~or serially receiving information from and serially transferring information to the arithmetic-logic unit. The four-bit serial shift regi-ster serves as an extend register ~or serially receiving in-~ormation ~rom either the memory access register or the arithmetic-logic unit and for serially trans~erring infor-mation to the arithmetic-logic unit.
The arithmetic-logic unit is employed for per-forming one-bit serial binary arithmetic, four-bit parallel :
' binary-coded-decimal arithmetic, and logic operations. It may also be controlled by the microprocessor to perform bi-directional direct and indirect arithmetic between any of a plurality of the working registers and any of the storage registers of the data storage section of the read-write memory.
The programmable clock is employed to supply a variable number of shift clock pulses to the arithmetic-logic unit and to the serial shift registers of the input-output, memory, and central processing units. It is also employed to supply clock control signals to the input-output control logic and to the microprocessor.
The microprocessor includes a read-only memory in which a plurality of microinstructions and codes are stored.
These microinstructions and codes are employed to perform the basic instructions of the calculator. They include a plurality of coded and non-coded microinstructions for trans-ferring control to the input-output control logic, for controlling the addressing and accessing of the memory unit, and for controlling the operation of the two ac-cumulator registers, the program counter register, the ex-tend register and the arithmetic-logic unit. They also include a plurality of clock codes for controlling the operation of the programmable clock, a plurality of qualifier selection codes for selecting qualifiers and serving as primary address codes for addressing the read-only memory of the micropro-cessor, and a plurality of secondary address codes for ad-dressing the read-only memory of the microprocessor. In re-sponse to a control signal from a power supply provided for the calculator, control signals for the programmable clock, and qualifier-control signals from the central-processing los8766 and input-output control units, the microprocessor issues the microinstructions and codes stored in the read-only memory of the microprocessor as required to process either binary or binary-coded-decimal information entered into or stored in the calculator.
In the manual operating mode, the calculator is controlled by keycodes sequentially entered into the cal-culator from the keyboard input unit by the user. The solid state output display unit displays a numeric repre-sentation of the contents of three of the working registersand their associated display registers. These working re-gisters and their associated display registers may contain the last-entered numeric operand and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The out-put printer unit may be controlled by the user to selectively print out a numeric representation of any numeric data entered into the calculator from the keyboard input unit, a numeric representation of any result calculated by the cal-culator, and a mark distinguishing numeric data entries fromcalculated numeric results. If the alpha read-only memory module is plugged into the calculator, the output printer unit may also be controlled by the user to print out labels for inputs to and outputs from the calculator and any other alphabetic in~ormation that may be desired.
~ hen the calculator is in the manual operating mode, it may also be operated in a key-log alphameric printing mode.
The output printer unit then prints out a numeric representa-tion of each keycode as it is entered by-the user. If the alpha read-only memory module is plugged into the calculator, -15_ , lOS8766 the output print~r unit also prints out a mnemonic representa-tion of each such keycode.
In the automatic operating mode, the calculator is controlled by automatically obtaining keycodes stored as steps of a program in the program storage section of the read-write memory. ~uring automatic operation of the cal-culator, data may be obtained from the memory unit as de-signated by the program or may be entered from the keyboard input unit by the user while the operation of the calculator is stopped for data either by the program or by the user.
The solid state output display unit displays the final con-tents of the three working registers and their associated display registers. This may include the final calculated numeric result and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The output printer unit prints out calculated numeric results and other numeric information designated by the program. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out any alphabetic information de-signated by the program.
When the calculator is in the automatic operating mode, the user may also employ a step program control key of the keyboard input unit to single step forward through the program being executed. This enables the user to check the execution oi the program step by step in order to determine whether the program, as entered into the calculator, does in fact carry out the desired sequence of operations In the program entering mode, keycodes are sequen-tially entered by the user into the calculator from the -16_ keyboard input unit and are stored as steps of a program in the program storage section of the read-write memory~ The program may include sequences of program steps that will be intrepreted, when the program is executed, as alphabetic information to be printed out by the output printer unit if the alpha read-only memory module is plugged into the cal-culator. This alphabetic information may include labels for inputs to and outputs from the calculator, alphabetic messages for facilitating the use of the program and the opera-tion of the calculator, or any other alphabetic informationthat may be desired. While the user is entering a program into the calculator in the program entering mode, the solid state output display unit displays a numeric representation of the last-entered program step and its associated address and the addresses of the next two progræm steps to be entered and the present contents of those addresses.
In the program entering mode, the user may also employ the step program control key and a back step control key of the keyboard input unit, to single step either for-ward or backward through any sequence of program steps storedin the program storage section of the read-write memoryO
While the user is single stepping forward or backward through a sequence of program steps, the solid state output display unit displays a numeric representation of the last-encountered program step, the program step presently encountered, the next program step to be encountered, and the addresses of these program steps. If the definable functions read-only memory module is plugged into the calculator, the user may also employ the insert and find keys described above by switching to the manual operating mode. These features 105~3766 greatly facilitate the editing of programs stored in the program storage section of the read-write memory.
When the calculator is in the program entering mode, it may also be operated in a key-log alphameric printing mode. The output printer unit then prints out a numeric representation of each program step and its associated ad-dress as it is entered into the calculator from the keyboard input unit by the user. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of ea¢h such program step.
When the calculator is in the program entering mode, it may also be operated in a list alphameric printing mode.
The output printer unit then prints out a numeric repre-sentation of every program step then stored in the program storage section of the read-~rite memory and a numeric re-presentation of the addresses of those program steps. If the alpha read-only memory module is plugged into the cal-culator, the output printer unit also prints out a mnemonic representation of each such program step.
In the magnetic card reading mode, the magnetic card reading and recording unit may be employed by the user to separately load either data or programs into the calculator from one or more external magnetic cards. Data and programs so loaded are separately stored in the data storage and pro-gram storage sections oi~ the read-write memory.
In the magnetic card recording mode, the magnetic card reading and recording unit may be employed by the user to separately record either data or programs, separately stored in the data storage and program storage sections of 1os8766 the read-write memory, onto one or more external magnetic cards. Programs stored in the program storage section of the read-write memory may be coded by the user as being secure when they are recorded onto one or more external magnetic cards. The calculator detects such programs when they are reloaded into the calculator and prevents the user from re-recording them or obtaining any listing or other indication of the individual program steps.
Description of the Drawings Figure 1 is a front perspective view of an adaptable programmable calculator according to the preferred embodiment of this invention.
Figure 2 is a rear perspective view of the adaptable programmable calculator of Figure 1.
Figures 3A-B are simplified block diagrams of the adaptable programmable calculator of Figures 1 and 2.
Figure 4 is a memory map of the memory unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 5 is a detailed memory map of the dedicated portion of the data storage section of the read-write memory employed in the memory unit of Figures 3A-B and 4.
Figure 6 is a detailed memory map of the dedicated portion of the program storage section of the read-write memory employed in the memory unit of Figures 3A-B and 4.
Figure 7 is a simplified operational logic flow chart illustrating the operation of the microprocessor employed in the central processing unit of Figures 3A-B.
Figure 8 is a plan view of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2 and 3A-B showing how the keyboard input unit may be redefined by an alpha plug-in r~ad-only memory module that may also be employed in the adaptable programmable calculator.
Figure 9 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a definable functions plug-in read-only memory module that may be employed in the adaptable pro-grammable calculator.
Figure 10 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a mathematics plug-in read-only memory module that may be employed in the adaptable programmable calculator.
Figure 11 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a statistics plug-in read-only memory module that may be employed in the adaptable programmable calculator.
Figure 12 (sheet 9) is a plan view of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B
showing how the keyboard input unit may be redefined by a typewriter plug-in read-only memory module that may also be employed in the adaptable programmable calculator.
Figure 13 is a simplified flow chart of the overall control sequence employed for keycode processing in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 14 is a flow chart of the display routine of Figure 13.
Figuresl5A-C are flow charts of the display list building routine of Figure 14.
Figure 16 is a map of the output bit assignment for the seven-segment di~play employed in the adaptable programmable c.alculatGr Ol- Fiyures 1, 2, and 3A-B.
Figure 17 is a map of the display list built in the read-write memory of Figures 3A-B, 4, and 5.
Figure 18 is a map of the internal structure of the display list of Figure 17.
Figures l9A-B are flow charts of the monitor routine employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 20A-B are flow charts of the interpreter routine of Figure 13.
Figures 21A-D are flow charts of the program mode key, run mode key, floating-point display key, and fixed-point display key processing routines, respectively, of Figure 13.
Figure 22 is a map of the status word register of Figure 5 illustrating how it is employed by some of the routines of Figures 21A-D.
Figure 23 is a flow chart of the back step key processing routine of Figure 13.
Figure 24 is a flow chart of the clear key processing routine selectable by the interpreter routine of Figure 13.
Figure 25 is a flow chart of the end key processing routine select-able by the interpreter routine of Figure 13.
Figure 26 is a flow chart of the stop key processing routine select-able by the interpreter routine of Figure 13.
Figure 27 (sheet 23) is a flow chart of the integer x key processing routine selectable by the interpreter routine of Figure 13.
Figure 28 (sheet 22) is a flow chart of the pi key processing - . .
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1~58766 routine se}ectable by the interpreter routine of Figure 13.
Figure 29 (sheet 22) is a flow chart of the clear x key processing routine selectable by the interpreter of Figure 13.
Figures 30A-~ are simpli~ied flow charts o~ the number entry processing routine selectable by the interpreter of Figure 13.
Figures 31A-C are flow charts of portions of the magnitude processing portions of the number entry routine o~
Figures 30A-B.
Figures 32A-B are ~low charts o~ e~ponent processing portions o~ the number entry routine o~ Figures 30A-B.
Figure 33 is a flow chart of the change-sign pro-cessing portion of the number entry routine of Figures 30A-B.
Figure 34 is a ~low chart of the termination portion of the number entry routine of Figures 30A-B.
Figure 35 is a ~low chart of the up-key processing routi~e selectable by the interpreter of Figures 13.
Figure 36 is a ~low chart of the down-key processing routine selectable by the interpreter routine of Figure 13.
Figure 37 is a flow chart of the roll-up key.processing routine selectable by the interpreter routine o~ Figure 13.
Figures 38A-B are simpli~ied flow charts of the re-gister trans~er and register arithmetic routines selectable by the interpreter routl~e of Fig:ure 13.
. Figures 39~-B are ~low charts of the register transfer and automatic address terminat~on routine employed in con-nection with the register transfer arithmetic ~ey processing routine o~ Fig~res 38A-B.
Figure 40 is a fIow chart of the indirect-key pro-cessing routine selectable by the interpreter routine o~ Figure 13.

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Figure 41 is a flow chart of the a- a~d b-register trans~er key processing routines selectable by the inter~reter routine of Figure 13.
Figure 42 is a flow chart of the indirect address computation routine employed in connection with the indirect-key processing routine of Figure 40.
Figure 43 is a flow chart of the deci~al address jump and automatic address termination routine employed in con-nection with the go-to a~d if key processing routines selectable by the interpreter routine of Figure 13.
Figure 44 is a flow chart of the label-key processing routine selectable by the interpreter routine of Figure 13.
Figure 45 is a ~low chart of the i~ key processing routine selectable by the interpreter routine o~ Figure 13.
Figure 46 is a flow chart of the subroutine/return key processing rout~ne selectable by the interpreter routine ~of ~igure 13.
Figures 47A-C are flow charts of the floating point add and subtract key processing routines selectable by the interpreter routine o~ Eigure 13.
Figure 48 is a flow chart of the ~loating point multi-ply key processing routine selectable by the interpreter routine of Figure 13.
Figures 49A-B are flow charts of the ~loating point division key processing routine of Figure 13.
Eigures 50A-C are flo~ charts o~ the floating point square root key processing routine selectable by the inter-preter routi~e of Figure 13.
Figure 51 (sheet 48) is a flow chart of the store routine of Figure 13.

. , , ~ ::,~. -1~58766 Figure 52 (sheet 47) is a flow chart of the ~ounding routine employed in connection with several of the routines selectable by the interpreter routine of Figure 13.
Figure 53 (sheet 47) is a flow chart of the x-squared key processing routine selectable by the interpreter routina of Figure 13.
Figure 54 (sheet 47) is a flow chart of the reciprocal-x key processing routine selectable by the interpreter routine of Figure 13.
Figure 55A-B are ~low charts o the basic ~ormat key processing routine selectable by the interpreter routine o~
Flgure 13.
Figure 56 is a ~low chart o~ a search routine that may be employed in connection with the basic ~ormat key processing routine o~ Flgures 55A-B.
Figure 57 is a memory map illustrating the use o~ the - search routine o~ Figure 56.
Figures 58A-B are flow charts o~ a plotter routine employed in connection with the ~asic ~ormat ~ey processing routine of Figures 5~A-B.
Figure 5g is ~ map o~ a memory register emt~loyed in connection with the plotter routine o~ Figures 58A-B.
Figure 60 is a ~low chart of the program-step re-cording portion o~ the record key processing routine o~
F~gure 13.
Figure 61 is a ilow chart o~ the program-step loading portion of the load key processing routine of Figure 13.
Figure 62 ~s a memory-map o~ the ~ro Fam storage section of tbe read-write memory of Figures 3A-B and 4-6 illustrating how a secure program is destroyed by an unsecure program.

..... .... . . .
"'" ~ , . ~

-Figure 63 is a flow chart of the ~ormat recording portion o~ the record key processing routine o~ Figure 1~.
Figure 64 is a ~low chart o~ the data recording port?on o~ the record key processing routine of Figure 13.
Figure 65 is a flow chart of the data loading portion o~ the load key processing routine oY Figure 13.
Figure 66 is a flow chart showing how a plug-in read-only memory module employed in the adaptable programmable calculator oi Figures 1, 2,and 3A-s can obtain keycordes from a program stored in the program storage section of the read-write -memory o~ Figures 3A-B and 4.
Figures 67A-C show ho~ the print routine accesses code in~ormation stored in tables in the data storage section o~ the read-write memory o~ Figures 3A-s and 4.
Figure~ 68A-B are memory maps of a directi~e table and a code table respectively, in an alpha plug-in :--read-on~ me~or~ mo~ule that may be employed in the adaptable progra~mable calculator o~ Figures 1, 2,and 3A-s.
Figure 69 is a flow chart showing how the printer .code is accessed by an alpha plug-in read-only memory module employed in the adaptable programmable calculator o~ Figures 1, 2,and 3A-s.
~ igures 70A-B are ~low charts o~ the type~riter iormat routine employed ~n connection with the format key processing routine selectable by the interpreter routine o~
- Eigure 13.
Eigure 71 is a memory map o~ a typewriter mnemonic table in a type~riter plug.-in read-only memory module that may be employed in the adaptable programmable calculator o~
Figures 1, 2,and 3A-B~
.

.. . . . .

Figure 72 is a flow ehart o~ a typewriter list routine that may be performed when the typewriter read- ( only memory module is plugged into the adaptable programmable calculator of Figures 1, 2,and 3A-s.
Figure 73 is a flow chart of a typewriter print routine that may be per~ormed when the typewriter read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2,and 3A-s.
Figure 74 is a flow chart o~ a typewriter alpha routine that may be peri'ormed when the typewrlter read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 75 is a ~low chart o~ a definable keycode entry routine employed when the definable ~unctions read-ouly memory module ~s plugged into the calculator.
Eigure 7~ is a flow chart of a protect key processing routine that may be performed when the definable functions read-only memory module is plugged into the calculator.
Figure 77 is a flow chart of a memory search routine that may be performed when the definable functions read-only memory module is plugged into the calculator.
Figures 78A-B are flow charts o~ a de~inable function call~ routine that may be per~ormed when the definable func-t~ons read-only memory module is plugged into the calculator.
Figure 79 is a directive table of the functio~ calls that may be performed by the definabla ~unction calls routine of Figures 78A-B.
Eigure 80 is a flow chart of a definable function return routine employed with the definable ~unction calls routine of Figures 78A-B.

- . - . ,; . .

~058766 ~
Figure 81 is a flow chart o~ a turn-o~-the-~unctio~
light subroutine employed by the deiinable ~unction retur~
routine o~ Figure 80.
Figure 82 is a ~low chart o~ a function stack - checking subroutine employed by the definable ~unction calls routine and the deiinable iunction return routine of Figures 78A-B and 80, respectively.
Figure 83 is a ilow chart o~ a delete-protect routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2,and 3A-g.
Figure 8~ is a flGw chart oi a turn-off-the-delete-light subroutine employed by the delete-prot ct routine of Figure 83.
Figure 85 is a flow chart o~ an empty-the-functiou-stack subroutine employed by the delete-protect routine oi .-. Figure 83.
~igure 8~ is a flow chart oi a find routine that may be performed whe~ the deYinable fu~ctio~s read-only memory ~odule is plugged into the adaptable programmable calculator of Figures 1, 2,and 3A-B.
Flgure 87 is a ~low chart of a get-the-neæt-key sub-routine employed by the ~ind routine of Figure 86.
~igure 88 is a ilow chart of a memory compactor routine that may be perSormed whe~ the de~inable ~unctions read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and ~A-B.
Eigure;89 is a memory map illustrating the use of the : memory compactor subroutine oi Figure 88.
F~gures 90A-C are ~low charts o~ a delete routine that may be periormed when the de~inable fu~ctio~ read-only memory module is plugged into the adaptable progr~mmable calculator o~ Figures 1, 2, and 3A-s.
-27_ 10587f~6 Figures 91A-3 are flow charts of ~n insert routine that may be perfcrmed when tne definable functions read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 92 is a flow chart of an address calculating subroutine employed by the insert routine of Figures 91A-B.
Figures 93A-B are flow charts of a tangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 94A-B are flow charts of an arctangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 95A-B are flow charts of an e-to-the-x-power routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 96 is a flow chart of a natural logarithm x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 97 is a flow chart of a subroutine employed by the tangent x and the e-to-the-x-power routines of Figures 93A-B and 95A-B, respectively.
Figures98A-B are flow charts of a subroutine employed by the tangent x and arctangent x routines of Figures 93A-B and 94A-B, respectively.
Figures 99A-B are flow charts of a subroutine employed by the e-to-the-x-power and natural logarithm x routines of Figures 95A-B and 96, respectively, Figure 100 is a ~low chart of a subroutine employed b~ the arctangent x and natural logarithm ~ routines o~
Figures 94~-~ and 96, respecti~ely.
Figure 101 is a ~low chart of sine and cosine routines that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-s.
Figure 102 is a ~low chart o~ a table f(x) routine that may be performed when the mathematics read-only memory module is plugged into the adaptable progr~mmable calculator o~ Figures 1, 2, and 3A-B.
. .
Figure 103 is a flow chart o~ an arc routine that may be performed when the mathematics read-onlq memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A B.
Figure 104 is a flow chart of an arcsine routine that may be per~ormed when the mathematics read-only memory module ~s plugged into the adaptable programmable calculator of ~igures 1, 2, and 3A-B.
Figure 105 is a flow chart o~ an arccosine routine that may be performed when the mathematics read-anly memory module is plugged into the adaptable programmable calculator .. .
of Figures 1, 2, and ~A-B.
Figure 106 is a ~low chart o~ a con~ers~on to polar coordinates rout~ne that may be performed when the mathe-~matics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-3.
. Figure 107 is a flow chart of a conversion to rec-tangular coordinates routine that may be per~ormed when the -_~9_ s, - ~
.. . . .. . .
..... .

mathematics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1 2 and 3A-B.
Figure 108 is a flow chart of a ten-to-the-x-power routine that may be performed when the mathematics read-only memory module is plugged into the adaptable pro-grammable calculator of Figures 1, 2, and 3A-B.
Figure 109 is a flow chart o~ an absolute ~alue y .routine that may be performed when the mathematics read-only memory module is plugged iuto the adaptable pro-grammab~e calculator o~ Figures 1, 2, and 3A-B.
Figure 110 is a flow chart o~ an x-to-the-y-power routine that may be performed when the mathematics read-o~ly memory module is plugged into the adaptable pro-grammable calculator of Figures 1, 2, and 3A-B.
Figure 111 ~s a ~low chart of a logarithm-to-the-base-ten routine that may be performed when the mathematics .~r.ead~o~L~ ~2mcr!y..mo.duie.is.~1ugged into the adaptable pro-grammable calculator of Figures 1, 2, and 3A-B.
Eigure 112 is a flo~ chart of a routine for converting degrees, minutes, and seconds to degrees that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 113 is a flow chart o~ a routine ~or con~erting degrees to degrees, minutes, and.seconds that may be per~ormed when the mathematics read-onl~ memory module is plugged into the adaptable progra~mable calculator o~ Figures 1, 2, and 3A-B.
Eigure 114 is a flow chart o~ a subroutine employed by the routine.~of Figure ~3~or converting degrees to degrees, minutes,and seconds. ~ .
Figure 115 is a ~low chart oi an x factorial routine _30-- ~, ~ 58766 that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-B.
Figure 116 is a flow chart of a recall routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figuresl, 2, and 3A-B.
. .
Figure 117 is a ~low chart o~ an accumulate plus routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figur~ 1, 2, and 3A-s.
Figure 118 is a ~low chart of an accumulate minus routine that may be employed when the mathematics read-only memory module is plugged i~to the adaptable.programmable calculator of Figur~s 1, 2, and 3A-s.
Figures 119A-B are flow charts of a rounding routine that may be employed whe~n the mathematics read-only memory module is plugged i~to the adaptable prograNmable calculator of Figur~ 1, 2, and ~A-B.
Figure 120 is a flow chart o~ a scale routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-s.
Figure 121 is a flow chart of a subroutine employed by the scale routine o~ Figure 120.
Figure 122 is a ~low chart of a clear routine that may be employed when the mathematics read-only memory module is plugged i~to~the adaptable programmable calculator of . . .
~igures 1, 2, and 3A-B.
Figure 123 is a flow chart of a de~inable f(x) .

~1- ..

10587f~;
routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 124 is a ~low chart o~ a do-loop routine that may be employed when the mathematics read-only memory module is plugged ~nto the adaptable programmable calculator of Figures 1, 2, and 3A-B.
- Figureq 125A-B are flow charts of a summation routine that may be per~ormed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 126 is a ~low chart o~ a correct routine that may be per~ormed when the statistics read-only memory module is plugged into the adaptable programmable calculator o~
Figures 1, 2, and 3A-B.
Figure 127 is a flow chart of a t-pair roùtine that may be performed when the statistics read-only memory module is plugged into the adaptable progxammable calculator o~
Figures 1, 2, and 3A-B.
Figure 128 is a i'low chart o~ a~ x squared routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 129 ~s a rlow chart of a mean ~alue routine.
that may be per~ormed ~hen the statistics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-B.
.
F~gure 130 is a ~low chart of a ma~imum/minimum routine that may be per~ormed when the statistics read-only memory module is plugged into the adaptable programmable ... .
catculator of Figures 1, 2, and 3A-B.
Figure 131 ~s a flow chart of a Yariance routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator - of Figures 1, 2, and 3A-8.

105~3766 Figure 132 is a flow chart of an initiali~e routine that may be-performed when the statistics read-only memory rnodule is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 133 is a flow chart of a regression routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 134 (sheet 113) is a flow chart of a variables routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 135 (sheet 112) is a flow chart of an r2-correlation routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 136 is a block diagram of the microprocessor of Figures 3A-B.
Figures 137A-D are detailed schematic diagrams of the microprocessor of Figures 3A-B and 136.
Figure 137'is a figure map showing how the detailed schematic dia-grams of Figures 137A-D fit together.
Figures 138A-H are detailed flow charts illustrating the operation of the microprocessor of Figures 3A-B, 136, and 137A-D.
Figure 138'is a figure map showing how the detailed flow charts of Figures 138A-D fit together.
Figure 138" is a figure map showing how the detailed flow charts of Figures 138E-H fit together.
Figure 138I shows the macro-instruction coding table, the used data format, and the used address and constants for the micro-processor of Figures 3A-B and 136.
Figure 138J is an instruction table for the microprocessor of Figures 3A-B and 136.
Figure 139 is a block diagram of the programmable clock of Figures 3A-B.
Figures 140A-C (sheets 119 and 129-131) are detailed ~. . . .

~` 105~766 schematLc diagrams of the programmable clock of Figure~ 3A-B
and 139 and of a portion of the input-output control unit o~
Figures 3A-B.
Figure 140' is a figure map showing how the detailed schematic diagrams of Figures 140A-c fit together.
Figure 141 is a ~ave~orm dia~ram illustrating the operation o~ the progra~mable clock o~ Figures 3A-B, 139, and 140A-C.
Figureq 142A-D (sheet 119 and 133-136) are detailed schematic diagrams of the shift register and arithmetic-logic units of Figures 3A-B.
Figure 142' is a figure map sh~wing how the detailed qchematic diagrams of Figures 142A-D ~it together.
Figure 143 is a block diagram o~ the arithmet~c-logic unit o~ Figures 3A-B.
Figure 144 ~s a table o~ the iunction code assignments of the arithmetic-logic unit o~ Figures 142A-D and 143.
Figure 145 is a table o~ i~tegrated circuits that may be employed to co2struct the ~L~ o~ Figures 142A-D and 143.
Figure 146 is a block d~agram of the memory u~t of Figures 3A-B.
Eigure 147 is a table o~ mnemonics used i~ the memory unit o~ Figures 3A-B.
Figure 148 is a schematic diagram o~ the read-write memory o~ Figures 3A-8, 4, and 146.
Figure 149 is a schematic diagram oi one of the add-on read-write memory modules o~ ~i.~ure 146 that may be plugged into the calculator to increase the amou~t of program storage memory available to the user.
Figure 150 is a schematic diagram of the other add-~n read-write memory module oi Figure 146 that may be plugged i~to the calculator to ~urther increase the amou~t o~ program storage memory available to the user.

`\
~058766 Figure 151 is a schematic diagram of the read-only memory of Figures 3A-B, 4 and 146.
Figure 152 is a schematic diagram of the add-on read-only memory modules of Figure 146 that may be plugged into the calculator to increase the number of functions available to the user.
Figure 153 i~ a ~lock diagram of one of the read-only memory chips of Figure~ 151-152.
Figures 154A-D (sheets 119 and 147-150) are ~chematic diagrams of one of the read-only memory chips of Figures 151-152.
Figure 154' is a figure map showing how the detailed schematic diagrams of Figures 154A-D fit together.
Figure 155 is a memory map of the memory unit of Figures 3A-B and 4 illu~trating how it is partitioned into -the read-only and read-write memory chips of Figures 148-153 and 154A-D.
Figure 156 is a flow chart illustrating how the row numbers of the lists storea in the read-only memory chips are computed.
Figure 157 i9 a table of bit numbers and actual bits used in connection with the flow chart of Figure 156.
Figures 158A-D are detailed schematic diagrams of the memory addres3 register of Figures 3A-~ and 146.
Figure 158' is a figure map showing now the detailed ~chematic diagrams of Figures 158A-D fit together.
FigureslS9A-D are detailed schematic diagrams of the -control circuitry of Figure 3 and 146~
- Figure 159' is a figure map ~howing how the detailed schematic diagrams of Figures 159A-D fit together.

, lOS8766 Figure 160 is a waveform diagram illustrating the operation of the control circuitry of Figures 159A-D.
Figures 161A-D (sheets 157 and 163-166) are detailed schematic diagrams of the memory access register of Figures 3A-B and 146.
Figure 161' is a figure map showing how the detailed schematic diagrams of Figures 161A-D fit together.
Figures 162A-D (sheets 157 and 167-170) are detailed schematic diasrams of the input-output register and gating control circuits employed in the input-output control unit of Figure 3.
Figure 162' is a figure map showing how the detailed schematic diagrams of Figures 162A-D fit together.
Figure 163 is a schematic diagram of the source and relationship of the input-output party lines connectqd to the peripheral interface module receiving receptacles of Figure 2.
Figure 164 is a waveform diagram illustrating the operation of the control section of the input-output control unit of Figures 3A-B and 140A-C.
Figure 165 is a flow chart illustrating the operation of the control section of the input-output control unit of Figures 3A-B and 140A-C.
Figure 166 is a schematic diagram of the address code decoding for the output selection portion of the interface module~ employed with the input-output control unit of Figures 3A-B.
Figure 167 i9 a chart listing and defining all of the input-output lines of the input-output control unit of Figures 3A-B.

10587~i Figure 168 is a wave~orm diagram o~ some o~ the out-put signals employed by the input-output control unit and associated interface modules of Figures 3A-B.
Figure 169 is a wa~eform diagram o~ some o~ the input signals employed by the input-output control unit and associated interface modules o~ Figures 3A-B.
~igure 170 is a waveform diagram illustrati~g the operatio~ of the interrupt mode of operation of the input-output control unit of Figures 3A-B.
Figure 17} is a schematic diagram of logic that may be used to i~terface an output peripheral to the input-output control unit of Figures 3A-B.
Figure 172 is a schematic diagram of log~c that may be used to inter~ace an input peripheral to the input-output control unit o~ Figures 3A-B.
- - .
Eigure 173 is a sche~atic diagram o~ logic that may ~
be used to inter~ace an interrupting p~ripheral to the input- :
output control u~lt o~ Figures 3A-s.
Figures 174A-D (sheets 157 and 178-181) are detailed schematic diagrams of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 174' is a figure map showing how the detailed schematic diagrams of Figures 174A-D fit together.
Figure 175 (sheet 180) i9 a schematic diagram of one of the transformer pairs employed in the keyboard input unit of Figures 174A-D.
Figure 176 is a pictorial view o~ a tra~s~ormer employed in the keyboard input unit o~ Figures 3A ~.
F~gure 177 is a schemat~c diagram of the tra~sformer o~ Figure 176.
~igure 178 is a schematic diagram of a portion o~ the .keyboard input unit o~ Figures 174A-D.

Figure 179 (sheet 179) illustrates the required polarities for ~he drive und sense l-ines employed in the keyboard input uri+ of Figures 3A-B and 176.
Figure 180 is a block diagram of the magnetic card reading and recording unit employed in the calculator of Figures 1, 2, and 3A-B.
Figures 181A-G are schematic diagrams of the magnetic card reading and recording unit of Figure 180.
Figure 181' is a figure map showing how the detailed schematic diagrams of Figures 181A-G fit together.
Figure 182 is a block diagram illustrating how the magnetic card reading and recording unit of Figures 180 and 181A-G interacts with the calculator of Figures 1, 2, and 3A-B.
Figure 183 is a block diagram of the output display unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 184A-B are detailed schematic diagrams of the output display unit of Figure 183.
Figure 184' is a figure map showing how the detailed schematic diagram of Figures 184A-B fit together.
Figure 185 is a block diagram of the output printer unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 186 is a cross-sectional view taken along the line A-A in Figure 185.
Figures 187A-B (sheets 191, 197, and 198) are detailed schematic diagrams of the thermal printing head, isolation diodes, four group drivers, and one-of-ten decoder of Figure 185.
Figure 187' is a figure map showing how the detailed schematic diagrams of Figures 187A-B fit together.
Figure 188 is a partial plan view of the thermal printing head of Figure 185.

r 38 11~5876~

- Figures 189A-~ are detailed schematic diagrams of the twenty dot driver~, the internal ten-bit shift register, the motor dr-ivers, the motor drive control circuit, and the printer timing circuit of Figure 185.
Figure 190 is a figure map showing how the detailed schematic diagrams of Figures 189A-D fit together.
Figures l91A-B (sheets 191, 204,and 205) are detailed schematic diagrams of the motor drivers of Figure 185.
Figure 191' is a figure map showing how the detailed schematic diagrams of Figures l91A-B fit together.
Figure 192 illustrates how the output printer unit of Figures 185-131 prints out each character.
Figure 193 is a flow chart illustrating the printing operation of -the output printer unit of Figures 185, 186, 187A-B, 188, 189A-D, and l91A-B.
Figure 194 is a block diagram of the power supply system employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 195 is a detailed schematic of the five volt power supply of Figure 194.
Figure 196 is a detailed schematic diagram of the sixteen, twenty, and twenty-four volt power supplies of Figure 194.
Figures 197A-B are detailed schematic diagrams of the positive and negative twelve volt power supplies of Figure 194.
Figure 198 (sheet 206) is a schematic diagram of an alternative ripple signal circuit that may be employed in the power supply of Figure 195.
Figures l99A-B are block diagrams of an interface module that may be employed to interface a typewriter to the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 199' is a figure map showing how the block diagrams of Figures l99A-B fit together.
Figures 200A-C are schematic diagrams of the interface module of Figures l99A-B.
Figure 200' is a figure map showing how the schematic diagrams of Figures 200A-C fit together.

Description of the Preferred Embodiment _ _ GENERAL DESCRIPTION
Referring to Figures 1 and 2, there is shown an adaptable programmable calculator 10 including both a key-board input unit 12 for entering information into and controlling the operation of the calculator and a magnetic card reading and recording unit 14 for recording informa-tion stored within the calculator onto one or more ex-ternal magnetic cards 16 and for subsequently loading the information recorded on these and other similar magnetic cards back into the calculator. The calculator also includes a solid state output display unit 18 for displaying three lines of numeric information stored within the calculator and a group of indicator lights 19, serving as part of the keyboard input unit, for indicating the status of the calculator. It may also include an output printer unit 20 for printing out alphameric information on a strip of thermal-sensitive recording paper 22. All of these input and output units are mounted within a single calculator housing 24 adjacent to a curved front panel 26 thereof.
As shown in Figure 2, a plurality of peripheral input and output units 28 including, for example, a digl-tizer, a marked card reader, an X-Y plotter, and a type-writer may be connected to the calculator at the same time by simply inserting interface modules 30 associated with the selected peripheral units into any of four receptacles 32 provided therefor in a rear panel 34 o~ the calculator housing. As each interface module 30 is inserted into one of these receptacles, a spring-loaded door 38 at the en-trance of the receptacle swings down allowing passage of ~058766 the interface module. Once the interface module is fully inserted, a printed-circuit terminal board 40 contained within the interface module plugs into a mating edge connector mounted inside the calculator. If any of the selected peripheral units require AC line power, their power cords may be plugged into any of three AC power outlets 42 provided therefor at the rear panel of calculator housing 24.
Referring to the simplified block diagram shown in Figure 3, it may be seen that the calculator also includes an input-output control unit 44 (hereinafter referred to as the I/O control unit) for controlling the transfer of information to and from the input and output units, a memory unit 46 for storing and manipulating information entered into the calculator and for storing routines and subroutines of basic instructions performed by the calculator, and a central processing unit 48 (hereinafter referred to as the CPU) for controlling the execution of the routines and subroutines of basic instructions stored in the memory ùnit as required to process informa-tion entered ~nto or stored within the calculator. The calculator also includes a bus system comprising an S-bus 50, a T-bus 52, and an R-bus 54 for transferring information from the memory and I/O control units to the CPU, from the CPU to the memory and IJO control units, and between different portions of the CPU. It further comprises a power supply for supplying DC
power to the calculator and peripheral units employed therewith and for issuing a control signal POP when power is supplied to the calculator.
The I/O control unit 44 includes an input-output 10587~6 register 56 (hereinafter referred to as the I/O register), associated I/O
gating control circuitry 58, and input-output control logic 60 (hereinafter referred to as the I/O control), I/O register 56 comprises a universal six-teen-bit shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from keyboard input unit 12, magnetic card reading and recording unit 14, and peripheral input units 28 such as the marked card reader via twelve input party lines 62.
Information may also be transferred from I/O register 56 either bit-serially to CPU 48 via S-bus 50 or in parallel to magnetic card reading and recording unit 14, solid state output display unit 18, indicator lights 19, output printer unit 20, and peripheral output units 28 such as the X-Y plotter or the typewriter via sixteen output party lines 64.
I/O gating control circuitry 58 includes control circuits for controlling the transfer of information into and out of I/O register 56 in response to selected ItO qualifier control signals from CPU 48 and selected I/O control instructions from I/O control 60. It also includes an interrupt control circuit 65, a peripheral control circuit 66, a magnetic card control circuit 67, a printer control circuit 68, a display control circuit 6~, and an indicator control circuit 70 for variously controlliny the input and output units and issuing control signals QFG and EBT to I/O control 60 via two output lines 71 and 72. These last mentioned control circuits variously perform their control functions in response to control signal ~F from the power supply, I/O qualifier control signals from CPU 48, I/O control instructions from I/O control 60, and control signals from keyboard input unit 12. Inter-rupt control circuit 65 ~ OS8766 initiates the transfer of information into I/0 registe~ 56 from keyboard input unit 12 or interrupting peripheral in-put units 28 such as the marked card reader and issues a qualifier control signal QNR to CPU 48 via output lines 73.
Peripheral control circuit 66 enables interface modules 30 plugged into the calculator to respond to information from I/0 register 56, control associated peripheral units 28, transfer information to and/or receive information from associated peripheral units 28, and in some cases initiate the transfer of information to I/0 register 56 from the interface modules themselves. Magnetic card control circuit 67 enables magnetic card reading and recording unit 14 to respond to information in I/0 register 56 and either read information into I/O register 56 from a magnetic card 16 or record information onto a magnetic card 16 from I/0 register 5~. Printer control circuit 68, display control circuit 69, and indicator control circuit ? enable output display unit 18, output printer unit 20, and indicator lights 19, respectively, to respond to information from I/O register 56.
When a basic I/0 instruction obtained from memory unit 46 is to be executed, CPU 48 transfers control to I/0 control 60 by issuing a pair of I/0 microinstructions PTR
and ~T~ thereto. In response to these I/0 microinstructions from CPU 48, control signal P~F from the power supply, control signals Q~G and EBT from I/0 gating control circuitry 58, and I/0 qualifier and clock control signals from CPU 48, I/0 control 60 selectively issues one or more I/O control in- :
structions to gating control circuitry 58 as required to execute the basic I/0 instruction designated by CPU 48 and iO58766 issues control signals TT~, XTR, QRD, and SCB to CPU 48 via output lines 74-77. The I/O qualifier control signals issued to I/O control 60 and gating control circuitry 58 by CPU 48 are derived from the basic ~/O instruction to be executed. Those qualifier control signals issued to I/O
control 60 designate the specific I/O control instructions to be issued by I/O control 60, while those issued to gating control circuitry 58 designate selected control circuits to be employed in executing the basic I/O instruction.
Memory unit 46 includes a modular random-access read-write memory 78 (hereinafter referred to as the RWM), a modular read-only memory 80 (hereinafter referred to as the ROM), a memory address register 82 (hereinafter re-ferred to as the M-register), a memory access register 84 (hereinafter referred to as the T-register), and control circuitry 85 for these memories and registers. RWM 78 and ROM 80 comprise MOS-type semiconductor memories. As shown in the memory map of Figure 4, they are organized into eight l,024-word pages. The basic RWM 78 contains a data storage section 86 of 512 sixteen-bit words extending from - address 1000 to address 1777 on page O and a separate pro-gram storage section 88 of 512 six-bit words extending from address 12000 to address 12777 on page 5. All addresse~ on the memory map are represented in octal form.
Data storage section 86 contains 49 ~our-word storage registers available to the user (as user addresses 000-048) for manipulating and storing data, 60 additional four-word storage registers that may be made available to the user (as user addresses 049-108) for the same purpose, and 76 words dedicated for use by CPU 48. The 60 additional four-word storage registers may be made available to the lOS8766 user by altering a control routine in the R0~ section 80.
This is accomplished by removing a top panel 90 of the calculator housing s~own in Figure 1, removing a printed cirouit board.containing the control routine to be altered, and substituting another printed circuit ~oard conta~ning the altered control routine. Additional data storage modules made available to the user are automatiea1ly ac-co.~.~odated by the calculator.
As shown in the more detailed memory map of ~igure 5, the dedicated portion of data storage section 86 includes 12 words ~addresses 1750-1753, 1740-1743, and 1760-1763) employed as "X", "Y", and "Z" i'our-woxd working registers available to the user and 8 words (addresses 1764-1773) employed as '!a" and ~'b" ~our-word storage reg~sters available to the user. It also includes 8 words (addresses 1744-1747 and 1754-1757) employed as "ARl" and "AR2" ~our-word working registers for performing binary-coded-decimal arithmettc;
12 words (addresses 1664-1677) empl~yed as three ('tTl~", 'IT2''', and "T3"') or more temporary storage regi~ters i~
connection with a definable section 91 of keyboard input unit 12 ~see Figure 1); 16 words (addresses 1720-1737) employed as four ("Tl", "T2n, "T3", and "T4") or more tem-porary storaæe registers in connection with the remai~ing sect~ons o~ the keyboard input unit; 7 ~ords ~addresses ln 1-17173 employed as a variable-length "system subroutine stack!' for storing return addresses required by programs stored i~ ROM 80 and as temporary storage ~or housekeep~ng inform~tion required by CPU 48; one wor~ ~address 1~77) em-.
ployed as a "system stac~ pointer"; 5 words taddresses ~702-1706) employed as a "user subroutine stack" ~or storing -- .

1~8766 return addresses required by programs entered into program storage section 88 of RWM 78 by the user; 1 word (address 1710 employed as a "user stack pointer"; 1 word (address 1701) employed as a "user program counter" for program steps entered into program storage section 88 by the user; 1 word (address 1707) employed as an "address of user ~p~0" register for storing the first address available to the user in program storage section 88; 1 word (address 1700) employed as a "microprocessor store" register for storing housekeeping information required by CPU 48; 1 word (address 1774) employed as an "interrupt store" register for storing information displaced from CPU
48 by some keyboard entries; 1 word (address 1775) employed as an "input buffer" register for storing keyboard information awaiting entry into CPU
48, and 1 word (address 1776) employed as a "status word" register for storing information regarding the present state of the calculator.
As shown in the memory map of Figure 4, program storage section 88 of RWM 78 contains 500 one-word program step registers available to the user (as user addresses 0000-0500) for storlng programs and 12 words dedicated for use by CPU 48. An additional 1,536 one-word program-step registers may be made available to the user (as user addresses 0511-2Q36) in steps of 512 words (addresses 13000-13777) and 1,024 words (addresses 14000 to 15777).
This is accomplished by removing top panel 90 of the calculator housing shown in Figure 1 and plugging additional program storage modules into the calculator. Added program storage modules are automatically accommodated by the calculator.
As shown in the more detailed memory map of Figure 6, the dedicated portion of program storage section 88 includes 1 word (address 12013) employed as a "security word" register for storing a code designating a program stored in program storage section 88 as being secure. It also includes 1 word (address 12000) employed as an "exe-cution flag" register for storing information indicating whether CPU 48 is being controlled by a program stored in the program storage section or by the keyboard input unit;
2 words (addresses 12001-12002) employed as "normalize ~ flag" and "print flag" registers for storing information about numeric data being processed by CPU 48; 3 words (addresses 12003-12005) employed as "temporary display" re-gisters for storing housekeeping information about the character position, decimal position, and register loca-tion of numeric information being displayed by the output display unit; 1 word (address 12006) employed as a "print code buffer" register for storing housekeeping information about alphameric information being printed out by the out-put printer unit; and 4 words (addresses 12007-12012) available for other uses.
As shown in the memory map of Figure 4, the basic ROM 80 contains 2,048 sixteen-blt words extending from .
address 0000 to address 0777 on page 0, from address 4000 to address 5777 on page 2, and from address 16000 to address 16777 on page 7 Routines and subroutines of basic in-structions for performing the basic functions of the cal-culator and constants employed by these routines and sub-routines are stored in these portions of ROM 80. An ad-ditional 3,072 sixteen-bit words of ROM may also be added . on pages 1, 3, and 4 in steps of 512 and 1,024 words This is accomplished by simply inserting plug-in ROM modules 92 into receptacles 94 provided therefor in top panel 90 of the calculator housing as illustrated in Figure 1 by the partially-inserted plug-in ROM
module on the left. As each plug-in ROM module 92 is inserted into one of these receptacles a spring-loaded door 95 at the entrance of the receptacle swings down allowing passage of the plug-in ROM module. Once the plug-in ROM module is fully inserted as illustrated by the plug-in ROM module on the right, a printed circuit terminal board 96 contained within the plug-in ROM module plugs into a mating edge connector mounted inside the calculator.
A handle 98 pivotally mounted at the top end of each plug-in ROM module 92 facilitates removal of the plug-in ROM module once it has been fully inserted into one of the receptacles 94.
Routines and subroutines of basic instructions (and any needed constants) for enabling the calculator to perform many additional functions are stored in each plug-in ROM module 92. The user himself may therefore quickly and simply adapt the calculator to perform many additional functions oriented toward his specific needs by simply plugging ROM modules of his own choosing into the calculator. Added plug-in ROM modules are automatically accommodated by the calculator and associated with definable section 91 of keyboard input unit 12 or employed to expand the functions performed by this and other sections of the keyboard input unit.
Referring again to Figure 3, M-register 82 of the memory unit com-prises a recirculating sixteen-bit serial shift register into which information may be transferred bit-serially from CPU 48 via T-bus 52 and out of which information may be transferred bit-serially to CPU 48 via S-bus 50. In-formation shifted into M-register 82 may be employed to address any word in RWM 78 or ROM 80 via fifteen output lines 106.
T-register 84 of the memory unit comprises a recirculating six-teen bit serial shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from any ad-dressed word in RWM 78 and ROM 80 via sixteen parallel input lines 108.
Information may be transferred from T-register 104 either bit-serially to CPU 48 via S-bus 50 or in parallel to any addressed word in RWM 78 via sixteen parallel output lines 110. The four least significant bits of information con-tained in T-register 104 may comprise binary-coded-decimal information and may be transferred from the T-register in parallel to CPU 48 via three parallel output lines 112 taken with S-bus 50.
The control circuitry 85 of the memory unit controls these transfers of information into and out of M-register 82 and T-register 84, controls the addressing and accessing of RWM 78 and ROM 80, and refreshes RWM 78. It performs these functions in response to memory microinstructions, memory clock pulses, and shift clock pulses from CPU 48.
CPU 48 includes a register unit 114, an arithmetic-logic unit 116 (hereinafter referred to as the ALU), a programmable clock 118, and a micro-processor 120. Register unit 114 comprises four recirculating sixteen-bit shift registers 122, 124, 126, and 128 and one four-bit shift register 130.
Shift registers 122 and 124 serve as sixteen-bit serial accumulator registers (hereinafter referred to as the A-register and the B-register, respectively) into which information may be transferred bit-serially from ALU
116 via T-bus 52 and out of which information may be trans-ferred bit-serially to ALU 116 via ~-bus 54. The four least significant bit positions of A-register 122 also serve as a four-bit parallel accumulator register into which four bits of binary-coded-decimal information may be trans~erred in parallel from ALU 116 via four parallel input lines 132 and out of which four bits of binary-coded-decimal informa-tion may also be trans~erred in parallel to ALU 116 via three parallel output lines 134 taken with ~-bus 54.
Shift register 126 serves as a sixteen-bit system program counter (hereinafter re~erred to as the P-register) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via ~-bus 54. In-formation contained in the least significant bit position of P-register 126 may also be transferred as a quali~ier control signal QP0 to microprocessor 120 via output line 135.
Shift register 128 serves as a sixteen-bit qualifier register (hereinafter referred to as the Q-register) into which information may be transferred bit-serially from ALU
116 via T-bus 52 and out of which information may be trans-ferred bit-serially to ALU 116 via ~-bus 54. Information contained in the five least-significant bit positions of Q-register 128 is transferred to I/0 gating control circuitry 58 as ~ive one-bit I/0 qualifier control signals Q00-Q04 via ~ive parallel output lines 136, and information contained in the six next-least-significant bit positions 1058~766 of the Q-register is transferred to I/0 control 60 as six one-bit I/0 qualifier control signals Q05-Q10 via six parallel output lines 138. Similarly, information contained in the seven least-significant, the ninth and eleventh least-significant, and the most-significant bit positions of Q-register 128 and information derived from the thirteenth, fourteenth, and fifteenth bit positions of the Q-register may be transferred to microprocessor 120 as eleven one-bit microprocessor qualifier control signals Q00-Q06, Q08, Q10, Q15, and QMR via eleven output lines 140. Information contained in the twelfth through the fifteenth least-significant bit positions of Q-register 128 may be trans-ferred to microprocessor 120 as a four-bit primary address code via four parallel output lines 142.
Shift register 130 serves as a four-bit serial extend register (hereinafter referred to as the E-register) into which information may be transferred bit-serially either from ALU 116 via T-bus 52 or from the least-significant bit position of T-register 84 via input line 144. In-formation may also be transferred out of E-register 130 to ALU 116 Yia ~-bus 54.
Register unit 114 also includes control circuitry 146 for controlling the transfer of parallel binary-coded-decimal information into and out of A-register 122 and the transfer of serial binary informatlon into and out of A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130. This is accomplished in response to register microinstructions from microprocessor 120, control signals ~T~ and ~T~ from I/0 control 60, and shift clock control pulses from programmable clock 118 Control circuitry 146 includes a flip-flop 148 (hereinafter referred to as the A/B flip-flop) for enabling the transfer of information into and out of either the A-register 122 or the B-register 124 as determined by the state of the A/B
flip-flop. The state of A/B flip-flop 148 is initially determined by information Qll transferred to the A/B flip-flop from the twelfth least-significant bit position of Q-register 128 but may be subsequently complemented one or more times by microinstruction CAB ~rom microprocessor 120.
ALU 116 may perform either one-bit serial binary arithmetic on data received from T-register 84 or M-register 82 via ~-bus 50 and/or from any register of register unit 114 via ~-bus 54 or four-bit parallel binary-coded-decimal arithmetic on data received from T-register 84 via output lines 112 taken with ~-bus 50 and/or from A-register 122 via output lines 134 taken with R-bus 54.
It may also perform logic operations on data received from memory unit 46 and/or register unit 114 via any of these linesO The arithmetic and logic operations performed are designated by ALU microinstructions from microprocessor 120 and are carried out in response to these microinstructions, shift clock control pulses ~rom programmable clock 118, and control signal SCB from I/0 control 60. Information is also transferred from ALU 116 to A-register 122 Yia output lines 132 or to I/0 register 56, M-register 82, T-register 84, or any register of register unit 114 via T-bus 52 in response to microinstructions and control signals applied to these registers. If a carry results while ALU 116 is performing either one-bit serial binary arithmetic or four-bit Rarallel binary-coded-decimal arithmetic, the ALU issues a corresponding .. :~. .

10~8766 qual~fier control si~nal QBC a~d QDC to microprocessor 120 via one o~ two output lines 152 and 154~.
Program~able clock 118 includes a crystal-co~trolled system clock 156, a cloc~ decoder and generator 158, and a control gate 160. System clock 156 issues regularly re-curring clock p~lses to clock decoder and generator 153 via output line 162. In response to these regularly recurring clock pulses from system clock 156 and to four-bit clock codes from microprocessor 120~ cloc~ decoder a~d generator 158 issues trains o~ n shift clock pulses to A~ 116, ~-register 82, T-register 82, and all o~ the registers o~
register unit 114 via output line 164. These tralns o~ n shi t clock pulses are employed for shi~ting a correspond~ng number of bits of serial informatio~ into or out o~ any o~
these reg~sters or for shi~ting a carry bit in the AL~. The num~er n OI pulses in eac~ OI t~ese trains may v~ry ~rom one to si~teen as determined by the ~umber of bits of serial ~n~ormation required during each operatio~ to be per~ormed.
In response to a control signal ~ from microprocessor 120, co~trol gate i60 prevents any shi~t clock pulses ~rom being applied to the ALU or any of these registers. ~pon comp}etion of each train of n shift cloc~ pulses, cloc~ decoder and generator lS8 issues a ROM clock pulse to microprocessor 120 via output line 166 and an I/0 clock pulse to.I/0 control 60 via output line 168. In response to the regularly re- -c ing.cloc~ signal from system clock.56, clock decoder and generator l58 also lssues correspondingly regularly recurring -. memory clock pulses to memory unit 46 ~ia output.line 170. ~ -croprocessor 120 selectively issues t~o I/0 .- . .
microinstructions to I/0 control 60 via two output lines .

~058766 172, six memory microinstructions to memory unit 46 via six output lines 174, thirteen register microinstructions to register unit 114 via thirteen output lines 176, and five ALU microinstructions to ALU 116 via five output lines 178. It also issues a four-bit clock code associated with each of these microinstructions to clock decoder 158 via four output lines 180. These microinstructions and associated clock codes are issued as determined by the control signal POP from the power supply, the eleven microprocessor quali-fier control signals from Q-register 128, the four-bit primary address codes from Q-register 128, and the flve microprocessor qualifier control signals from I/O control 60, interrupt control 65, ALU 116, and P-register 126.
As shown in the simplified flow chart of Figure 7, microprocessor 120 executes a hardware diagnostic routine (stored within the microprocessor itself) in response to the control signal POP. Upon completion o~ this diagnostic routine, ALU 115 issues the qualifier control signal QBC in-dicating whether or not the diagnostic routine was suc-cess~ul, microprocessor 120 thereupon responds to this qualifier control signal by entering the basic machine operating loop and issuing microinstructions causing a six-teen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128.
Microprocessor 120 thereupon sequentially responds to one or more additional quali~ier control signals by issuing microinstructions and associated clock codes for executing the instruction then contained in Q-register 128 and causing another sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to the . .

Q-register. When an instruction requiring multiple branching is contained in Q-register 128, microprocessor 120 issues a pair of microinstructions ~ and ~TR causing the micro-processor to respond to a four-bit primary address code from the Q-register by issuing additional microinstructions and associated clock codes for executing the instruction contained in the Q-register.
As illustrated by the basic machine operating loop shown in the flow chart of Figure 7, microprocessor 120 initially responds to the qualifier control signal QNR
either by issuing microinstructions and associated clock codes for interrupting the basic machine operating loop and executing an I/0 service routine or by issuing microinstruc-tions and associated clock codes for loading A/B flip-flop 148 with the information Qll contained in Q-register 128.
The manner in which microprocessor 120 responds is deter-mined by the condition of the qualifier control signal ~NR, which in turn indicates whether or not the basic machine operating loop should be interrupted.
Assuming the basic machine operating loop is not to be interrupted, microprocessor 120 loads the information Qll into AfB flip-flop 148 and responds to the qualifier control signal QMR either by issuing microinstructions ~or transierring an address portion of the instruction contained in Q-register 128 from T-register 84 lnto M-register 82 or by responding to another qualifier control signal Q15.
Again, the manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QMR, which in turn indicates whether or not the instruction contained in Q-register 128 is a memory reference instruction.

10587~6 Assuming the instruction contained in Q-register 128 ls a memory re~erence instruction, microprocessor 120 transfers the required address in~ormation into the M-register 82 and responds to qualifier control signal Q10 either by issuing microinstructions and associated clock codes to select the base page of the memory ti.e. page 0) or by issuing microinstxuctions and associated clock codes to select the current page o~ the memory (i.e. the page ~rom ~hich the instruction contained in Q-register 128 was obtained). In either case, the microprocessor then issues microinstructions as required to read data ~rom the preset page of the memory at the address designated by the address in~ormation last trans~erred into ~-register ~2. Upon completion o~ this operation, m~croprocessor 120 responds to quali~ier control sig~al Q15 by issuing additional micro-instructions and associated clock codes to execute an in-direct memory access operation if the condition o~ this quali~ier control signal indlcates that the address informa-tio~ contai~ed in ~-register 82 is ind~rect.
Assuming the address in~ormation contained in M-register 82 is direct (or upon completion o~ the indirect memory access operation), m~croprocessor 120 issues micro-instructions and associated clock codes causing ~he micro-processor itsel~ to respond to a iour-bit primary address code ~rom the Q-register. The microprocessor responds by ssuing additional microinstructions and associated ~lock codes ~or executing whichever one o~ ten possible me~ory re~erence instructions is contained in Q-register 128 and designated by the four-bit primary address code.
Following execution o~ the designated memory reference . .

instruction, microprocessor 120 issues microinstructions and associated clock codes causing another sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and trans- -ferred from there to Q-register 128 thereby beginning another cycle of the basic machine operating loop.
As illustrated by other possible paths of the basic machine operating loop shown in Figure 7, microprocessor 120 sequentially responds to other qualifier control signals when other types of instructions are contained in Q-register 128. For example, when an I/O instruction is contained in Q-register 128, microprocessor 120 sequentially responds to qualifier control signals QNR, QMR, Q15, Q10, and QRD by issuing microinstructions and associated clock codes to execute the I/O instruction. It should be noted that the microprocessor qualifier control signals not shown in the simplified flow chart of Figure 7 are variously contained within those flow chart blocks requiring decisions as will hereinafter become apparent.

~058766 KEY OPERATIONS
All operations per~ormed by the calculator may be controlled or initiated by the keyboard input unit and/or by keycodes entered into the calculator from the keyboard input unit, the magnetic card reading and recording unit, or peripheral input units such as the mar~ed card reader and stored as program steps ln the program storage section of the RWM. The calculator responds to keycodes in basically the same manner whether obtaining them from the keyboard input unit or ~rom the program storage section o~ the RW~.
An operational description o~ the keyboard input unit is there~ore ~ow given with speci~ic reference to Figures 1 and 8 e~cept as othsrwise indicated.
Line Switch . .
An on-of~ line switch 182, which may be considered as part o~ the keyboard input unit, controls the applica-tion o~ power to the calculator and hence initiation of the control sig~al POP ~rom the power supply. The ~ndicator lights 19 serve as a pilot light since at least two o~ them are always tur~ed on ~hile power is applied to the cal-culator.
~s shown ~n Figure 2, the calculator may be operated at 230, 200, 115, or 100 volts ~ 10% as determined by a pair of line voltage selector switches mounted at rear panel 34 o~ the calculator housing and at a line ~re~uency within the range of 48 to 66 ~ertz. The calculator is provided ~ith a 6-amp ~use and either a l-amp fuse ~or operatio~ at a line voltage o~ 200 ~or 230 volts I lOZ or a 2-amp ~use ~or opera~
tion at a line voltage of 100 or 115 volts ~ 10%. It is~
also provided with a three-conductor power cable 184 which, . .

~058766 when plugged into an appropriate AC power outlet, grounds the calculator housing. The maximum power consumption of the calculator is 150 voltamps. No more than a total of 610 voltamps may be drawn from AC power outlets 42 pro-vided for peripheral units 28.
Mode Keys (RUN7 PRGM, EEY LOG) When the calculator is first turned on, it is automatically initialized and placed in a manual operating mode. If the calculator is switched to some other opera-ting mode, it may subsequently be placed in the manual operating mode again by simply depressing the RUN mode key.
In the manual operating modej operation of the calculator is manually controlled by the user from the keyboard input unit. During this mode the output display unit displays a decimal numeric representation of the contents of the x-, y-, and z-registers (or of associated memory registers in which the actual or intended contents o~ the x-, y-, and z-registers are temporarily stored and, for simplicity of description, are then considered to be the contents of the x-, y-, and z-registers). The contents of the x-, y-, and z-registers are displayed adjacent to the corresponding register designators "keyboard x","accumulator y", and "temporary z", respectively, in the display window. De-pression of the RUN mode key also conditions the calculator for operation in an automatic operating mode, a first key-log printing mode, a program-list printing mode, a magnetic card reading mode, and a magnetic card recording mode as determined by other keys hereinafter explained. A run in-dicator light 19 positioned immediately below the RUN mode key is turned on when the calculator is operating in any of the RUN modes.
The PR&~ mode ~ey is depressed to place the cal-culator in a program entering mode. In this mode keycodes sequentially entered by the user ~rom the keyboard input unit are stored as program steps i~ successive program-step registers o~ the program storage section o~ the RWM as speci~ied by the user program counter. As described above, 500 program-step registers (user addresseæ 0000-0499) are available, and 1536 additional program-step registers (user addresses (0500-2035) may be made available, to the user ~or this purpose. The program step register into which each program step is to be stor~d and from which each program step is to be obtained in any program-related operation is always speci~ied by the user program counter. Thus, be~ore entering a program or subprogram ~nto the calculator, the user program counter must be set to the address o~ the pro-- gram step register into which it is desired to store the initial program step of the program or subprogram to be entered (this address is hereinaft~r referred to as the de-sired starting address nnnn o~ the program). This may be ac-complished, when the calculator is in a keyboard-controlled ru~ mode, by de~ressing the G0 T0 key followed by the decimal-digit keys 0-9 specifying the desired starting address nnnn o the program. If the desired starting address is 0000, this may also be accomplished, when the calculator is in the manual operating mode by simply depressing the END
key ~ i -O~ce the user program counter is set to the desired starting address nnnn, the ussr may proceed t~ enter the pro-gram or subprogram by sequentially per~orming basically the -10~8766 same key operations that he would normally per~orm in the manual operating mode. Thus no special language need be learned to program the calculator. ~uring the program entering mode the output display unit displays a decimal numeric representation of the last-entered program step and its associated address and the addresses of the next two program steps to be entered and the present contents of those addresses.
Depression o~ the PRGM mode key also conditions the calculator ~or operation in a second key-log printing mode and the program-list printing mode as determined by other keys hereinafter explained. A program mode indicator light 19 positioned immediately below the PRGM mode key is turned on when the calculator is operating in any of the P~GM
modes.
The KEY LOG mode key is depressed, when the cal-culator is in the manual operating mode, to place the cal-culator in the first key-log printing mode. In this mode, the output printer unit prints out an octal numeric repre-sentation of each keyboard operation as it is performed by the user. This provides a permanent record of all keyboard operations (including regular data print-out operations), as illustrated by the following example:
Keyb ~ Key log - ~ 27

3 03 -, . .

1~58766 Keyboard entry (Cont'd) Key log (Cont'd)

4 04 + 33 P~INT
~P~E 45

5.00000 If the alpha ROM module enabling the calculator to print out every alphabetic character and many symbols indivi-dually or in messages is plugged into the calculator, the output printer unit also prints out a mnemonic represen-tation of each keyboard operation as it is performed by the user This is illustrated by the following example:
Keyboard entry Key log 20. + + 33 PRI~T PNT 45 5.00000 In the firæt key-log printing mode the output display unit displays the same information as during the manual operating mode.
The KEY 10G mode key is depressed, when the cal-culator is in the program entering mode, to place the calculator in the second key-log printing mode. In this 105876~i mode the output printer unit prints out an octal numeric representation of each keycode as it is entered into the calculator from the keyboard input unit and a decimal numeric representation of the address at which each such keycode is stored as a program step in the program storage section of the RWM. This provides a permanent record of all keyboard-entered program steps, as illustrated by the following example:
Keyboard entry Key log ~ 0003 --------- 27 4 0005 ~ ---- 04 + 0006 --------- 33 x~y 0008 ------___ 30 pRI T 0009 --~~~~~~~ 45 If the alpha ROM module is plugged into the calculator, the output printer unit also prints out a mnemonic representa-tion of each keyboard-entered program step. This is illus-trated by the following example:
Keyboard entry Key log . _ ~ 0003-- UP --- Z7 ,.... .

Keyboard entry (Cont'd) Key log (Cont'd) + 0006-- ~ --- 33 x~y 0008-- XEY ---- 30 PRINT O009L_ PNT --- 45 In the second key-log printing mode the output display unit displays the same in~ormation as during the program entering mode.
The KEY LOG mode key is a toggling on-of~ key (i.e.
repeated depressions of the key alternately switch the calculator in and out o~ either the ~irst or the second key-log printing mode). A key-log indicator light 19 positioned i~mediately below the KEY LOG mode key is turned on when the calculator is operating in either key-log printing mode Program Keys (LIST LOAD~ RECORD) The LIST program key is depressed, when the cal-culator is in the manual operating mode, first key-log print-ing mode, second key-log printing mode, or program entering mode, to place the calculator in the program-list printing mode. In this mode, the output printer unit prints out an octal numeric representation of keycodes then stored as program steps in the program storage section o~ the RWM and a decimal numeric representation o~ the addresses of these program steps. These program steps and addresses are printed out in a list beginning with the address initially 1058'766 specified by the user program counter and ending with the address specified by the user program counter when an END
program step is encountered or the STOP key is depressed.
The user may select the starting address nnnn of the list by depressing the GO TO key followed by the decimal digit keys (0-9) designating the desired starting address nnnn, or simply by depressing the END key if the starting address is 0000. Similarily, the user may terminate the list at any time by depressing the STOP key. When the program-list operation is terminated either by an END program step or by depression of the STOP key, the calculator reverts to its original manual operating, first or second key-log printing, or program entering mode. If the program-list operation is terminated by an END program step, the user program counter specifies the address of the END program step. However, if the program-list operation is terminated by depression of the STOP key, the user program counter specifies the address of the next program step to have been encountered had the STOP key not been depressed.
The list printed out by the output printer unit serves as a permanent record of a sequence of program steps stored as a program, subprogram, or part thereof in the program storage section o~ the RWM and the address o~ these program steps. A typical list is illustrated by the right- and left-hand columns of numbers printed out on the strip of thermal-sensitive recording paper 22. If the alpha ROM module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each o~ these program steps. This is illustrated by the central column of alpha-meric characters printed out on the same strip of thermal-sensitive recording paper.

105~766 The LOAD program key is depressed, when the cal-culator is ln the manual operating mode or the ~irst key-log printing mode, to place the calculator i~ the magnetic card reading mode. During this mode, program steps re-corded on one or more external magnetic cards 16 are read by the magnetic card reading and recording unit and stored in the program storage section o~ the RN~. In order to properly accomplish this program loading operation:
1. The user program counter is set ~o the desired starting address nnnn o~ the program storage section to be loaded. This may be accomplished by depressing the ~0 T0 key ~ollowed by those decimal degit keys designating the desired starting address nn~ or simply by depressing the END key if the desired starting address is OC00.
2. A recorded magnetic card 16 inserted into an input receptacle 186 of the magnetic card reading a~d re-~ording ~nit with the f~rst side 187 to be read placed in the operative reading and recording positio~ as shown in Figure 1.
3. The ~OAD key is depressed, thereby causing the magnetic card reading and recording u~it to begin reading the ~irst recorded ~ide o~ the mag~etic card and turning on an INSERT CARD indicator l~ght 19 positioned ~mmediately below and between the LOAD and RECORD program keys. This program reading operation will terminate and the INSERT
CARD indicator light will turn off wh~n an END (i.e. terminating) program step is read~ The calculator will thereupon revert .~.
to the original manual operating or first key-log printing mode ~ith the user program counter specifying the address o~ the END program step. In any ca~e, the magnetic c~rd will be partially ejected at an output receptacle 188 of the magnetic card readîng and recording unit after each reading pass has been completed.
4. I~ the INSERT CARD indicator light remains on and the magnetic card reading and recording unit continues to run, the partially ejected magnetic card is retrieved ~rom output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into input receptacle 186 with the next side 189 to be read placed in the operative reading and recording position. The magnetic card reading and recording unit thereupon begins reading this next recorded side. This program reading operation is repeated, i~ necessary, until it is terminated by reading an END program step. If desired, program reading operation may also be terminated by depressing the STOP key. The calculator will thereupon also revert to the original manual operating or ~irst key-log printing mode, but with the user program counter specifying the address o~ the next program step to have been read and loaded into the program storage section of the RWM had the program reading operation not been so termi-nated.
When the program reading operation is terminated by t an END program step, the user program counter is left speci-~ying the address of this END program step so that additional program steps, subprograms, and programs may be chain-loaded into the calculator without extra e~fort by simply repeating steps 2, 3, and 4 above. The ~irst additional program step will over-write the last encountered END program step there-by leaving only a final END program step at the completion 10587~6 of the composite program. Similarly~ when the program reading operation is terminated by depressing the STOP key, the user program counter is also left specifying the address of the next program step to have been read so that ad-ditional program steps, subprograms, and programs may also be chain-loaded by simply repeating steps 2, 3, and 4 above.
The RECORD program key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to place the calculator in the magnetic card recording mode. During this mode program steps stored in the program storage section of the RWM
are recorded on one or more external magnetic cards by the magnetic card reading and recording unit. In order to properly accomplish this program recording operation:
1. The user program counter is set to the starting address nnnn of the stored program to be recorded. This may be accomplished by depressing the GO TO key followed by the decimal digit keys designating the required address nnnn, or simply by depressing the END key if the starting address is 0000.
2. A magnetic card 16 is inserted into input re-ceptacle 186 of the magnetic card reading and recording unit with the ~irst side 187 of the card to be recorded placed in the operative reading and recording position as shown~
3. The RECORD program key is depressed, thereby causing the magnetic card reading and recording unit to be-gin recording the stored program onto the first side of the magnetic card and turning on the INSERT C M D indicator light 19. This program recording operation will terminate and the INSERT CARD indicator light turn off when an END

lOS8766 program step is recorded. The calculator will thereupon revert to the original manual operating or first key-log printing mode with the user program counter specifying the address of the END program step. In any case, the magnetic card will be partially ejected at output receptacle 188 of the magnetic card reading and recording unit a~ter each recording pass has been completed.
4. If the INSE~T C~RD indicator light remain9 on, and the magnetic card reading and recording unit continues to run, the partially e;ected card is retrieved ~rom output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into input receptacle 186 with the next side 189 to be recorded placed in the operative reading and recording position.
The magnetic card reading and recording unit thereupon be-g~ns recording on this next side. This program recording operation is repeated, if necessary, until it is terminated by recording an END program step. If no END program step is encou~tered, the calculator will continue to request more magnetic card recording passes until 2,036 program stcps are recorded, regardless of the actual amount o~ pro-gram storage me~ory installed in the calculator. I~ de-sired, the recording operation can be terminated at any ti~e by depressing the STO~ key. The calculator will there-upon also revert to the original manual operating or ~rst key-}og printing mode but with the user program counter le~t speci~ylng the address of the next program step to have been recorded had the recording operation not been so termi-nated.
Once the progr~m is recorded on one or both sides :

lOS8766 of one or more magnetic cards 16, it may be protected against undesired erasures by punching out a perforated portion 190 at the leading edge of each side on which it is recorded.
If a protected (notched) magnetic card is inserted into input receptacle 186 of the magnetic card reading and re-cording unit and the RECORD key depressed, the STATUS
(error) indicator light 19 will turn on and will remain on while the magnetic card reading and recording unit drives the magnetic card to output receptacle 188, whereupon the STATUS light will be extinguishedO Nothing will be recorded on the protected magnetic card during this recording pass nor will there be any impairment of the calculator itself or the information previously recorded on the protected magnetic card. The calculator and the magnetic card unit will simply continue to wait for a nonprotected magnetic card to be inserted into input receptacle 186 for the mag-netic card reading and recording unit.
Automatic Operating Mode Control Keys (CONTINUE STOP~ END PAUSE) The CONTINUE key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to start the automatic execution of a program or sub-program stored within the program storage section of the RWM. Automatic execution begins at the address specified by the user program counter. Thus, in order to execute a desired program or subprogram stored within the program storage section of the RWM
1. The user program counter is set to the starting address nnnn of the desired program or subprogram. This is accomplished by depressing the GO TO key followed by those decimal digit keys designating the starting address 10587~6 nnnn of the desired programO If the starting address is 0000, this may be accomplished by simply depressing the END keyO
2 The CONTINUE key is depressed, when the cal-culator is in the manual operating mode or the first key-log printing mode, to place the calculator in the automatic operating mode and begin automatic execution of the stored program or subprogram at the address nnnn speci~ied by the user program counter. Automatic execution will continue until a STOP or END program step is encountered or a STOP
key is depressed as described below.
The STOP key is depressed, when the calculator is in the automatic operating mode, to halt the automatic execution of a stored program or subprogram immediately after completion of the program step then being executed.
Automatic execution of a stored program or subprogram is similarly halted when a STOP program step is encountered.
In either case the calculator will thereupon revert to the original manual operating or first key-log printing mode with the program counter specifying the address of the next program step to be encountered. The user may then operate the calculator in the manual operating mode to enter data required by the program being executed or to per~orm other calculations. So long as the user does not depress the GO TO or END key or perform some other opera-tion altering the last setting of the user program counter, he may resume automatic operation of the calculator at any time by simply depressing the CONTINUE key again.
As described above, the STOP key may also be de-pressed, when the calculator is in the program-list printing .. .. . . . ~ .

mode, the magnetic card r ~Q ~7m6oe, or the magnetic card recording mode to halt the program-list printing operation, the magnetic card reading operation or the magnetic card recording operations, respectively. In each of these cases the calculator will revert to the mode it was in immediately prior to the halted operation with the user program counter speci~ying the address o~ the next program step to have been printed, read, or recorded had the STOP key not been depressed.
The END key is depressed, ~hen the calculator is in the manual operating mode, to set the user program counter to address 0000 in the program storage section of the RWM (this is equivalent to depressin~
the GO To, o, o, o, and o keys). An E~D program step terminates the automatic execution o~ a stored program by the calculator and resets the user program counter to the first a~ailable address 0000 in the program storage section o~ the-RtnM. The calculator thereupon reverts to the original manual operating or first key-log printing mode, ~rom ~hich automatic operation ~as initiated. Auto-matic execution may then be resumed by depressing the CONTINUE key, if the desired starting address is 0000 or by repeating steps 1 and 2 described above in connection with the CONTINUE key i~ the desired starting address is not 0000. An END program step also clears any subroutine return-address to which return has not by then been made.
~s describe~ above, it also terminates the program listing, magnetic card ~eading, and magnetic card recording opera-tions. -The PAUSE key is typically used only as a program 1058~766 step. Autom~tic execut~ion of a stored program or sub-program is automatically halted for a 1/4 second pause interYal whenever a PAUSE program step is encountered or the PAUSE key is depressed. This enables part~al results of a calculation to be displayed by the output display unit during automatic execution of the stored program or subprogram. Successive PAUSE program steps may be employed to increase the d~ration of the pause interval by 1/4 second increments. Automatic execution of the stored pro-gram or subprogram automatically resumes after the pause interval.
A PA~SE program step may also be used as a con-ditional stop permitting the user to stop,the automatic operation o~ the calculator ~mmediately a~ter execution o~
any PA~SE program step. This is accomplished by simply depressing any key (other than STOP) during automatic eæ cu~ion o~ the program until the PAUSE program step has been executed. In other words, a P~USE program step im-mediately followed by depression of any key other tha~ STOP
has the same effect as depressing STOP, with the ad~antage that automatic eæecution of a stored program or subprogram may thereby be precisely halted at one or more predetermined program steps if the user so desires. Automatic execution of the stored program may then be resumed by depressing the CONTI~UE key. -Decimal Display Keys (FiOATt FIg () ) These keys are employed to control the for~at of numbers displayèd by the output display unit when the caI-culator is in the manual operating and first key-log printing modes. Either a fixed or a floating decimal point format . ~
1058~66 may be used. A fixed point indicator light 19 positioned immediately below the FIX () key is turned on when the fixed decimal point format is being used. Similarly, a floating point indicator light positioned immediately below the FLOAT key is turned on when the floating decimal point format is being used.
In the fixed decimal point format, numbers appear in the form in which they are most commonly written. The decimal point is fixed in its correct position. In the floating decimal point format, numbers appear in a normalized form with the decimal point located immediately after the most significant non-zero digit of the normalized number.
Each normalized number is followed by an exponent comprising a positive or negative power of ten and representing the number of digit places that, and the direction in which, the decimal point must be moved to express the normalized number in the fixed decimal point formatO The following examples illustrate the relationship between numbers ex-pressed in both the fixed and floating decimal point for-mats.
FIXED DECIMAL FLOATING DECIMAL
POINT FORMAT POINT FORMAT
_ _ _ _ 1234.5 =1.2345 x 103 0.0012345 =1.2345 x 10-3 -1.2346 ~-1.2345 x 10 When the calculator is turned on and automatically initialized, the output display unit displays numbers in the floating decimal point format. If the output display is switched to the fixed decimal point format, it may subsequently be switched back to the floating decimal point format by simply depressing the FLOAT key. Every ~058766 number displayed in the floating decimal point ~ormat in-cludes the sign (if negative) and ten most significant digits of the normalized number followed by the sign ~if negative) of the exponent and two exponent digits. This is illustrated by the following examples:

NUMBERS TO FLOATING DECIMAL
BE DISPLAYED _POINT DISPLAY

1234.5 10234500000 03 0.0012345 1.234500000 -03 -1.2345 -1.234500000 00 The output display may be changed to the fixed decimal point format by depressing the FIX () key followed by a decimal digit key designating the desired number n (0-9) of digits to be displayed to the right of the decimal point. Less significant digits are not displayed, and the least significant digit to be displayed is rounded up if the nondisplayed next least significant digit is five or greater.
This is illustrated by the following examples for different values of n:

BE DISPLAYED OF n POINT DISPLAY

123.456784 2 123.46

-6.703256 2 -6.70 123.456784 5 lZ3.4567 -6.703256 5 -6.70326 123.456784 0 123.

-6.703256 0 -7.
If the FIX () key is depressed but not followed by a decimal digit key, the calculator will automatically treat the next key depressed as being the O key (i.e. n will thereupon equal O as in the last example).

105~376~

Numbers of up to (and including) ten significant digits and their signs (if negative) may be displayed in the fixed decimal point format. Thus, (lO-n~ digits may be displayed to the left of the decimal point. If a number to be displayed has more than (lO-n) digits to the left of the decimal point (i.e. is too large for the selected value of n), the display of that number (not the whole display) overflows and thereupon reverts to the floating decimal point format. This is illustrated by the fixed decimal point display of Figure l wherein the numbers con-tained in the x and Y registers have overflowed and are therefore displayed in the floating decimal point format.
It is also illustrated by the following example:

NUMBER TO VALUE ACTUAL
BE DISPLAYED OF n NUMBER DISPLAYED
12345~7.89 5 1.23456789 06 If the first non-zero digit of a number to be displayed is more than n digits to the right of the decimal point (i.e~
is too small for the selected value of n), the display of that number (not the whole display~ underflows. In this case only zeros will be displayed. This is illustrated by the following example:

NUMBER TO ~ALUE ACTUAL
BE DISPLAYED OF n NUMBER DISPLAYED
0.0000012 3 o.ooo Regardless of the way in which numbers are displayed, the calculator always stores all numbers and performs all calculations in the floating decimal point format. Further-more, regardless of the number of digits entered or displayed, each number is stored with twelve significant digits, their ~OS8766 associated sign, a two-digit exponent, and its associated sign. Up to (and including) ten significant digits, their associated sign, the two-digit exponent, and its associated sign can be displayed (however, no sign is displayed for positive numbers or exponents). The remaining two digits (called guard digits) are not displayed. They are employed to maintain greater than ten-place accuracy during cal-culations and also to automatically round the tenth dis-played digit.
The calculator has a dynamic range o~ from +10 98 to +9.999999999(99) x 1098. Whenever this range is ex-ceeded during a calculation the STATUS indicator light 19 turns on.
Numeric Data Entry Keys (0-9), . ENTER EXP CHG SIGN ~) The decimal digit.keys 0-9 are depressed to enter numbers into the x-register. Numbers are entered serially, the last digit entered becoming the least significant digit.
For example, the number 1325 is entered by sequentially depressing the decimal digit keys 1, 3, 2, and 5, A number entered into the x-register is terminated as soon as any non-data-entry key is depressed. Another number entered into the x-register will automatically replace a terminated number, but will become a part of any non-terminated number.
The decimal point (.) key is depressed to enter the decimal point into the x-register. For example, the number 1.234 is entered by sequentially depressing the 1, ., 2, 3, and 4 keys. Regardless of the display format, it is not necessary to use the decimal point key when entering integers.
I~ the decimal point key is not used, the decimal point will be assumed to have followed the last-entered digit. When the fixed decimal point display format is used, the cal-culator automatically positions the decimal point. Simi- ;
larly, when the floating decimal point display format is used the calculator automatically corrects the exponent according to the position of the decimal point.
The ENTER E~P key is depressed ~ollowed by one or two decimal digit keys to enter a one- or two-digit exponent (power of ten) into the x-register, the last digit entered becoming the least significant digit. I~ a third dig~t is entered, it ~ill terminate entry of the exponent and beg~n a new numeric data entry. A non-terminated number in the x-register may be multiplied directly by successive powers of ten by simply entering successive e~-ponents. For example, the product o~ 8.3 x 102 x 1014 may be obtained by sequentially depressing the 8, ., 3, ENTER
E~P, 2,ENTER ~, 1, and 4 keys. If the ENTER E~P key is depressed as the first key o~ a numeric data entry (i.e.
before any of the decimal digit keys have bee~ depressed or following a term~na~ed number),the number 1 is entered into the x-register. Eor example, the number 1 ~ 1016 may be entered by depressing the ENTER EXP, 1, and 6 keys.
The CHG SIG~ key is depressed to change the sign of any terminated or unterminated number in the x-register.
If the CHG SIGN key ~s depressed as the first key of a numeric data entry, it changes the sign o~ the number then in the x-register (whatever the sign may be) and, once that number is replaced by the first digit o~ the new data entry, it prefaces the new data entry with a negati~e sign.
This is illustrated by the following example:

--77_ 105876~;

KEYS DEPRESSED CONTENTS OF x-REGISTER
-123.45 CH~ SIGN 123O45 6 -6.

7 -67.
The CHG SIGN key is also depressed immediately following the ENTER EXP key (or the last-entered digit of the exponent) to enter negative exponents into the x-register. For example, the number 8.3 x 10 2 x 104 x 10 12 may be entered by sequentially depressing the keys 8, ., 3, E~TER EXP, CHG SIGN, 2, ENTER EXP, 4, ENTER EXP, CHG
SIGN, 1, and 2 keys and the number 1 x 10 16 may be entered by depressing the ENTER EgP, 1, 6, and CHG SIGN
keys.
The ~ key is depressed to enter the value of (i.e. 3.14159265360) into the x-register.
Clear keys (CLEAR x CLEAR) The CLE M x key clears (i.e. sets to zero) the x-register. It does not a~fect any other registers.
The CLEAR key clears the x-, y-, and z- (w`orking) registers, clears the a- and b- (data storage) registers, and clears (or resets) the ~lag, which can be set by the SET FLAG key as hereina~ter explained. It does not a~ect any other registers.
When the calculator is switched on, all o~ the working, program, and data storage registers o~ the RWM are automatically cleared. Any terminated numbers subsequently stored in them will automatically be cleared and replaced by any new data entry.

; ., -;

\

Working Register Control Keys (~, ~ ROLL ~ x~y ?
The working register control keys a~e used to re-position the contents of the x-, y-, and z-registers. They do not affect any other registers.
When the t key is depressed, the contents of the y-register shift to the z-register and the contents of the x-register appear in both the x- and y-registers. The contents of the z-register are lost.
When the ~ key is depressed, the contents of the y-register shift to the x-register and the contents of the z-register appear in both the y- and z-registers. The contents of the x-register are lost.
When the ROLL t key is depressed, the contents of the x-register shift to the y-register, the contents of the y-register shift to the z-register, and the contents of the z-register shift to the x-registerO No information is lost.
The x~y key is depressed to exchange the contents of the x- and y-registers. The contents of the z-register are unaffected by this operation.
Arithmetic Keys (+, -, x ~) These four keys are used to perform working re-gister arithmetic operations in which the contents of the x- and y-registers are employed as operands. The results of these arithmetic operations are stored in the y-register and the contents of the x-register remain unchanged by the arithmetic operations performed. These four keys do not afi'ect any other registers.
The I key is depressed to add the number in the x-register to the number in the y-register, the sum appearing in the y-register.

~058766 The - key is depressed to subtract the number in the x-register from the number in the y-register, the dif-ference appearing in the y-register.
The x key is depressed to multiply the number in the y-register by the number in the x-register, the pro-duct appearing in the y-register.
The ~ key is depressed to divide the number in the y-register by the number in the x-register, the quotient appearing in the y-register.
The use of these keys and the working register control keys is illustrated by the following method o~
computing (3 x(8)x+2~-8- -6-9-) = 1 1 :

CONTENTS OF CONTENTS OF CONTENTS OF
KEYS DEPRESSED x-REGISTER y-REGISTER z-~E&ISTER

~ 3 3 ROLL ~ 0 4 12

8 8 4 12 x~y 4 8 12

9 9 8 12 ~ 9 -1 12 ~ -1 12 12 + -1 11 12 ROLL~ 12 -1 11 x~y -1 8 11 (Computing continued) -- 10 1.1 11 -The answer, appearing in the y-register, is underlined.
Unary Function Keys (~ x2 l/x int x CHG SIGN) These five keys are used to perform unary ~unctions in which the contents o~ the x-register are employed as the argument. The results of the unary functionR performed are placed in the x-register. These five keys do not affect any other registers.
The ~ key is depressed to calculate the square root of the number in the x-register. If the number is negative, the square root of its absolute value is cal-culated and the STATUS indicator light 19 turned on. The STATUS indicator light remains on until the next key is depressed.
The x2 key is depressed to calculate the square of the number in the x-register. If the number is greater than ~~ x 1049, the number 9.99999999999 x 1098 is placed in the x-register and the STATUS indicator light 19 turned on The STATUS indicator light remains on until the next key is depressed.
The l/x key is depressed to calculate the reciprocal of the number in the x-register. For example, 1/9.8 may be calculated by sequentially depressing the 9, ., 8, and l/x keys.
The int x key is depressed to truncate the fractional .. , , ~

10~8766 part of the number in the x-register. It does not affect the sign of the integer part of the number. For example, if the number -5.9 is contained in the x-register when the int x key is depressed, the number -5.0 will remain.
The CHG SIGN key has already been described above in connection with the numeric data entry keys.

Data-Storage and Register-Transfer Keys (a, b, x~(), y)(), x (), y,ll' INDIRECT) _ _ _ _ _ _ _ _ _ _ . _ These keys are variously used to perform direct data storage and recall, direct storage-register arithmetic, in-direct data storage and recall, and indirect storage-register arithmetic operations. As illustrated below, the a and b keys are depressed following any of the remaining five keys o~ this group to specify the a- and b-registers, respectively.
The a and b keys may also be used to directly recall the contents of the a- and b-registers, respectively, to the x-register without changing the contents of the a- and b-registers themselves. Either of these functions o~ the a and b keys may be performed in response to a single key-stroke thereoi'. For example, the contents o~ the b-register may be directly recalled to the x-register by simply de-pressing the b key alone. As noted above the contents of the b-register itself will remain unchanged by this recall operation.
The x)(), y~(), x~(), andy~l)keys are used to control the transier of numeric data ~rom the x- and y-registers to the a- and b-registers and 49 additional storage registers available to the user (at user addresses 000-048) in the data storage section of the R~M and ~rom these storage registers to the x- and y-registers. If the 60 optional storage re-`
gisters included in the data storage section o~ the RWM

~ 58766 (at user addresses 049-108) are made available to the user, these same four keys may also be used to control the trans-fer of numeric data from the x- and y-registers to these optional storage registers and from them to the x- and y-registers.
The specific storage register to or from which numeric data is transferred by these four keys is specified by the key or keys depressed immediately following them.
Accordingly, the a key is used to specify the a-register, the b key to specify the b-register, and the decimal digit keys 0-9 to selectively specify any of the available storage registers at user addresses 000-108 of the data storage section of the RWM. For simplicity of description, the available storage registers at user addresses 000-108 will hereinafter be referred to by their addresses (i.e. -the storage register at any available address nnn will be referred to as register nnn). If a non-existant or non-available storage register is designated, the ST~TUS in-dicator light is turned on, no data transfer or arithmetic operation is performed, and the operation o~ the calculator halts. (If such a register is designated while the cal-culator is automatically executing a stored program, the program-counter specifies the program step immediately following the improper operation.) The x)() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the x-register in the a-register, the b-register, or register nnn respectively In any case, the contents cf the x-register remain unchanged by this opera-tion. For example, ~ may be stored directly in the b register by sequentially depressing the ~, x~(), and b keys. Similarly, ~ may be stored directly in register 027, by sequentially depressing the ~, x~(~, 0, 2, and 7 keys.
In each of these examples, ~ will also remain in the x-register.
The y-)() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the y-register in the a-register, the b-register, or register nnn~respectively. In any case, the contents of the y-register remain unchanged by this opera-tion. For example, a number contained in the y-register may be stored directly in register 000, without changing the contents of the y-register, by sequentially depressing the y)(), 0, 0, and 0 keys.
The x () key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to directly re-call the contents of the a-register, the b-register, or register nnn, respectively, to the x-register. In any case, the contents of the recalled register remain unchanged by this operation. For example, the contents of register 012 may be recalled to the x-register, without changing the contents of register 012, by sequentially depressing the x (), 0, 1, and 2 keys. Recall from the a- or b-register to the x-register may be accomplished in the same manner as described above, by simply depressing the a or b key alone.
The y"~ key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to exchange the con-tents of the y-register with the contents of the a-register, the b-register, or register nnn, respectively. For example, a number in the y-register may be exchanged with a number :: ~ . - .

; lOS8766 in register 048 by depressing the y~o, O, 4, and 8 keys.
The direct storage and recall operations performed by the x~(), y)(), x~), and y~ll keys may be conveniently summarized by employing the following notation:

~Y~

lX ( )J l J
In this notation each pair of braces implies that any one of the enclosed group of key operations or storage registers may be selected. The order of the successive pairs of braces from left to right specifies the key-sequence re-quired to perform the selected key operation with the selected storage register. Thus, any of the key operations enclosed in the left-hand pair of braces may be employed with any of the storage registers enclosed in the right-hand pair of braces by first depressing the key performing the selected key operation and then depressing the key or keys designating the selected storage register. The usefull-ness of these direct storage and recall operations is il-lustrated by the following method of multiplying a series of numbers nl, n2, etc. by a constant K, where nl = 3, n2 - 11.2, etc. and K ~ 1.684:

KEYS CONTENTS OF CONTENTS OF CONTENTS OF
DEPRESSED x-REGISTER y-REGISTER a-REGISTER
. .
CLE M O O O

1, O, 6, 8, 4, 1.684 0 0 y,~" a 1.684 0 1.684 3 3 0 1,684 ~ 3 3 1,684 , ~ . . . .

-, , (Illustration continued) a 1.684 3 1.684 X 1.684 5.0520 1.684 1, l, ., 2 11.2 5~0520 1.684

11.2 11.2 1.684 a 1.684 11.2 1.684 X 1.684 18.8608 1.684 The answers, appearing in the y-register, are underlined.
The x~(), y~(), x~(), and Y,l) keys may also be em-ployed with the +, -, x, and ~ arithmetic keys to per~orm direct register arithmetic operations in which the con-tents of the x-register or the y-register are employed as one operand and the contents o~ the a-register, the b-register, or register nnn are employed as the other operand.
These direct register-arithmetic operations may be sum-marized as ~ollows by using the above-described notation:
~ $~
Thus, the x-~() key may be employed to directly per-form any o~ the arithmetic operations enclosed by the second pair o~ braces upon the contents of the x-register and the contents o~ any o~ the storage registers enclosed by the third pair of braces and store the result in the selected storage register without recalling the contents o~ the selected storage register and without changing the contents o~ the x-register. For example, the contents of the x-regi~ter may be subtra~ted ~rom the contents of the b-register by sequentially depressing the x)(), -, and b keys.

~ . . - .... .

The difference is stored in the b-register, and the contents of the x-register remain unchanged by the operation. Simi-larly, the contents of register 042 may be divided by the contents of the x-register by sequentially depressing the X~(), ~J 0~ 4, and 2 keys. The quotient is stored in re-gister 042, and the contents of the x-register itse~f re-main unchanged by the operation.
The y~() key may be similarly employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the y-register and any of the storage registers enclosed by the third pair of braces and store the result in the selected storage re-gister without recalling the contents of the selected storage register and without changing the contents of the y-register. For example, the contents of the y-register may be added to the contents of the a-register by sequentially depressing the y)(), ~, and a keys. The sum is stored in the a-register, and the contents of the y-register remain unchanged by the operation. Similarly, the contents of register 038 may be multiplied by the contents of the y-register by sequentially depressing the y-)(), x, 0, 3, and 8 keys. The product is stored in register 038, and the contents of the y-register remain unchanged by the opera-tion.
The x~() key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the x-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the x-register without changing the contents of the selected storage register. For , example, the contents of the a-register may be added to the contents of the x-register by sequentially depressing the x~(), +, and a keysO The sum is stored in the x-register, and the contents of the a-register remain un-changed by the operation. Similarly, the contents of the x-register may be multiplied by the contents of register 022 by sequentially depressing the x~(), x, 0, 2, and 2 keys. The product is stored in the x-register, and the contents of register 022 remain unchanged by the operation.
The Y o key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the y-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the y-register without changing the contents of the selected storage re-gister (i.e. the y~ may be used as though it were a y-() key in performing register-arithmetic operations).
For example, the contents of the b-register may be subtracted from the contents of the y-register by sequentially depressing the y~t~, -, and b keys. The dif-ference is stored in the y-register, and the contents of the b-register remain unchanged by the operation. Similarly, the contents of the y-register may be divided by the contents of regiters 039, by sequentially depressing the y~, ~, 0, 3, and 3 keys. The quotient is stored in the y-register, and the contents of register 039 remains unchanged by the operation.
The INDIRECT key is used with the above-described data-storage and register-transfer keys to perform indirect data-storage and recall and indirect register-arithmetic operations, in which the contents of a directly-addressed register (e.g. the a-register, the b-register or any o~
the registers nnn) are employed as the address of an indirectly-addressed storage register (e.g. any of the other storage registers nnn) to be used in these opera-tions. When indirectly addressing any of the storage re-gisters 000 through 048 or 108, care must be taken to in-sure that the directly-addressed register contains the proper address nnn of the indirectly addressed-register nnn. The indirect address used is the absolute value of the integer part of the contents of the directly addressed register. Thus, 1.732 will be treated as the address of register 001, -6.99 as the address of register 006, 0.999 as the address of register 000, and 106.75 as the address of register 106. Since the storage registers may only contain numeric data, the a- and b-registers may not be used as the indirectly-addressed registers in these opera-tions.
The indirect data storage and recall operations may be summarized as follows by again using the above-described notation without braces for the INDIRECT key:

~ ~ INDIRECT ~!

Thus, the x)() and y~() keys may be employed with the INDIÆ CT
key to indirectly store the contents of the x- and y-registers, respectively in any storage register nnn designated by the contents of any of the other data storage registers. More-over, this may be accomplished without changing the contents ,. .. ....
.......
.

-of the x- and y-registers or of the directly addressed storage register. For example, the contents of the x-register may be indirectly stored in the storage register designated by the contents of the a-register by sequentially depressing the x>(), INDIRECT, and a keys. The contents of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the y-register may be indirectly stored in the storage register designated by the contents of register 022 by sequentially depressing y~(), INDIRECT, 0, 2, and 2 keys. The contents of the y-register and register 022 remain unchanged by this operation.
The x~() key may be similarly employed with the INDIRECT key to indirectly recall to the x-register the contents of any storage register nnn designated by the contents of any of the other storage registers. This is accomplished without changing the contents of either the directly-or indirectly-addressed storage register. For example, the contents of the register nnn designated by the contents of the b-register may be indirectly recalled to the x-register by sequentially depressing the x~(), INDIRECT, and b keys. The contents of the b-register and of the indirectly-addressed register remain unchanged by this operation.
The y~l~ key may be employed with the INDIRECT key to indirectly exchange the contents of the y-register with the contents of any storage register nnn designated by the contents of any of the other storage registers. This is accomplished ~ithout changing the contents of the directly-addressed storage register. For example, the contents of the y-register may be indirectly exchanged with the contents 105~766 of the register designated by register 041 by sequentially depressing the y~(" INDIRECT, 0, 4, and 1 keys. The con-tents of register 041 remain unchanged by this operation.
The indirect register-arithmetic operations may be summarized as follows:

) ~ INDIE~CT ~ J

In connection with the indirect register arithmetic opera-tions it should be noted that the INDIRECT key may also be depressed immediately after the selected arithmetic key. Thus, the indirect register-arithmetic operations may also be summarized as follows:
DIIU:CT ! ~ ~

Thus, any of the xit), y~(), x~(), and y~l~ keys may be employed with the INDIRECT key and any of the arith-metic keys to indirectly perform register-arithmetic opera-tions employing the contents of either the x- or the y-register as one operand and the contents oi' any o~ the storage registers nnn designated by the contents o~ any o~ the other storage registers as the other operand. In the case of the x)() and y~() keys, the results of these operations are stored in the indirectly addressed storage register nnn, and the contents of the x- and y-registers and the directly-addressed registers are not changed.
Similarly, in the case of the x () and y~o keys, the results of these operations are stored in the x- and y-registers, respectively, and the contents of the directly and in-directly addressed registers are not changed.
For example, the contents of the x-register may be added to the contents o~ the register nnn designated by the contents of the a-register by sequentially depressing the x~(), INDIRECT, +, and a keysO The sum is stored in the indirectly-addressed register nnn, and the contents of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the storage register nnn designated by the contents o~ register 014 may be multiplied by the contents of the y-register by sequentially depressing the y~(), x, INDIRECT, 0, 1, and 4 keys. The product is stored in the indirectly-addressed storage register nnn, and the contents of the y-register an~ register 014 remain unchanged by the operationO Simi-larly, the contents of the register nnn designated by the contents of the b-register may be subtracted from the con-tents of the x-register by sequentially depressing the x~(), INDIRECT, -, and b keys. The dif~erence is stored in the x-register, and the contents of the b-register and the indirectly-addressed register remain unchanged by the opera-tion. As a last example, the contents o~ the y-register may be divided by the contents o~ the register nnn designated by the contents oi register 008 by sequentially depressing the y~, INDIRECT, s, 0, 0, and 8 keys. The quotient is stored in the y-register, and the contents of register 008 and the indirectly-addressed register nnn remain unchanged by this operation.

.

-Multiple-level indirect addressing may be performed to any desired level in the above described indirect data storage and recall and indirect register arithmetic opera-tions by sequentially depressing the INDIRECT key once for each desired level. Multiple-level indirect data storage and recall may be summarized as follows:

~ DI~ECT . .. INDIRECT ¦ b i 1 0 ` Y~"
Thus, for example, the contents of the x-register may be indirectly stored in the contents of register 017 designated by the contents of register 003 in turn designated by the contents of the a-register by sequentially depressing the x)(), INDIRECT, INDIRECT, and a keysO The contents of the x-register, the a-register, and register 003 remain un-changed by this operation. Similarly, the contents of re-gister 046 designated by the contents of register 031 in turn designated by the contents of register 000 in turn designated by the contents of register 025 may be exchanged with the contents of the y-register by sequentially depressing the y~, INDIRECT, INDIRECT, INDIRECT, 0, 2, and 5 keys.
The contents of registers 025, 000 and 031, remain un-changed by this operation.
Multiple level indirect register-arithmetic may be similarly summarized as follows:

¦ I~DI~ECT ... INDIRECT

.

' lOS8766 OR

J ¦ J I~DIRECT I~DIRECT ~ AA j Thus, assuming, for example, that the 60 optional storage registers 049-108 are available to the user, the contents of the y-register may be subtracted from the contents of register 108 designated by the contents of register 082, in turn designated by the contents of register 049 by sequentially depressing the y~(), INDIRECT, INDIRECT, -, O, 4, and 9 keys. The difference is stored in register 108 and the contents of the y-register, register 049, and register 082 remain unchanged by this operation. Simi-larly, the contents of the x-register may be divided by the contents of register 106 designated by the contents o$
register 056 in turn designated by the contents of the b-register by sequentially depressing the x-(), ~, INDIRECT, INDIRECT, INDIRECT, and b keys. The results are stored in the x-register, and the contents of the b-register and registers 003, 056, and 106 remain unchanged by this opera-tion.
Numeric Address Termination .
As described above, each of the available numerically-addressed storage registers 000 through 048 or 108 employed in the $oregoing data-storage and register-trans~er opera-tions is properly addressed by selectively depressing the decimal digit keys to specify its three-digit address. Upon entry o$ the third digit, the numeric address is automati-cally terminated. Any immediately $ollowing digit entries are therefore not intrepreted as part of the numeric ad-dress, but rather as the beginning of a new data entry.
Thus, for example, if the x~(), 1, 0, 3, 2, and 5 keys are sequentially depressed, the contents of the x-register are stored in register 103, and the number 25 is entered into the x-register Similarly, if the y~(), +, 0, 0, 2, 1, and + keys are sequentially depressed, the contents of the y-register are added to the contents o~ register 002, and the number 1 is entered into the x-register and there-upon added to the contents of the y-register.
A numeric address may also be terminated, without entering leading zeros of the address, by depressing any non-numeric key except the STEP PRGM key or, i~ the cal-culator is in the manual operating or first key-log printing mode, the CONTINUE key. However, most of the terminating key entries that may be used will also be executed. For example, if the x)(), 2, and ~ keys are sequentially depressed, the contents of the x-register are stored in storage register 002 and also added to the con-tents of the y-register. Similarly, if the y~(), +, 3, 8, and a keys are sequentially depressed, the contents of the y-register are added to the contents of register 038, and the contents of the a-register are recalled to the x-register When the calculator is in the manual operating or first key-log printing mode, the STOP key may be used to terminate a numeric address if a no-operation address-terminating key entry is desired For example, by simply depressing the x)(), 3, and STOP keys the contents of the x-register may be stored in register 003 without performing any other operation. Similarly, when formulating or :,~. , - .
~ ,. , ~, . . . .
.,. ~

lOS8766 entering a pro~ram by which the calculator is to be con-trolled in the automatic operating mode, a CONTINUE pro-gram step may be employed to terminate a numeric address if a no-operation address-terminating program step is desired. For example, if the program steps y~(), x, 2, 9, CONTINUE, and 3 are sequentially encountered when the calculator is in the automatic operating mode, the contents o~ register 29 are multiplied by the contents of the y-register, and the product is stored in register 29. No operation is per~ormed by the CONTINUE program step, and the next program step 3 is stored in the x-register as the beginning o~ a new data entry.
Since every numeric storage register e~cept optional registers100-108 may be uniquely speci~ied by less tha~
three digits, these abbreviated address-termination ~eatures permit signi~icant reductions i~ the number o~
key-operations and program steps required to perform many calculat~ons. Moreover, these same address termination ~eatures may be used in connection with the ~cur-digit numeric addresses o~ the program storage section o~ the RW~ to achieve still further reductions in the ~umber of key-operations and program-steps required to per~orm many calculations.
Program-Control ~eys (GO TO, IF x<y, IF x~y, IF x~y, IF FLAG, `- SET FLAG, LABEL, RE~Bu~) . _ . . . . _ . _ Ali o~ the previously-described keys except the FLOAT, FI~(), R ~ PRGM, KEY LOG, LIST, LOAD, and RECORD
keys may be employed both for controlli~g the operation o~
the calculator during the manual operating and ~irst key-log 10~87~;6 printing modes and for entering program steps into the calculator during the program entering and second key-log printing modes. When the calculator is in the manual operating mode, the user may continuously observe the output display of the contents o~ the x-, y-, and z-registers and, in accordance with his observations, make his own decisions about what to do next at any stage of the cal-culation. However, this is not possible when the calculator is executing a stored program at high speed in the auto-matic operating mode. The above eight program-control keys have therefore been provided to permit the calculator itself to test calculated quantities and make decisions based on those tests during the automatic execution of an internally-stored program. These eight keys may be used to permit unconditional branching (or transfers), condi-tional branching (or transfers), symbolic or labelled branching, storage of "yes-no" information in a flag and conditional branching based on that "yes-no" information at a later stage in the execution of a program, and un-conditional or conditional branches to pre-defined program routines with return to the main program sequence upon com-pletion.
Branching instructions in a program cause the user program counter to specify an address other than the next sequential address in the program storage section of the RWM, whereupon execution of the program continues sequén-tially from the new address. If a branch is conditional, the calculator makes a decision, based upon a specified condition, whether or not to branch. However, if the branch is unconditional, the calculator has no option, and -10~8766 must branch to the address specified in the program (e.g.
ky a GO T0 program step followed by a numeric address nnnn).
The GO T0 key is depressed followed by decimal digit keys specifying a selected four-digit address nnnn in the program storage section of the RWM to set the user program counter to the selected address nnnn. When this sequence of keycodes is encountered as a sequence of pro-gram steps, an unconditional branch is made to the address indicated and the program step stored at that address is executed. Execution of the program then automatically con~
tinues to run from that address.
For simplicity of description the terms '1keys" and "program steps" will hereinafter be used synonomously since the remaining keys of this group are used almost exclusively to enter keycodes into the calculator as program steps during the program entering mode of the calculator. All of the program steps so entered are automatically executed during the automatic operating mode of the calculatorO
The four IF keys are used for conditional branchingO
The IF x<y, IF x=y, and IF x>y keys compare the numeric values contained in the x- and y-registers to determine if the number in x is less than the number in y, equal to the number in y, or greater than the number in y respectively.
The IF FLAG key tests the condition ("yes-no") of the flag, which is controlled by the SET FLAG key hereinafter ex-plained. There can be only two possible results to each test made by each of these four keys. The condition tested is either r'met" (YES) or "not met't (NO).
When the condition tested is met (YES), the next program step following the "IF" is automatically executed.

~,:

lOS8766 However, when the condition tested is not met (N0), the calculator automatically skips (ignores) the next four program steps and continues execution at the fifth program step following the ~IF~.
If the program steps immediately following the "IFM -constitute a numeric address nnnn and the condition tested is met (YES), an automatic branch is made to that address nnnn. The program step stored at address nnnn is thereupon executed, and automatic execution of the program continued from there. If the program steps immediately following the "IF" constitute operations (e.g. +, t, etc.) then no branch occurs and the operations are executed.
When an IF program step (other than IF FLAG) is encountered, the two numbers in the x- and y-registers are automatically rounded before the test is made. In each register, the tenth digit of the number is rounded according to the value of the guard digits; the guard digits are then set equal to zero. Thus the numbers to be tested actually have the same values as would appear in a floating point display with all ten significant digits displayed. After the test has been made, the numbers in the x- and y-registers retain their rounded values. This means that the actual values of the number in the x- and y-registers may be dif-ferent after the test than before. If the resulting slight loss in accuracy is undesireable, the numbers in the x- and y-registers can be stored in the data-storage section of the RWM before the "IF" test is made and can be recalled and substituted for the rounded numbers after the "IF" test is completed.
The use of the IF x>y and IF x~y keys is illustrated _99_ , .

-by employing the following sequence of program.steps be-ginning with an I~ x>y program step and including a three-step conditional routine for taking the absolute value of the contents of the y-register:
IF x>y conditional r x~y ~ 4-step conditional routine for ¦Y¦ ~CHG SIGN ~ sequence ~y CONTINUEJ

If the contents of the x-register are greater in value than the contents of the y-register (i.e. condition met), then every program step in this sequence is executed and the ab-solute value of the contents of the y-register is calculatedO
As described above CONTINUE is a no-operation program step.
It is used in this and the following examples to fill in the fourth program step to be skipped if the test condition is not met~ If the contents of thé x-register are equal to or greater in value than the contents of the y-register (i.e.
the condition is not met), then the four program steps im-mediately following the IF x>y program step are skipped and execution continues beginning with the t program step, In this case the absolute value of the contents of the y-register is not calculated.
The use of the IF x=y key is illustrated by employing the following sequence of program steps:
IF x=y 3 ~ 4-step conditional sequence CONTINUE
CONTINUEJ

10587t~6 If the contents of the x-register equal the contents of the y-register in value (i.e. condition met), then every program step in this sequence is executed. This results in an auto-matic branch to execute the program step stored at user address 0023. However, if the contents of the x-register do not equal the contents of the y-register in value (i.e.
condition not met), the four program steps immediately fol-lowing the IF x=y program step are skipped and execution con-tinues beginning with the + program step.
The use of the IF FLAG key is illustrated by the following sequence of program steps:
IF FLAG

~ 4-step conditional sequence CONTINUE ¦
CONTINUE J
SET FLAG
If the flag controlled by the SET FLAG key has been set (i.e. condition met), then every program step in this se-2~ quence is executed. This results in an automatic branch to execute the program step stored at user address 0041. HGW-ever, if the flag controlled by the SET FLAG key has not been set (i.e. condition not met), then the four program steps immediately following the IF FLAG program step are skipped and execution continues beginning at the SET FLAG
program step by setting the flag.
The SET FLAG key establishes the condition to be tested by the IF FLAG key. The "YES" condition is established when a SET FLAG keycodè is encountered either as a program step or as a keyboard entry~ The "NO" condition is established by clearin~ the ~lag. This occurs automatically whenever the calculator is switched on or whenever a CLEAR or IF FLAG key-code is encountered either as a program step or as a keyboard entry. If the ~lag condition must be retained for use later, the program must include a SET ~LAG program step in the se-quence of program steps executed following the flag-clearing program step. The flag enables the user to select the con-ditions ~hich will determine whether a conditional branch (or operation) is to be made.
The LABEL key allows relocatable symbolic addresses to be used wlthin a program. A TAREL key immediately fol-lowed by any other programmable key (e.g. LABEL, ~) except the END key serves as a symbolic address that may be in-serted in a program immediately before any program step a user may wish to relocate independently of its absolute ~numeric) addre~s. This symbolic address is relocated by a search command comprising a GO T0 key immediately ~ollowed by the symbolic address itsel~ (e.g. GO T0, LABEL, ~ . In response to this search command, the user program counter is reset to the ~irst user available address 0000 in the program storage section o~ the R~nM and is sequentially increme~ted in a search operation until the symbolic address (e.g. LABEL, is found. -The user progra~ counter then specifies the ne~t address which is the program step desig~ated by the symbolic address.
I~ the search command came from the keyboard~ the calculator waits for the next ~ey to be depressed. ~owever, i~ the search cgmmand came ~rom the program, then execution automatically continues at the progr~m step designated by the symbolic address. The keys o~ the symbolic address itsel~

~058766 serve as no-operation codes and are ignored during execution of the program. This may be illustrated by the following sequence of program steps.
PROGRAM
ADDRESS STEP

0101 ~
0102 etc.

036~ _ 0366 etc.
The search for the symbolic address "LABEL, ." is initiated immediately after address 0101 is designated by the user pro-gram counter and starts at address 0000. When the symbolic ad-dress is found, program execution continues with the t program step at address 0365. The ~ program~steps 0101 and 0364, serving as part of the symbolic address are not executed.
A specific symbolic address cannot be used to specify more than one location at any one time. I$ it is, only the first (lowest order numeric address) specified will be valid (i.e. the point of transfer). Any number of different labels can be used at one time, limited to the number of keys available to follow the T~BEL key.
If transfer to an undefined symbolic address occurs, the calculator will search all o~ program memory, and if the symbolic address is not found, will stop with the STATUS
indicator light on. The program-counter will speciiy the next iollowing program steps.
Branching to a symbolic address offers considerable advantages over branching to an absolute address. Programs sith symbolic addresses can be stored anywhere in the pro-gram storage section of the R~M and can be easily moved and relocated because there are no absolute addresses to be changed.
Also, any time a program is to be corrected (i.e. program steps changed, added or deleted), any absolute addresses must be checked in case they themselves must now be changed as a result of the corrections. This may entail substantial bookkeeping by the user. If symbolic addresses are used instead of absolute addresses, the corrections will not af-~ect the symbolic addresses.
The main disadvantage oi using symbolic addresses is that a search takes considerably more time (depending upon the location o~ the label in memory) than does a branch to an absolute address. Usually, this will have no si~nificance because, in this case, "time" constitutes only a iew thousandths oi a second. Even ii time is a significant factor, the user may still take advantage of symbolic addresses by writing his original program ~ith symbolic addresses and once the program has been completely debugged, changing the symbolic addresses to the appropriate absolute addresses.
The EET~E~ key 1s used to transier to (i.e. call) a subroutine (subprogram) and return irom the subroutine to the point in thè caIling program where the transier was ini-t~ated. Subroutines may be nested up to a depth oi five. An attempt to ne~t to a depth oi more than fiYe is an error, stopping execution of the program and turning on the STATUS
indicator light. Both the automatic initialization occuring at turn-on and the END key (given either as a program step or a keyboard entry) automatically reset the nesting to a depth of zero so that all five depths are then availableO
A GO TO key followed by a EE~tE~ key and either an absolute numeric or symbolic labelled address may be used in the calling program to (unconditionally) call a subroutine. The address used specifies the starting address of the subroutine.
If a symbolic address is used, the first two program steps of the subroutine must also be the same symbolic address. An IF key followed by GO TO and RST~RN ke~ and either an absolute numeric or symbolic labelled starting address may also be used in the calling program to conditionally call a subroutine. Execu-tion of the steps of the subroutine starts automatically as soon as the subroutine is called. A RSTu~N key must be in-cluded as the last step to be executed in the subroutine. The RETURN causes a branch to the "return-address" in the calling program. The return address is always the address immediately following the last step used to call the subroutine. Exe-cution of the calling program then continues automatically, starting at the return address.
Any number of subroutines may be called lndividually during a programO However, it is also possible to use more than one subroutine at one time. One subroutine can call a second subroutine which, in turn, can call a third subroutine, and so on. This multiple-calling is known as "nesting". The calculator can remember (store) from one to fi~e return-addresses at a time so that the subroutines may be nested up to a depth of five. Returns are made on a "last-in, first-out"

basis, the return always being made to the last return-address stored. As soon as the return is made, that return-address is forgotten (erased from storage) so that the pre-vious address now becomes the "last" one. Thus the returning order is al~vays the opposite of the calling order.
A program written as a subroutine may also be used as a "stand-alone" program. This is accomplished by depressing the END key to erase any return-addresses currently stored in the calculator and by not using the ~ETI~ key when addressing the memory before the program is run.
Special Function Keys (FMT, ~P~F~' PAPER) The FMT (format) key is used to initiate special operations not otherwise defined and implemented by the other basic keys of the calculator. It is always used with other keys and, in effect, serves to re-define these other keys to implement the desired special operations. Several of these special operations associated with the FMT key are defined as part of the basic calculator. Others have been defined as part of associated plug-in ROM modules and are available only when the associated ROM modules are plugged into the calculator.
The command-sequences FMT, t and FMT, l are used to operate the X-Y plotter peripheral unit. They are part of the basic calculator. The X-Y plotter-input commands are PEN t, PEN l, and x and y coordinates to which the pen-carriage is to be moved. The x and y coordinates are specified by decimal numbers in the range 0000 to 9999. The corresponding actual pen range of physical movement is determined by adjustments on the plotter itself. The FMT, t command-sequence causes the pen to be raised and the contents of the x- and y-registers to be fed to the plotter as the x and y coordinates to which ~358766 the pen is to be moved. The FMT, l command~sequence lowers the pen and transmits the x-y coordinates. Note that for both commands the pen is raised or lowered first and the pen car-riage is then moved. The x-y coordinates in the x- and y-registers must be pre-scaled by the user in the range 0000 to 9999. If these limits are violated, the following events occur:
1. If the contents of the x- and/or y-registers are less than 0000 (i e~ negative), 0000 is sent to the plotter, the pen is raised, mo~ed, and loweredO
2 If the contents of the x- and/or y-registers are greater than 9999, 9999 is sent to the plotter, the pen is raised, moved, and lowered.
The result is to plot a series of dots along the boundary o~ -the plot. The raising and lowering of the pen is a visual and audible warning to the user that he is plotting out-of-bounds.
The basic calculator includes provision for recording a user-program in the program storage section of the RWM as a secure program. This provision is completely distinct from a protected recording obtained by physically notching the magnetic card. A secure program is, by definition a program which can be executed only. It cannot be listed, recorded, looked-at in the program mode, edited, or changed in any way. It is a program which can only be executed in the automatic operating mode at high speed by using the CONTI~UE key (or step-by-step using the STEP PRGM key hereinafter explained).
Any program entered by the user from the keyboard input unit into the program storage section of the RWM, or any non-secure program loaded from a magnetic card, can be - ~ . ~ ~ ,,, :

recorded as a secure program. This is accomplished in the same manner as described above in connection with the RECORD
key except that the keys FMT and RECORD are sequentially de-pressed in the named order to initiate the recording operation.
The program thereupon recorded on the magnetic card or cards is a secure program~ The original program also remains in the program storage section of the RWM as a non-secure pro-gram, and can be recorded again, either as a secure or non-secure program. It should be noted that once recording of a secure program has begun, it must be completed by continuing to insert cards until recording is terminated by an END pro-gram step. If the recording process is interrupted by de-pression of the STOP key, the recording will be terminated but the original program stored in the program storage sec-tion of the RWM then becomes a secure program and can only be executed - no further recordings can be made.
If a program stored in the program storage section of the RWM is a secure program (either by loading a program re-corded as a secure program or by the STOP default outlined above) the following conditions prevail:
1. If the PRGM key is depressed, the entire program memory is cleared.
2. If LIST or RECORD are depressed, they are ignored, so that no listing or recording of the program can be made. These actions do not destroy the program - they are just ignored.
3. Since the program is destroyed by switching to the PRGM mode, the program cannot be changed or edited in any way.
Loading of a secure program is no different than .. ~ .

~058766 loading a non-secure program - the same procedure holds Several secure programs may be chain-loaded. If a non-secure program is loaded into the calculator when a secure program is already stored therein, the program storage section of the RWM is cleared of the secure program in all areas not loaded by the non-secure program so that no trace of the secure pro-gram remains after loading the non-secure program. Thus, a-non-secure program may not be chain-loaded a~ter a secure pro-gram. However, the reverse can be done - a secure program can be chain-loaded to a non-secure program but the composite program is then secure.
The command sequence FMT, GO TO is used to implement automatic or program-controlled loading of magnetic program cards. The effect of FMT GO TO is the same as the following sequence: GO TO, O, LOAD, GO TO, O, and CONTINUEo This may be used to load a program from the keyboard, with automatic initiation of execution, or it may be used in a program to "link" programs. If the magnetic card reading and recording unit is not loaded with a magnetic card, the INSERT CARD in-dicator light will come on indicating to the user that a mag-netic card should be inserted. The LOAD routine operates in the same manner as described above in connection with the LOAD
key and is terminated by an END ~rogram step on the magnetic card.
The command sequence FMT, x~ causes the contents of the available numeric-addressed data-registers in the data storage section of the RWM to be recorded on a magnetic card.
The INSERT CARD indicator light comes on, and the recording continues, pass-after-pass, card-after-card until all registers are recorded, at which time the magnetic card reading and 1058~66 recording unit stops ~nd the INSERT CARD indicator light goes out. If the FMT, x-) command sequence was executed from a stored-program, the program will return to execution at the keycode immediately following the x) command. Recording may be terminated after any card by depressing the STOP key if the FMT x~ command sequence came from a stored program, execu-tion may then be resumed by depressing the CONTINUE keyO
The command sequence FMT x~ causes the loading of the available numeric-addressed data registers in the data storage section of the RWM from one or more magnetic data cards.
These registers are loaded card-after-card until all the registers are loaded. The INSERT CARD light remains on, and the card unit continues to run until all are loadedO The loading may be terminated by a STOP keyO If the FMT, x~ com-mand sequence is executed from a stored program, execution re-sumes after a completed data load.
The ~ E key causes the contents of the x-register to be printed in the same format as it is displayed (i. e.
FIX (), n, or FLOAT). If additional ~n~F~ commands follow im-mediately, they will cause the printer to space (print a blank line). If the = command follows immediately after a numeric entry to x (from the keyboard or from a sequence of digit-keys in a program) the numeric printout is ~ollowed by an * (asterisk) indicating that this was a data entry and not a computed result.
The PAPER key is depressed to space the strip of thermal-sensitive paper used by the output printer unit. It continues to dri~e the paper upward until it is releasedO
Program Checking and Editing Keys (~ TEF) The STEP PRGM key is not programmable and is used, from lOS~3766 the keyboard only, to single-step programs. When the cal-culator is in the manual operating mode the ~TEP PRGM key single-steps program execution. Each time STEP PRGM is de-pressed the program counter is incremented by one so that one program step is executed. When the calculator is in the program mode the STEP PRGM key enables the program steps stored in the program storage section o~ the RWM to be viewed. Each time the STEP PRGM key is depressed, the program counter is incremented by one, so that the address and program step displayed in the y-register shifts to the z-register, those in the x-register æhift to the y-register and the next higher address and program step appears in the x-register.
The BACK STEP key is not programmable and is used to decrement the user program counter by one each time it is pressed. This backs up the output display (iOe. does just the opposite of the STEP PRGM key). It should only be used in the program mode. If the STEP PRGM and BACK STEP keys are de-pressed alternately, thè same program step will be executed repeatedly. This key is extremely useful in editing and checking programs and when used with the PRGM STEP key per-mits the user to advance either forward or backward through a stored program one step at a time.
Definable and Redefinable Keys The half keys A-O comprising the group o~ definable keys 91 enable the calculator to be tailored to the special needæ of the user. Operation of these keys is de~ined by the various plug-in ROM modules 92 that may be used with the cal~
culator. Without these ROM modules the definable keys 91 serve no function and accidently depressing them, or encounter-ing them in the execution of a stored program, will result in a completely non-destructive no-operation.

- lOS8766 The plug-in ROM modules 92 include the alpha ROM
- module mentioned above, a de~inable functions ROM module, a mathematics ROM module, a statistics ROM module, and a typewriter ROM module. Both the alpha ROM m~dule and the typewriter ROM module redefine nearly all of the keys of the keyboard as well as defining the de~inable keys 91 themselves. The de~inable ~unctions ROM module, the mathe-matics ROM module, and the statistics ROM module each uniquely de~ine the de~inable keys alone and may each be used at the same time as the alpha ROM module or the typewriter ROM
module.
A di~erent overlay 192 is associated with each o~
the de~inable functions, mathematics, and statistics ROM
modules and is employed wi~h the de~inable keys 91 to identi~y the ~unctions per~ormed therby when its associated ROM module is plugged into the calculator. Each o~ these overlays 192 comprises a thin metal template that fits over the de~inable keys 91 and latches into a recess around them. The graphics on these templates visually complete the key shapes and in-dicate the ~ey function. A small tab positioned jUQt above the nameplate releases each template, which then pops up enough to grasp. Three holes 196 near the top edge o~ each template allow direct viewing of three light-emitting diode indicator lights used to indicate various operating condi-tions associated with the routines implemented by the ROM
modu}e. When the overlay and its associated RO~I module are not L~ use they may be secured together by a pair o~ tabs 198 provided o~-the ROM module~
~ description o~ the additional key operations that 3Q may be provided by the plug-in ROM modules will now be giYen.

lOS8766 Alpha ROM Module The Alpha ROM module redefines the keyboard input unit as indicated by the letters printed on the tops of the definable keys 91 and the letters and symbols printed on the front sides of most of the other keys to provide an "alpha keyboard" (see Figure 8) containing 54 character-entry keys, 5 operational keys, and 16 "non-essential" keys (these non-essential keys are either inoperative or duplicate other keys during the alpha mode). During the alpha mode, the key-log feature is deactivated (thus, any keys pressed are not logged).
The 54 character-entry keys include all of the English alphabetic characters A Z, all of the decimal numbers 0-9, and all of the following symbols ~, ~ / (printed by the . key), x, -, +, ~, ~, ,, ., =, $, ?, (, ), %, ", and #.
Depressing any of these keys during the alpha mode, will cause the alphameric character or symbol indicated thereby to be printed out in line-printer fashion. The output printer unit operates as a line printer in that each character is not im-mediately printed out, but rather an entire line (16 characters) is first stored and then printed out. The print-out occurs as the 16th character is entered.
The 5 operational keys include the FMT key, the STOP
key, a SPACE key (normally the CONTINUE key), a ~LETAuRRN key (normally the CLEAR key), and a PAPER key During the alpha mode, the following operational keys are depressed to perform various printing operations. De-pressing the FMT key twice redefines the keyboard to the alpha mode, after which character keys may be depressed After the last character is entered, depressing the FMT key causes a line print, a line $eed, and returns the keyboard to normal --" lOS8~6~
operation. (The output display is blanked during the alpha mode, although the contents of the x-, y-, and z-registers remain unchanged.) ~or example, the alphabet may be printed by sequentially depressing the RUN, STOP, FMT, FMT, A through Z, and FMT keys.
Depressing the SPACE key inserts a blank space in the printed line (similar in operation to the space bar on the typewriter).
Depressing the RETU~N key causes a line print and advances the printer to the next line (i.e. liXe a typewriter carriage-return and line ~eed operation). The alpha mode remains set a~ter this instruction. Successive CLEAR instruc-tions will cause the printer to advance, without printing, one line for each instruction.
Depressing the STOP key terminates the alpha mode wtthout a line print or line ~eed. Any characters entered but ~ot printed will be erased when STOP is pressed. This in-struction is not programmable and should not be used while programming alpha messages.
The PAPER key is a manual paper ad~ance control. This operation is not programmable.
The 16 "non-essential" keys include the ~, x~y, t, PEI~T S~B , END, BATCKp, SRT~G~, FLOAT, FIX (), RUN, PRG~, EEY
LOG, LIST, LOAD, and RECORD keys. These keys are not essential ~or alpha printing operations. The non-essential keys which are programmable duplicate the SPACE key, while most of the non-programmable ke~s are "locked-out" (i.e. not operational) ~uring alpha printing operations. Pressing BACE STEP or STEP
PRG~ will c~use I or 0, respectively, to be printed.

De~inable Functions ROM Module When the definable functions ROM module is plugged into the calculator, the user may employ the definable keys 91 to perform the redefined functions identified by the associated overlay shown in Figure 9. These functions in-clude:
a. Defining special subroutines that can be called by a single key;
b. Protecting such subroutines against accidental erasure;
c. Deleting one, or more, o~ such subroutines when desired; and d. Deleting, inserting, or searching for keycodes in any stored program.
a. De~ining a Function A user definable function can be any se~uence o~ pro-gra~ steps, beginning with the keys DEFINE F(i), where F(i) represents one o~ the keys Fl thru F9. The exeeution o~ such sequence o~ program steps must be terminated with the F-RET
key in the same manner as the SUB~RET key in the case of sub-routines.
Example .
The ~ollowing is a function which puts ~ in x, y, and z.
Pro~ram Step Eey .
0000 DEFI~E
- 000l Fl 0003 t 0004 t - ~

The above function is identified by the key Fl. To execute this function simply press the Fl key in RUN mode or insert Fl in a program at the place you want it executed.
Example:
The following is a call on Fl from another program (the program here happens to be another function F2).
Program Step Key oooo DEFINE

3 Fl Notice that we have assigned the same program step numbers to both the functions Fl and F2. Every function definition is assumed to start at program step 0000. All GO T0 commands when present in a function are coded accordinglyO This al-lows the user to define functions and delete them in a way independent of where they actually reside in the calculator memory. The key DEFINE in both of the above functions serves to mark the start of the definition of a function in the cal-culator memory. This key is treated as an error if it is pressed during RUN mode. The key DEFINE is also treated as an error if the user attempts to execute it in a program.
Exa_ple:
Program Step Key :

lOS8766 The DEFINE at program step 0003 will be treated as an error when encountered during the execution of F3. The user here forgot to terminate the exacution of F3 with F-RETo This error will cause the calculator to stop execution and turn on the STATUS light.
b. Protecting User Defined Functions The protection feature allows the user to designate areas of memory to be a part of the calculator's executive system.
i. Protecting A Single Function Assume that you have just entered the definition of the function Fl in memory (the same Fl discussed earlier). After entering the last keystroke in the definition, namely F-RET, the program counter (y display) will point to program step 0006. Location 0005 which contains F-RET will be displayed in the z-register. Switch to the RUN mode. Press PROTECT.
The light on the top of the PROTECT key (option 2 light) ... 0..... OO....... will come on. The de-finition of Fl is now protected up to and including the F-RET key. If you switch back to PROGRAM mode, whatever was in program step 0006 before will appear now to be at program step 00000 All the program steps used in defining Fl became "invisible". For all purposes these program steps are now a part of the calculator system. You can still execute Fl by pressing the corresponding key in RUN mode, or by calling on it from another stored program or function.
ii. Protecting Several User Defined Functions Assume now that both the functions Fl and F2, de-scribed earlier, are to be protected. After protecting ,-.. . : : ~ : -~,Q5S766 Fl switch to the PROGRAM mode and enter the de-finition of F2, namely:
Program ~ Key 0003 Fl After entering the definition of F2 switch to the RUN mode. Press DELETE PROTECTo The protect light indicator (option 2) will go off. Press PROTECT.
Both the definitions of Fl and F2 are protected.
iii. Effect of Protection on User Memory When protecting a certain number of keystrokes the calculator subtracts that number from the total number of program steps available in user memory.
The user can compute the number of program steps available at any time as follows. In RUN mode, press END, DELETE, PROTECT, switch to the PROGRAM
mode and read the program step number in the y display, assume this number is p. The number of program steps available to the user are given by the simple formula:
Available Program Steps = n - p The variable n in the above formula is 500, 1012 or 2036 according to the amount of user memory pur-chased.
After finding the value of p, as illustrated above, you can switch back to the RUN mode and press PROTECT
again to re-establish the protection.

~058766 c. Deleting User Defined Functions To delete a given function simply press the DELETE key followed by the name o~ the ~unction to be deleted. The DELETE key only applies to the unprotected area of user me-mory. This prevents accidental erasure o~ protected ~unc-tions. Pressing the DELETE key causes the Insert/Delete light to come on (option 1) indicating that a memory modi-fication operation is to be per~ormed. I~ a~t%r pressing the DELETE key you ~ind that you did not want to delete after all, you can press the C1EAR key to abort the delete option. Pressing the CLEAR key at this time will cause the Insert~Delete light to go of~ the ~unction to be de-leted does not e2ist the error light will come on and the delete operation w~ll be aborted. The DELETE key must be pressed while the calculator is in RUN mode. The DE~ETE
key may be ~ollowed by a function name (Fl thru F9), CnEAR, or a digit. Other keys following the DELETE key will turn on the error light and abort the delete operation. I~ en-countered during the execution o~ a stored program the DELETE
~ey will cause the calculator to stop e~ecution a~d tur~ on the error indicator.
DELETING TEE ~AST ~ Tl0N IN ~ ~ORY
The delete operation is designed to delete a portion o~
user memory which starts with the DEFI~E o~ the ~unction to be deleted and ending with the keystroke prior to the DEFINE
o~ the neæt function in memor~, or END. To illustrate, con-sider the ~ollowing memory map~
ProOE am Step ~ey 0001 Fl 1051~766 (Memory Map Continued) 0017 ...
When pressing DELETE Fl the calculator will delete the memory portion delimited by the two arrows in the memory map.
After deletion the DEFINE at program step 0004 will move to program step 0000. The following keystrokes will move ac-cordingly. Since the last function in a user memory is not likely to be ~ollowed by another DEFINE it is advisable to terminate that function with the keystroke END as shown in the memory map (program step 0016). If the last function in memory is not terminated with END then by deleting that func-tion the user will also delete that portion o~ memory which follows that function and terminates with an END. When de-leting the last function in memory, the delete operation does not delete the END key. Thus deleting F2 from the memory map -120_ ~513766 shown earlier will result in the following memory map.
Program Step Key 0001 Fl The keystroke END becomes now the terminator to the de~ini~
tion of Fl.
d. General Editing Capabilities In addition to deleting functions the user of the de-finable function block is offered the capability of deleting, inserting, and searching for individual keystrokes in memoryO
This feature is discussed next.
i. Deleting Individual Keystrokes If the D~LETE key is followed by a 4 digit address*
the calculator will delete the keystroke contained in that address and move all the following key-strokes accordingly.
Example:
Consider the memory map:
Program Step Key -000~ 0 -0006 .~ J

*See next paragraph on Automatic Address Termination for further details on address length.

.
,' ! ' : ' , ~ ~

lOS1~766 To delete the keystroke at program step 0002 press the DELETE ~ey in RUN mode, (Insert/Delete light will come on), ~ollowed by the keys 0 0 0 2. The resultlng me-mory map will be:
Program Ste~ Key CLR

0005 ...
0006 , Notice that the keystroke previously at 0003 ls now at program step 0002. ~11 the keystrokes following the deleted ke~ up to the las~ keystroke in memory ha~e been mov.ed accordingly.
~A~TOMATl~ ADDRESS TER~INATION ~ND ABORTING A DELETE-.
. In the above example we used-a 4 digit address to speci~y the keystroke to be deleted. The user can use a 3, 2, or one digtt address if such an address is terminated by a non-numeric key other than CLEAR. The ~ollowing delete co~mands are equt-valent to that gi~en in the last example: -DE~ETE 2 STOP - . ;
DELETE 02 ........ STOP
, . - DELETE 002 STOP
.
To abort a delete comma~d before it is executed press the C~ key. The Insert/Delete light (option }) will go o~f and the delete command will be cancelled. The CLEAR key can be pres-ced immediately after the DELETE key or during the entry of the address digits. Notice that the 4th digit in a~ address , ; . , - i - ~ . . -10~8766 terminates that address. This digit signals to the calculator that the delete operation is to be performed. A CLEAR key following the 4th digit of an address will have no effect on a delete operation. After performing a delete operation the calculator switches off the Insert/Delete light. If the de-lete address is bigger than 2035 the status light will come on and the delete operation will be aborted. This number re-presents the maximum available program steps in the cal-culator.
ii. Inserting Individual Keystrokes The definable function block also offers the user the capability of inserting key codes at any arbit-rary program step.
Example:
Consider the following memory map:
Program Step Key 0004 Ø
To insert a keystroke before the key at program step 0002, press INSERT in RUN MODE, (the Insert/
Delete light will come on), followed by O O 0 2, Switch to PROGRAM mode. The y display will point to program step 0002. At this location you will ~ind that a CONTINUE (Code 47) has been inserted.
The keystroke originally at 0002 has now been moved to step 0003. All the keystrokes which follow this keystroke have been moved accordingly.

-123_ ~058766 To put a new keystroke at 0002, simply press the new key while you are still in PROGRA~ mode.
The key pressed will replace the CONTINUE in-serted earlier by the calculator. Without re-placing the CONTINUE at step 0002 the new memory map is as shown below:
Program Step Key 0005 ...
The address in an INSERT command may . . . . . . .
be automatically terminated in the same manner described earlier in connection with DELETE. The insert operation can also be aborted in the same - fashion O "
Notice that the insert operation effects the con-tent of all the program steps following the one designated in that operation.
iii. Searching for a Given Eeystroke in Memory:
The ability to search for a given keystroke in me-mory is provided by the FIND key. By pressing the FIND key, in RUN mode, followed by any other key on the keyboard the user commands the calculator to search ~or that key in memory starting at the cur-rent program counter value. If the key asked for is not ~ound, the status light will come on. ~ow-ever i~ the key is found: the calculator will ~058766 automatically switch to PROGRAM mode, and the Z
register will contain the program step at which the key was foundO
Example-.

Consider protecting a function definition area inmemory. This area is terminated with the key ENDo Reset the program counter to 0000 by pressing GO
TO O or END, in RUN mode. Now press FIND END, the z-register will now contain the terminating END
in the function area. Press RUN PROTECT. The function area is now protected up to and including that terminating END.
PROGRAMMING ~INTS:
The definable functions can be nested 5 levels deep, irrespective of regular subroutine nesting~ A higher nesting value will cause the calculator to stop execution and turn on the status light.
The light on top of the F-RET key (option 3) when lit in-dicates that the user is executing a sequence of keystrokes in a function definition. If you press STOP while this light is on you may stop the calculator in the middle of a function.
To reinitialize program execution press DELETE, F-RET in RUN

mode, the F-RET light will go off and the program counter ad-justed to the value it had when the function area o~ memory was called.
Calling on a non-existant function from a stored program will cause the calculator to stop execution and turn on the status light. The program counter at this time will point to the program step which contains the name o~ the function called.

~0587~6 Mathematics ROM Module . .
~ hen the mathematics ROM module is plugged into the calculator at the left-hand receptacle 94, the user may em-ploy the de~inable keys 91 to perform the additional ~unc-tions indicated by the mathematics overlay shown in ~igure 10. All of these additional functions are programmable. Any mathematicall-y illegal functions per~ormed either from the ~eyboard input unit or a stored program will turn on the STATUS light.
The units to be used in problems involving trigono-metric ~unctions or ~ector arithmetic are selected according to the procedure listed in Table A. The units specified by the appropriate indicator light above the definable key block.
Table A. Specifying Units To Speci~y: Press: Indication:
DEGRE~S TABL~ N 1 Deg Rad Grad RADIANS TABLE N 2 Deg R;d Grat G~ADS - T~BLE N 3 Deg Rad Grad lt should be noted that the setting o~ degrees, radians, and grads (360 degrees - 400 grads) is progra~ma~le.
Trigonometric ~unctions o~ angles from 0 up to 5760 can be calculated at ~ull accuracy; however, inverse trigono-metric functions are calculated only ~or the principal ~alues of the ~unctions:
- ~-. si~ 1 x; -90 < ~ < + 90 - Cos~l x, 0 < ~ < ~ 180 4 ~ tan~l x; -90 < ~ < + 90 For instance: cos 150 ~ cos 210 ~ cos 510 ~ (etc.) ~ -.866 - But: cos .866 - 150 The sin x key is depressed to calculate the Sine o~
the contents of the x-register and insert the result in the ~-register.

1058~66 The cos x key is depressed to calculate the Cosine of the contents o~ the x-register and insert the result in the ~-register.
The tan x key is depressed to calculate the Tangent o~ the contents o~ the x-register and insert the result in the x-register.
The arc key is depressed followed by a trigonometric key to calculate the inverse trigonometric ~unction o~ the contents of the x-register and insert the result in the x-register For example, the sin 1 0.5 may be calculated by sequentially depressing the TABLE N, 1, ., 5, arc, and sin keys. Depression o~ the TABLE N and 1 keys selected the units (degrees) per Table A above.
The ~ollowing logarithmic and exponential ~unctions may all be per~ormed by employing one or two keystroke opera-tions.
The TABLE N and 4 keys are sequentially depressed in the order named to calculate the logarithm (to base 10) o~
the contents of the ~-register and display the result in the x-register.
The T~BLE N and 5 keys are se~uentially depressed in the order name~ to raise 10 to the power indicated by the contents o~ the x-register and display the result in the x-register (i.e. lOX)~ For example, the number 0.69897 may be raised to the power indicated by the contents o~ the x register by sequentially depresstng the ~, 6, 9~ 8, 9, 7~ TABLE ~J and 5 keys. ;;
The ln x key is depressed to calculate the logarithm (to base e, i.e. natural logarithm) of the contents of the `` 1058766 x-register and display the result in the x-register (i.e.
ln x). For example, the 5 ~ may be calculated by sequen-tially depressing the 2, 39 ln x, t, 5, ., ~, and ex keys.
The ex key is depressed to raise e (i.e. 2.718....) to the power indicated by the contents o~ the x-register and display the result in the x-register (i.e. eX).
The xY key is depressed to raise the contents o~
the x-register to the power indicated by the contents o~ the y-register. The result is displayed in the x-register, and the contents o~ the y-register remain unchanged.
The ~ollowing keys provide capability ~or per~orming complex and vector arithmet~c with a single keystroke opera-tion.
The T0 POLAR key is depressed to co~vert re~tangular coordinates (consisting o~ x and y components in the x- and y-registers, respectively) to polar coordinates (4 ~ tan 1 _, R ~ ~ ). When converting ~rom rectangular (cartesian) to polar coordinates, the calculated angle 4 will be within the range of -180~ 4 <18Q. The ~inal displày is:
temporary z --~
acc~mulator y (Angle 4) keyboard x (Radius R) For.example, the coordinates 4, 3 (x, y) may be converted to polar ~orm by sequentially depressing the TABLE N, 1 (these keys select the units, i.e. degrees), 3, t~ 4, and T0 POLAR
keys.
The T0 RECTANGULAR key is depressed to conYert polar coordinates,`when the radius (R) and the angle ~) are in the x- and y-registers, respectively, to rectangular coordinates (y ~ R Sin ~, x ~ R Cos ~).

, The final display is:
temporary z ---___ accumulator y (y component) keyboard x (x component) For example, the polar coordinates R = 8, ~ = 120 (or -240) may be converted to rectangular form by sequentially de-pressing the TABLE N, 1, 1, 2, 0, t, 8, and T0 RECTAN~ULAR keys.
The final display is:
temporary z accumulator y 6.928 keyboard x _4.000 The ACCUMULATE +, ACCUMULATE -, and RECALL keys are storage and recall keys associated with the a- and b-data storage registers. These keys provide complete capabilities ~or vector addition and subtraction.
The ACCUMULATE + key is depressed to simultaneously add the contents of the x- and a-registers together and the contents of the y- and b-registers together. The sums are entered in the a- and b-registers, respectively, while the x- and y-registers remain unchanged.
The ACCUMULATE - key is depressed to simultaneously subtract the contents o~ the x-register from the contents of the a-register and the contents of the y-register from the contents of the b-register. The remainders are entered into the a- and b-registers, respectively, while the contents of the x- and y-registers remain unchanged.
The TABLE N key permits access to 10 more R0~ func-tions than there are de~inable keys. A list o~ these func-tions is given in Table B below. The TABLE N key may be fol-lowed by any key. I$ this key is di~erent from a numeric ;- .

1 [3S8766 or FMT, no operation is performed.
Table B
TABLE N FUNCTION
1 SET DEGREES~ -I SETS ARG~ ~ T UNITS FOR
- 2 SET RADIANS ) ~ TRIGONOMETRIC FUNCTIONS
3 S~T GRADS J
4 Logl0x 6 DEGR, MIN, SEC _ DECI~AL DEGREES
7 DECI~AL DEGREES _ DEGR, ~IN, SEC
8 g.

FMT A~TOMATIC P~O-ll~R SCALING
The ~irst i~e functions o~ the TABLE N key have al-ready been explained above. However, this key may also be used to per~orm any o~ the next ~ive functions (na~ely, angle co~ersion, calculation ~', rounding a number to a speci~ied power of ten, and piotter scaling) not previously described above.
The TABLE N and 6 keys are sequentially depressed in the order named to convert an angle e~pressed in degrees, ~inutes and secouds to decimal degrees. The a~gle must be entered into the calculator as ~ollows:
DISPLAY
temporar~ z - (~egrees) accumulator y - (Minutes) keyboard ~ - (Seconds) The result in dècimal degrees, appears in the x-register, while tke y- and z-registers are cleared. This is illustrated as ~ollows:
.

.

lOS1~766 temporary z - 0 accumulator y - 0 keyboard x - DECIMAL DEGREES
The TABLE N and 7 keys are sequentially depressed in the order named to convert an angle expressed in decimal degrees to degrees, minutes and seconds. The angle to be con-verted must be entered into the x-register, and the resultant angle appears as in the previous display. However, the con-tents of the y- and z-registers need not be zero for the in-struction TABLE N, 7.
The TABLE N and 8 keys are sequentially depressed in the order named to replace the contents of the x-register with X' (where x 0 < ¦xj < 69).
The TABLE N and 9 keys are sequentially depressed in the order named to round the contents of the y-register to the power of ten indicated by the integer value of the con-tents of the x-register. The rounded number appears in the x-register, while the y-register remains unchanged. For example, the number 5610.0 may be rounded to 102 (or nearest 100), by sequentially depressing the 5, 6, 1, 0, and t fol-lowed by the 2, TABLE N, and 9 keys.
DISPLAY
accumulator y 5610.000 keyboard x 56000000 (y rounded) Similarly, the contents of the y-register may be rounded to another power (10 ) by sequentially depressing the 4, TABLE
N, and 9 keys.
DISPLAY
accumulator y5610.000 keyboard x 10000.000 (y rounded) 1058~66 A fractional number may be rounded by inserting a negative number into the x-register. For example, the number 0.005 may be rounded to the 10 or nearest 1/100 by sequ~ntially depressing the ., 0, 0, 5, t, CHG SIGN, 2, TABLE N, and 9 keys.
DISPLAY
accumulator y 0.005 keyboard x 0.010 (y rounded) A problem usually encountered when writing a calculator/
plotter program is that of scaling the available problem variables to coordinates which the plotter can use. The plotter scaling feature to be described, simplifies this typical plotting problem. The TABLE N, FMT, and t or 1 keys are sequentially de-pressed in the order named to replace the plotter problem variables, which are entered in corresponding x- and y-registers, with scaled coordinates. The user variable maxima and minima for this scaling operation are stored in user data storage registers 001-0040 The foregoing sequence of keys controls the plotter (using the scaled variables) in the same manner as FMT, t, or ~ described above.
The DEFINABLE f ( ) key is used to label and "call" an often used (or favorite) function which is programmed as a subroutine in the calculator. The definable function may be executed at any time from the keyboard by depressing the DEFINABLE key, or it may be "called" in a program by inserting the DEFINABLE (key) instruction. The definable function is programmed similar to a "LABEL" subroutine, while the function is executed as a normal subroutine; except it may be "called"
with only one keystroke or program step.
When the DEFINABLE f ( ) key is depressed the program counter searches for a subroutine labeled DEFINE f ( ), 10~8766 executes, and returns This key can be used both in key-board and program control. A user written subroutine to be called by the DEFINABLE f ( ) key can be stored anywhere in the program memory, its first program steps must be LABEL, DEFINABLE f ( ); its last step must be SUB/RETURN. There are no restrictions on the operations this subroutine may performO It is illustrated by the following example:
LABEL
DEFINABLE f ( ) t ex x~y eX

+

SUB

Whenever the key DEFINABLE f ( ) is called either in RUN or PROGRAM mode, the hyperbolic cosine of the number in the x-register is computed and placed in the y-register by this subroutine.
The TABLE N and CLEAR x keys are depressed to clear all numerical storage registers without affecting the a- and b-registers or the x-, y- and z-registers.
A programmed subroutine may be repeated m number of times by inserting the following keys at the end of the sub-routine: TABLE N, SUB RETURN, and n, where n may be any key from O to 9 indicating a data storage register that contains m, and m is equal to the absolute integer value of the contents . .

lOS~3766 of the n-registerO After the subroutine has been repeated n times, the program exits the subroutine and resumes normal program operation at the program step following the sub-routine "calling instructions". The iterative subroutine feature may be added to a "~.AREL" subroutine, but when the LABEL subroutine is "called" (during a program) the call instructions must contain 6 program steps. The ~ollowing partial program shows how to call the LABEL ~ iterative sub-routine, Iterative "LABEL" Subroutine STEP KEY ~EE COMMENT
.....
0400 - - - _ _ 0401 CONTINUE 47' Subroutine ¦ CALLS
0403 GO TO 44 ¦
SUB I Instructions 0405 LABEL 311 (6 keys) 0406 ~ ~6J
Return from 0407 ~ 35 Subroutine lOS8766 Statistics ROM Module The primary function of the statistics ROM module is to carry out the summations of variables, cross-products, and squares needed as funda-mental quantities in a variety of statistical analyses. These summations are generated in the general data storage user registers, and the user must be careful to avoid any operations which might destroy or alter the contents of these registers. The number of registers used is dependent on the number of variables treated - as defined by the user.
The registers used are:
n ~0 2 x ~1 2 x2-- ~2 ~ variable; x 2 y ~3 2xy :~ 4 2 y2 ~ 5 ~,r 2 - variable; x, y .
2 z-~6 2XZ ~7 2yz ~ 8 2 z2-~9 ~ 3 _ variable; x, y, z -2 a~10 2xa~11 2ya.~12 2za~13 2 a2~14 ~ 4 - variable; x, y, z, a 2 b~15 2xb~16 2yb~17 2zb~18 2ab~19 2 b2~20 ~5 - variables; x, y, z, a, b These are graphically summarized in an easy-to-recall form in this table:

_ 1 1 3 ¦ 6 l 101 15 x ~ 4 7 11 16 r G~L 8 ~ 18 In addition to ~he user-registers O - ~- 20 ut~ized as sh~wn above, registers 21 - ~27 axe usedfor co~ection of max~num /m~N~num values, for the "seed" ofthe pseudo-random ~umber genera$or. This is shown below:
~ ---s-2 z ~
Zmax ~ 26 $UN- ~27 ~ y regi~ers notused in a spec~ic sequence are ava~able. For ~Yample, ~ 2 - ~ariable operations are set up, oDly reg~ers 0~ ~5 are ~n use, and 8 ~ ~20 arefreefor other purposes.
When the statistics ROM module is plugged into the calculator, the user may employ the definable keys 91 to perfonm the additional functions indicated by the statistics overlay shown in Figure 11. All of these additional functions are progra=mzble and will hereinafter be described key-by-key.

, ~OS87~6 The VARIABLES K key is used to define the number of variables to be treated, 1 to 5. It must be followed immed-iately by a digit key, 1 to 5. If any other key is depressed after this key. the STATUS light will be turned on, and the calculator will halt in the display mode. The VARIABLE key and the erroneous key following it are ignored - there is no other action.
If a correct digit key follows, one or more of the indicator lights will come on, to signal the number of variables selected. The pattern is:
1- variable 1 - light 2 - variable 2 - light 3 - variable 3 - light 4 - variable 1 and 3 - lights 5 - variable 2 and 3 - lights The definition of the number of variables affects subsequent use of the ~ key, MAX/MlN key, and the ~ITlALIZE and CORRECT keys used in conjunction with it. The number of variables remains unchanged until the VARIABLES key is used to change it, which may be done at any time.

This key is used to accumulate the data summations of variables, cross-products, and squares as outlined previously. The number of summations is determined by the VARIABLES key described above.
That is, the contents of the registers utilizedare:
1- variable x 2 - variable x, y 3 - variable x, y, z 4 - variable x, y, z, a 5 - variable x, y, z, a, b If the summation key ( ;~ ) is depressed without a previous definition of the number of variables (VARIABLES key followed by digit 1~ 5), the number of variables is set at 3. I~ will remain at this setting unless changed by use of VA~ABLES
The E key generates the summations, and leaves the contents of x, y, z, a, and b unchanged.
The ~ITIALIZE and COMECT ke~s work in conjunction with the summation key. They must precede the ~ key.
When the sequence I~ITIALIZE - ~ is used, all registers (defined by the number of variables set) involved in the summations are cleared to zero. This sequence should always be used before the start of a series of summations on a set of data - otherwise any previous contents of the registers are included in the summations.
If, after depressing the ~ key, it is discovered that the contents of x, y, z, a, or b were erroneous, the user may remove the erroneous data from the summation by depressing CORRECT - S keys in that sequence. This will remove all variables, cross-products, and squares of that data from the summation. The user may then correct the data and reenter it by depressing the ~ key. Since x, y, z, a, and b are unchanged by the use of ~ (or CORRECT - ~ ) this is most conveniently done when the erroneous data is still intact - i. e., immediately after ~ . However, if the erroneous data is not discovered until later the user must reenter the erroneou~,data in x through b tonly x and y if ~ - variable, etc. ), use CO~RECT - 2- , and then correct the erroneous data and enter it with the ~ key.

The user must be careful not to do any operations during a summation-sequence on data which will alter the con-tents of any user-registers involved in the summation.
However, the contents of any of the summation-registers may be recalled and used at any time, so long as they are not altered.
Once a data-sequence has been entered by use of the ~ key, the summations are available for any desired statistical analysis. For user convenience, four commonly used statistical processes are implemented, to be performed by a single keystroke. The function of these four keys will follow.

The MEAN key computes tfrom the collected summatians) the arithmetic mean of up to three variables; x, y, and z. If 4 or 5 variables are set, the MEAN key operates on only 3, and does not form the other two means (on a and b).
For various variable settings, the following computations are made, and appear in the x, y, z registers:
1 - variable z 0.0 x x = ~x = (1) n (O) where (1) means "contents of register - 1".
2 - variable z 0.0 y y=~ y=(3) n (O) x x . l~S~3766 3 - variable z z = E z = (6) n (O) Y Y
x x These computations are carriedout and the results appear in x, y, z as shown, without changing the contents of any of the summation registers.

The ~ARIANCE key computes (from the collected summations) the variance of up to three variables, x, y, and z. If 4 or 5 variables are set, the VARIANCE key cperates on only 3, and does not form the variance of aorb.
The following computations are performed:
x2 _ ( ~nx)2 (2) -~
x n- 1 (0)-1 y2_ ( ~ y)2 (5)_ (3)2 y = n = (O) n- 1 (0)-1 z2 _ ( ~ z)2 (9)_ (6)2 z =i n = (O) n- 1 (0)-1 The results appear in the x, y, 2 registers in the pattern.
1 - variable 2 - variable 3 -~ariable Z- ' 0-0 . 0-0 ~z Y- 0.0 ~,2 ~,2 x - ~,2 ~ 2 ~2 The contents of all summation-registers used in these computations remain unchanged.

. ~
. .". :, , . ~ .;
. ,.~ ~ ., .,, , ~ . - -lOS8766 The REGRESSION key performs linear regression (least-squares curve fitting) using the accumulated summations. The computations and results are controlled by the variable-sett~ng, as outlined below:
Variable - 1: The regression of a single variable on itself is not performed. E REGRESSION is depressed with VARIABLES - 1 set, the ST~TUS light is turned on, and the calculator halts in the display mode.
There will be no other action - the contents of x, y, z, and a~l summation -registers will be unchanged.
Variable - 2: The regression of the dependent variable on one independent variable is performed for the equation:
y = aO + alX
The results are placed in x, y, z in the pattern:
z --0.0 y --- aO
x- al The contents of all summation-registers used in the computation remain unchanged.
Variable - 3: The regression of the dependent variable on two indè~endent is performed for the equation:
z = aO + alx + a2y The results are placed in x, y, z in the pattern:
Z aO
y --- a2 X al The contents of all summation-regiæters used in the computation remain unchanged.
Variable 4 - and Variable - 5: This situation is treated as Variable - 3. Four - and 5 - variable regression may be performed ~y user-~rogramming. All summations required are generated by the .
key when variables are set at 4 or 5.
r2 The r2 key generates the correlation coefficient (a measure of -goodness-of-fit) for the linear regressions performed by the REGRESSION
key. The computations performed are controlled by the variable setting.
Variable - 1: No computations are performed - the key is ignored.
Variable - 2: The correlation coefficient of the linear regression for:
y = aO + alX
is computed.
The computations performed are best described by introduction of a subsidiary quantity:
XiXj = ~xiXj - ( ~ Xi)( ~ Xj) -h The correl~tion-coefficient for variable - 2 is then defined to be:
r2 = (~ xy)2 ~ xx.~yy This result is placed in register x, and y and z are cleared.
Variable - 3: The correlation-co~fficient of the linear regression for:
Z=aO+alX+a2y i8 computed. This is:
r2=al~(xz+a2~(yz ~zz ..
The result is placed in register x, and y and z are cleared.

The MAX/MI~ key is used to collect the maximum and minimum values of the variables x, y, and z. Since these values are stored in registers 21 through 26, they do not affect the summation registers ( ~ key). Thus, MAX/M~ ~nformation may be collected on the same data on which summation information is being collected.
The MAX/M~ storage registers 21 through 26 are initialized by the key-sequ nce lNITIALIZE - MAX/MIN. This results in loading the registers ~vith:

~OS87~6 (~1), (~3)~ (~5) (x~ Y~ Z)min = 1099 (22~ ~24), (26) (x~ Y~ Z)max = -10 All six registers are initialized without regard to the variable-numbersetting.
When ~L9X/MIN is depressed, the contents of x (l-variable), x and y (2~variable) or x, y, and z (3, 4, or 5-variable) are compared to the stored contents of the max/min registers. If the new value is less than the contents of the associated "min" register, the new value is substituted -if not, the register is left unchanged. The maximums are handled correspondingly. Thus, at any time the max/min registers contain the max/min of the input data since the last initialization. This data is not displayed - the user must recall it, as needed, from the appropriate register.
The CORRECT key c7oes not work in association with the ~L9X/M~
key, since any previous values changed are lost irretrievably by the MAX/MIN operation.
t The t key collects summations necessary to compute a t-statistic on data in x and y, and computes and displays the statistic. The overall action is quite different from the ~ key, which collects summations only, and leaves the original data unchanged. In contrast, the t key collects needed summations, computes and presents the t-statistic, and destroys the data just entered.
Further, the t-summations are stored in registers 0, 1, and 2 which are the same registers used by the ~ key. Therefore, use of the ~ and t key cannot be intermixed.
-The summations accumulated are:
n ~0 ~ (x - y)a Y) ~ D~ D
These are accumulated with each depression of the t key. The three registers may be cleared for starting a new data-sequence by the key-sequence INITIALIZE - t.
If an error i~ made in data entry and the erroneous data is included in the summations by depression of the t key, it is convenient to have a means for removing the erroneous data. Ho~vever, the data has been destroyed in order to present the t-statistic which is computed after each key depression. When the user discovers the data error, he may reenter the erroneous data in x and y. Then, depression of CORRECT - t will remove the data from the summation. He may then reenter the correct data ~nd include it by depressing the t key.

--14~--lOS87~6 The computations performed from the summations are:
D _ (x - y) ~ n ~ n ~~ D
~D 1¦ (x _ y)2 ( ~ (x _ y))G
y n(n- 1) D is placed in the z - register, n in y, and t in x.

-The x2 key accumulates the summations and then computes andpresents the chi-squared statistic at each depression of the key. It's general operation is the same as the t key in that:
1. 2 Summations are accumulated in O and 1 so that use of X and ~ cannot be mixed.
2. The presentation of results after each key depression destroys the data entry in x and y. Correction for erroneous data can be accomplished ~y reentering the bad data and then depressing CORRECT - X .
3. The regi~ters used (0 and 1) are cleared by depressing INlTIALIZE - X .
The summations accum~llated are:
n -~ ~0 ln the normal context for use of chi-square the "observed" value is in x, the "e~pected" value in y.
The RANDOM key causes the computation of a sequence of pseudo-random numbers, uniformly distributed in the interval O_RN>l. The method used is congruential products. It is neces-sary for the user to provide a "seed" for the sequence before using the RANDOM key. A given seed will produce the same se-quence of pseudo-random numbers each time it is used.
The seed should be stored by the user into register 27.
After each depression of RANDOM, the newly-generated pseudo-random will be stored in register 27 as a new seed, and the number will also be presented in the x - register. They y and z regis ters rema in unchanged .

10~8766 The initial seed provided by the user should be selected with certain rules in mind in order to obtain acceptable pseudo-random number properties. They are:
1. Enter a decimal fraction consisting of 12 digits (i.e., enter a complete number including guard-digits, even though they cannot be seen).
2. The number should be odd.
3. The number should not be evenly divisible by 5.
The LOGlox, LOGex, and eX keys provide the specified mathematical function on the argument in x, and the result is left in the x-register. No other registers are changed.

. . . . . .
: , . . . .

, - ,~.. " ~. ~

~OS8766 Typewriter ROM Module When the typewriter ROM module is plugged into the calculator, the keyboard input unit is redefined as shown in Figure 12 so that the entire keyboard of a properly interfaced typewriter such as the Facit ~odel 3841 (hereinafter referred to as the Model 61) may be completely controlled by the calculator. The Model 61 is capable of performing three basic operations:
l. Type data contained in the calculator's X-register.
2. Type alphameric messages and control typewriter functions.
3. List programs contained in the calculator memory.
These operations are accomplished by calculator instructions given either'from the keyboard or as program steps in a proper sequence. In this section, these instruction sequences will be described. Numerous examples are provided so that the user will be able to manually key the instruction sequences and observe the results. In normal operation, the instruction sequences would be placed in a program.
Table C provides, in brief form, the instruction sequences used to operate the Model 61. The table is not provided to teach typewriter operation; rather, it is provided for quic~ reference once the instruction sequences are under-stood.
All of the Model 61 irstruction sequences presented in this section can be reduced into component parts consisting of one or more calculator instructions. For example, all of the ~lodel 61 instruction sequences contain the two calculator instructions FMT and 2.
The instructions FMT and 2 ser~ice the special purpose of redefining the following calculator instructions so that they will be understo,od only by the typewriter. The two instructions, when thought of as a component part of an instruction sequence, can be considered as "the type-writer address". Although these two instructions will be shown as part of' each o~ the following instruction sequences, their meaning will not be explained again.
, 10587~6 TABLE C
COMMAND SET
Instruction Sequence:
Typing a Number Types the number in the x-register in a notation and location specified by 1. FMT 2 PRINT the last w.d. instruction.
2. FMT 2 w.d. w speci~ies field width (location).

3. FMT 2 w.d The number will be right justified in the PRINT
field At turn-on, the calculator assumes a w of 20 d specifies the number of digits to the right of the decimal point or specifies ~loating point.
Alphanumeric Typing FMT 2 FMT Message FMT
Allows the user to type labels and headings Also allows control of all keyboard functions except margin setting. Messages may include print instructions. Calculator keyboard has two modes, shifted and unshifted (see keyboard diagram on the back page).
Listing A Program FMT 2 List Lists the contents of the calculator's memory be-ginning with the present locat~on of the program counter and continuing until an end statement is encountered in the memory or stop on the calculator keyboard is pressed. The listing includes address location, key code, and key mnemonic.
All commands are available on program or manual request.

., : . , , : -The instruction sequence FMT, 2, w.d, PRINT allows the user to type the data contained in the calculator's X-register. In this sequence, the notation (fixed or floating point) of the typed data can be specified. In addition, the location where the data will be typed on the typewriter platen may also be specified. This instruction sequence consists of the following component parts:
FMT 2 - Typewriter address.
w.d. - Specifies the location and notation of the typed data.
PRINT - Causes the data point to be typed.
The instruction sequence is initiated with the typewriter address and is terminated by the PRINT instruction. The component parts of the instruction sequence have the following meaning for the typewriter.
w.d. - This component of the instruction sequence allows the location and notation of the typed data to be specified.
The w part of the component specifies the location; the d part specifies the notation. The decimal point in the com-ponent delimits the two parts. Although a w cannot be given without also giving a d, they are best explained separately.
w specifies the field width (w) in which the data is to be typed. The left side of the field is defined by the location of the typewriter carriage when the data is typed. The right side of the field is defined by the value of w. For example, if the typewriter carriage were sitting ten spaces from the left margin setting and w was specified as twenty, then after the data has been typed the carriage will be located thirty spaces from the left margin setting.
Any data typed in a field, will automatically be typed in the right most spaces (right justified) of the field. The following drawing illustrates the number 123.45 right justified in a field of ten.

w = 10 The field must be large enough to contain the typed data, including the decimal point and any signs that may be present . .
- . . ~ . - "

in the data point. If, for example, the data point were the digit one, a w of one would be large enough to contain the data point; however, if the data point were a negative one, a field width of two would be required.
If the field is not large enough to contain the data point, the data will not be typed; instead, the entire field would be filled with asterisks to notify you that the data point could not be fitted into the specified field width.
W may be specified as any number between one and sixty-three (inclusive). Since the data point is always right justified in the ield, you will use w to place the data point at the desired location on the typewriter platen.
Do not, however, set w so large that the data, when typed, exceeds the right margin setting. If the right margin is exceeded, the program will be stopped at the memory location following the PRINT instruction (explained later) that exceeded the right margin setting and the STATUS lamp will be lit.
When a w instruction is given, the value is automatically stored in the calculator. A w instruction, once given, need not be given again in a program and may be used any number of times when succeeding FMT, 2, PRINT texplained later) instruction sequences.
The value selected for w is lost when the calculator is switched OFF. When the calculator is switched ON
a w of twenty is automatically stored.
The d part of the w.d component allows the user to control the mode of the calculator display from a program and, therefore, the notation (fixed or floating point) of the typed data.
In this instruction sequence, when the data in the calculator's X-register is typed, it will be typed as it is displayed in the X-register. In order to provide the capability of specifying the notation (fixed or floating point) of the typed data, this instruction sequence is capable of con-trolling the format of the calculator display. This is provided by the d part of the w.d component.

; , . . . .
, . . ~ .

The following table shows the relationship between d and the notation of the typed data.
d Typed Notation 0 decimal part and decimal point are suppressed 1 one digit to the right of the decimal point is typed.
2 two digits to the right of the decimal point are typed.

9 nine digits to the right of the decimal point are typed.
decimal point) the data will be typed in floating point notation.
A data point in the calculator's x-register will always contain a decimal point; however, if the data point is displayed with no digits to the right of the decimal point (e.g., 10.), the data, when typed, will be typed without the decimal point.
The d part of the w.d component is most easily thought of as a programmable FIX ( ) - FLOAT instruction. It has the same effect as those keys on the calculator display. Also, all of the rules of operation concerning overflow and under-flow applicable to the FIX ( ) and FLOAT keys apply equally to d.
In the case of overflow, if the calculator display contains nine digits to the right of the decimal point and a data point containing two digits to the left of the decimal point is entered in the x-register, the register will overflow and display the data point in floating point notation.
Exactly the same situation can occur with d. If you specify a d of nine and the data point in the x-register overflows, then the data point will be typed in floating point notation.
There is a potential problem in the interaction between w and d that the operator should be aware of. For example, assume that w has been set for two and d has been specified as zero. If the data point in the x-register over-flows and an attempt is made to type the data point, the field width of two will not be large enough to contain the data point in floating notation and two asterisks will be typed.

.~, - , ~ .. ..
.,: - - .. .. ~

Whereas an overflow condition which exceeds the field width will cause asterisks to be typed, an underflow condition will not. In an underflow condition, the data point in the x-register has become so small that the d specification does not allow the data point to be dis-played with enough accuracy. Like the overflow condition, the data point is, in essence, not typed. For example, assume the yalue of the data point in the x-register were 1.23 x 10 11 and d were specified as zero. When the data point is typed it will be typed as zero.
The operator should be aware of the range in which the typed data will lie and set the w.d specification so that neither underflow or overflow occur. If the range is likely to be very great, the field width and d should be set so that the data point is typed in floating point notation (16 . . ).
Because d is essentially stored by changing the format of the calculator display, the value for d remains unchanged until the display format is changed. This can be done by giving another d instruction or by manually pressing the FLOAT or FIX ( ) keys. If, for example, you specify a d of two, stop the program and press FLOAT, then, when the data is typed it will be typed in floating point notation.
The PRINT component of this instruction sequence causes the typewriter to type the data contained in the calculator's x-register. The data will be typed in the location and notation specified by the last w.d component given.
When a FMT, 2, w.d, PRINT instruction sequence has been executed, the instruction sequence will automatically be terminated and the typewriter address reset. This means that if you wished to type the same data twice, the entire instruction sequence (less w.d, explained later) must be given again.
In order to provide maximum programming flexibility, certain component parts of the FMT, 2, w.d, PRINT instruction sequence may, optionally, be omitted from the instruction sequence. The following variations of the sequence are allowable:
FMT, 2, w.d, PRINT - Type the data in the x-register in a specified location and notation.
FMT, 2, w.d - Establish a field width (w) and notation (d) which will be used later in the program by one or more FMT, 2, PRINT
instruction sequences.
FNT, 2, PRINT - Type the data in the x-register in a location and notation stored earlier in the program.

.

105~37~

The FMT, 2, w.d instruction sequence allows you to save program steps by specifying w and d only once in a program and reusing them any number of times with succeeding FMT, 2, PRINT instruction sequences.
The PRINT instruction in these sequences will automatic-ally terminate the instruction sequence and reset the typewriter address. In the case of the FMT, 2, w.d instruction sequence, the instruction sequence is not terminated; however, the next calculator instruction, in addition to performing its normal function will terminate the sequence.
The use of the FMT, 2, w.d, PRINT instruction sequence is illustrated by the following example:
A piece of paper 8-1/2" or wider is placed in the typewriter and the margin stops, paper guide and carriage set as shown below:
Left Margin Right Margin Stop ~ ~ Stop O O O O . . . O O
Paper Guide 1 2 3 4 Paper Bail's 0 Q 0 0 0 . . . Graduated Typing Scale p O O O O . . .
f--l Card Holder The number one thousand is keyed into the calculator's x-register, and floating point display is selected.
DISPLAY: 1.000000000 03 X
PRESS: FMT, 2 1 3 2 DISPLAY: 1000.00 ---~X
The w (13) was stored and the d t2) changed the display.
The instruction sequence is not terminated, however, and a PRINT instruction may be added:
PRESS: PRINT
TYPE-OUT:
w = 13, d = 2 ~ 1- ~ 2 3 4 0 0 3 0 0 0 . . .

.: . . . . . .. .

1~58766 The red pointer mark on the CARD HOLDER points to thirteen on the PAPER BAIL'S graduated typing scale, not fourteen as one might expect. That is because the scale starts at zero, not one.
The PRINT instruction has terminated the instruction sequence. To type the data again will require another instruction sequence:
PRESS: FMT, 2, PRINT
TYPE-OUT:
w = 13, d = 2 1000.00 1000.00 0 0 0 6 0 0 . . .
The FMT, 2, PRINT instruction sequence has used the w and d stored in the preceding FMT, 2, w. d instruction sequence.
The type-out is right-justified on the twenty-sixth space as the left side of the field is defined by the location of the carriage when the data is typed.
It should be noted that a FMT, 2, w.d PRINT
instruction sequence does not contain the capability of a carriage return/line feed instruction. This capability does exist, however, as explained below.
A FMT, 2, w. d instruction sequence is terminated by the next calculator instruction given. In addition to terminating the FMT, 2, w. d instruction sequence, the instruction will be performed in its normal manner.
PRESS: FMT, 2 DISPLAY: 1.000000000 03 --~ X, Y
This instruction sequence has specified floating point notation; however, this display can be manually over-ridden with the FIX ( ) - FLOAT keys:
PRESS: FIX ( ) 2 DISPLAY: 1000.00 _ X

, : '':' -~os87f~6 PRESS: FMT/ 2, and PRINT
TYPE-OUT: w = 13, d = 2 1000.00 1000.00 1000.001 O O O O ,~0 . . .
f~
Data in the calculator's x-register can be typed without a decimal point. This is done by specifying a d of zero:
PRESS: FMT, 2, 4, ., 0, and PRINT
TYPE-OUT: w = 4, d = 0 :~' 1000.00 1000.00 1000.00 0 0 0 0 ~ 3 The data point just typed was typed in a field width of four, just large enough to contain the data. Spaces between this data type-out and the one previouslY typed could have been provided by specifying a larger field width, w.
Asterisks will be typed across a field that is not large enough to contain the data.
PRESS: FMT, 2, 3, ., 0, and PRINT
TYPE-OUT: w = 3, d = 0 ,-- 1000.00 1000.00 1000.001000***

0 0 0 0 0 6 0 . -1~1 .

-: , The FMT, 2, FMT, MESSAGE, FMT instruction sequence allows labels and headings to be typed for data. With this instruction sequence, the user can control both characters on each typewriter key and control all typewriter functions directly from the calculator, either by stored program step or manually, from the calculator keyboard.
The instruction sequence consists of the following component parts:
FMT 2 - Typewriter address FMT - Established the TYPING
MESSAGES instruction sequence.
MESSAGE - Your label or heading FMT - Terminates the instruction sequence.
Other calculator instructions which terminate this instruc-tion sequence are:
LOAD STOP * PRGEP FLOAT
RUN KEYLOG RECORD END *

STEP FIX ( ) PRGM LIST
* Programmable instructions.
In the MESSAGE component of this instruction sequence, one programmable calculator instruction will control one typewriter key. Which character on the typewriter key will be typed or which typewriter function will be performed, will depend on the mode of the calculator keyboard when the instruction is given. In the MESSAGE component of this sequence, the calculator can be in one of two modes, unshifted or shifted.
When the instructions FMT, 2, FMT are given, the calculator keyboard will automatically be in the unshifted mode. In this mode of operation, the calculator instructions and the typewriter character typed or function performed have the correspondence shown by the characters and symbols included within the keys of Figure 12.

-1~4-~058766 rhe-~ns~ ed ~a?r~1~t~r ~yboatd ~dn control ~h~ typewriter's numbers and capital alphabet. In addition, the functions TAB
CLEAR, TABg CR/LF (Carriage return/Line feed), SPACE, BLACK
RIBBON may also be performed. The FMT instruction and the blank keys shown in the diagram will terminate the instruction sequence. Three instructions (PRINT, TAB and SHIFT) avail-able on the unshifted calculator keyboard require special mention.
A PRINT instruction placed in a MESSAGE will cause the data in the calculator's x-register to be typed. The data will be typed in the location and notation specified by the last w.d given. A w.d may not be placed in a MESSAGE; however, they are stored when they are given and automatically recalled and used with a PRINT instruction p1aced in a MESSAGE.
A TYPING MESSAGES instruction sequence will not affect the contents of the calculator's display registers. Therefore, data can be placed in the x-register and typed with a PRINT
instruction placed in this instruction sequence.
Giving a TAB instruction will cause the typewriter carriage to move either to the next tab set or to the right margin setting. If the carriage is less than two spaces from a tab setting and a TAB instruction is given, then that tab setting will be ignored by the typewriter and the carriage will move to the next tab setting or right margin setting.
The SHIFT instruction allows one to change the mode of the calculator's keyboard. If the calculator keyboard were un-shifted and a SHIFT instruction was given, then the calcula-tor keyboard would be in the shifted mode. In the shifted mode of operation, the calculator instructions and the typewriter character typed or the function performed have the correspondence shown by the characters and symbols printed below the keys of Figure 12.

; ' ~ .
- ~ , -~058766 The shif-ted calculator keyboard can control the typewriter's small letter alphabet and th~ symbols above the numbers and in addition, the functions TAB CLEAR ALL (CLEAR ALL TABS), -TAB SET, CR/LF, SPACE, BACK SPACE. The FMT instruction and the blank keys shown in the diagram will terminate the in-struction sequence. The operation of the PRINT and SHIFT
instructions on the shifted calculator keyboard are the same as on the unshifted keyboard. The two instructions that require special mention on the shifted calculator key-board are the CR/LF instruction and the RED RIBBON instruction.
The CR/LF instruction will cause the typewriter to perform a carriage return and line feed. In addition, this instruction wi11 cause the calculator keyboard to become unshifted.
A RED RIBBON instruction will cause the typewriter to type in red. Once red ribbon is selected, only two things can reset the red ribbon, they are, giving a BLACK RIBBON instruction (available on the calculator's unshifted keyboard) or switching the calculator interface OFF. Terminating the TYPING MESSAGES
instruction sequence will not reset a RED RIBBON instruction.
THE MESSAGE component of a TYPING MESSAGES instruction sequence may be any number of program steps (limited only by the size of the calculator memory). However, a typewritten line must not be allowed to exceed the right margin setting. If the right margin setting is exceeded, the program will stop at the second memory location following the instruction that exceeded the right margin setting and the STATUS lamp will light.
(It should be noted that if the right margin setting is exceeded in a typing data instruction sequence, the program will stop at the memory location imme-diately following the PRINT instruction that exceeded the right margin setting.) ..

~OS87~i6 Because of the two things an operator must keep track of, an example of TYPING MESSAGES is potentially confusing. For example, i~ the instruction "A" were placed in a MESSAGE, the operator could not easily predict whether the character typed would be "A" or "a", further, the color would be unknown.
Which character and which color would, of course, depend on whether the calculator keyboard were shifted or unshifted and the status of the ribbon color. The following format makes keeping track of these two things easier and, therefore, helps clarify the examples.

_ _ _ ~ _~ ~
s . ._ ' ' - ,.

The format is essentially the standard programming pad format with five additional columns: B, R, S, U and PROG INST.
Mark the B and R column so that you will know the status of the ribbon color, red or black. In the S and U columns, you can mark the mode of the calculator keyboard when the instruction is given - S for shifted, U for unshifted. In the PROG INST column you can record the typewriter instruc-tion that, considering the mode of the calculator keyboard, corresponds to the instruction in the KEY column. In the following examples, the PROG INST column will not be used except for typewriter instruction sequences.

~ , ~(~S8766 To type messages the typewriter's LEFT MARGIN STOP and PAPER
GUIDE are set to zero. The typewriter carriage is positioned against the LEFT MARGIN STOP. A piece of paper 8-1/2" or wider is placed in the typewriter and the RIGHT MARGIN STOP
set to seventy. The number 123.45 is keyed into the calcu-lator's x-register and a display mode of FIX ( ), 3 selected.
In this example, the MESSAGE "The value is" wiIl be typed followed by the data just entered into the calculator's x-register. This is accomplished by keying in the following instructions:

. STrp _ 3R iU _ PROG. iNs-r~ KEY COOE X
0000 F MTF MT 42 123 .450 4 _ _ _ _ 2 2 21 123 45 6 _ _ _ _ FM2T FMT 42 7 FMT FMT 42 ..
a_ _ BLK RIBS/R 77 ..
g_ CR/LF CLR 20 ..
0 010 _ T X T O 2 3 l_ $ H I F T U P 27 6 v A 6~, = = =
. a e E60 2l s YT0 40 3 _ l PR I NT PNT 45 ..
4s _ l FMT FMT 42 TYPE-OUT: The value is 123.45 Steps 0000-0004 The ~ m w.d instruction sequence established a field of seven with two digits to the right of the decLmal point.
The data point (123.45) requires a field width of six setting the width to seven will ensure that there wili be a space between the data and the last character typed.

, ~058766 Steps 0008-0009 The BLK RIBBON instruction in step 0008 will ensure that the MESSAGE in this example is typed in black. Prior to that time the status of the ribbon color was unknown; therefore, neither the B or R column was filled in.
The CR/LF instruction in step 0009 will ensure th~ MESSAGE
is typed against the LEFT MARGIN STOP.

The next example performs the same type of operation with the instruction sequences used in a slightly different manner.
In this example the TYPING MESSAGES instruction sequence will be used to type the message "123.45 squared -" in black and then set the red ribbon. Next a TYPING DATA instruction sequence is used to set a field width of ten with four digits to the right of the decimal point, and type the data contained in the x-register.
If the number 123.45 is not still in the x-register from the last example, it is entered into the x-register and the fol-lowing calculator keys are depressed in the order given:

STEP BRSUPROG. INST. KEY COOE .. __ .
u000 _ _ _ U P 27 123.45 123.45 1 _ _ X 36 t 23.45 15239.9025 2 _ _ _ON 25 15239.9025 _ 3 _ _ FMT FMT 42 " ., 4 l _ 2 2 02 " "
5 ~ _ ~ FMT FMT 42 " "
76 j _ _ CR/LF CLR 20 8 1- - 2--2 02 _ u010 _--5 -5 21 , ~ __ 3 _SPACECNT 47 ,. ., 4 SH I FTUP 27 " "
sYTO 40 6 q b 14 " "
7 ul/X 17 " "
8 a a 62 ' u020 1 e E 60 2 SPACECNT 47 " "
3 _ 34 ,. " , 4 RED RIB S/R 77 " "
s FMT FMT 42 " "
., 6 _ FMT FMT 42 . "
7 _ _ 2 --2 02 "
- 8 _ _ 1 1 01 " ..
9 O O 00 .. ., 1 _ _ 4 4 21 .
2 _ _ PR I NT PNT 45 __ . .. _ . . _ . .

, :

1~5~37~i6 In the last example, a BLK RIBBON instruction was given. Since then, the ribbon color has not been changed. Therefore, in step 0003, the B column can be filled in even though a BLK RIBBON instruction was not given.
At step 0024 a RED RIBBON instruction is given so that the data in the x-register will be typed in red. Remember, the red ribbon can be reset to black ribbon by two things only, giving a BLK RIBBON instruction or turning the typewriter interface OFF.
TYPE-OUT: 123.45 Squared = 15239.9025 It may be noticed that there is no space in the type-out between the "="
and the data. That can be corrected in two ways:
1. Setting the w specification to eleven.
2. Inserting a SPACE instruction immediately following the "=" instruction.
The instruction sequence FMT, 2, LIST allows the user to list a programcontained in the calculator memory. The listing will be typed in a column format with each line consisting of the memory location, the mnemonic of the instruction stored in the location and the key code of the instruction.
The listing will begin at the location of the program counter when this instruction sequence is given and will continue until either an END in-struction is given or STOP on the calculator keyboard is pressed.
(It should be noted that if the ribbon color status is red, the listing will be typed in red.) This may be illustrated by entering a typewriter exerciser program intothe memory of the calculator and then:
PRESS: END FMT 2 LIST
TYPE-OUT:

0001-- *---36 - \
~)58766 KEY CODES AND MNEMONICS
All of the keys of the keyboard input unit and their associated octal keycodes and mnemonics are listed in Table D belowO Every key has only one keycode and only one mnemonic (if it has a mnemonic), regardless of how many different functions it may be used to perform. The keycodes for the FLOAT, FIX ( ), RUN, PRGM, KEY LOG, LIST, LOAD, RECORD, BACK STEP, and STEP PRGM keys are applied to the CPU in seven-bit binary ~orm. Since these keycodes are used only to control the mode of the calculator, are not programmable, and are never printed out by the output printer unit, they have no associated mnemonic. All of the remaining keycodes are applied to the CPU in six-bit binary form, are pro-grammable, and have a mnemonic that may be printed out by the output printer unit.
, . _ . . .................. . . ................ . _ '105~766 TABLE D
KEY
KEY CODE MNEMONIC KEY CODE MNEMONIC

1 01 ~ 45 PNT

4 04 4IF x=y 50 X=Y

6 06 6IF x<y 52 X<Y
7 07 7IF x>y 53 X>Y

x2 12 XSQ ~ 56 a 13 a PAUSE 57 PSE
b 14 b E 60 E

l/x 17 l/X D 63 D
CLEAR 20 CLR int x 64 INT
. 21 . I 65 ROLL t 22 RUP B 66 B
g~() 23 XTO x-() 67 XFR
y~() 24 YE M 70 M
~ 25 DN O 71 0 - t 27 UP N 73 N
x~y 30 XEY ~ 74 CHG SIGN- 32 CHS ~ 76 ~-. 35 DIV LOAD 103 X 36 x LIST 104 CLEAR x 37 CLX KEY LOG 105 y~() 40 YTO PRGM 106 FMT 42 FMT FIX () 110 I~ FLAG 43 IFG FLOAT 110 PROOE SSING KEYCODES
The manner in which keycodes entered into the CPU from the keyboard input unit or from the program storage section of the memory unit are processed is shown and described in the keycode processing ~low chart o~ Figure 13. Once the calculator is turned on, it operates in the display routine until a key is depressed. If a FLOAT, ~IX (), RUN, PRG~, KEY
LOG, LIST, LOAD, RECORD, BACK STEP, or STEP PRGI~ key (each having a seven-bit keycode) is depressed, the calculator operates in a director routine to determine which o~ these keys was depressed and thereupon selects the routine ~or per-~orming the ~unction required by that key. Upon completion o~ the selected rout~ne, the calculator reverts to operation in the display routine.
I~ any other key (each having a siæ-bit ~eycode), ex-cept the CONTINU~ key, is depressed and the PRG~ key-has not been depressed or has been ~ollowed by the R~N key, the cal-culator operates in the interpreter routine to determlne which six-bit keycode it has recei~ed and to select the ap-propriate routine ~or per~orming the ~unction required by that six-bit keycode. Upon completion o~ the selected routine the calculator reverts to operation in the display routine.
I~ the CONTINUE key is depressed and the PRG~ key has not been depressed or has been ~ollowed by the R~N key,.the calculator operates in a ~etch routine to sequentially ~etch keycodes, as designated by the user program counter, ~rom the program storage section o~ the RW~. Each ~etched keycode is interpreted and-the routine ~or per~orming the ~unctlon re-quired thereby selected in the same manner as i~ the ~etched keycode had been received ~rom the keyboard input unit.

` -163-. .
.. , ~ .

lOS~3766 ~owever, upon completion o~ the selected routine the calculator reverts to the ~etch routine unless the ~etched keycode was a STOP, END, or PAUSE (if the execution of the PAUSE is im-mediately ~ollowed by depression of a key), in which cases the calculator reverts to operation in the display routine.
I~ any key ha~ing a six-bit keycode is depressed and the PRGM key has been depressed and has not been followed by the RUN key, the calculator operates in a store routine to store the six-bit keycode received from the keyboard input unit as a program step in the progra~ storage section of the RWM. Upon completion of this storage operation the cal-culator reverts to operation in the display routi~e.
I~ the KEY LOG key has been depressed and has not been ~ollowed by the RUN key or the PRGM key, the calculator also prints out each si~-bit keycode received ~rom the keyboard input unit in any of the above-mentioned cases.
The display routine, the director routine, the inter-preter routine, the routines ~or per~orming the various functions required by the siæ-bit and seven-bit keycodes, and other routines used by the calculator are sho~n and de-scribed in Figures 14-135.

-16~-., . ~ . :

lOS8766 BASIC INSTRUCTION SET
Every routine and subroutine of the calculator comprises a sequence of one or more of 71 basic sixteen-bit instructions listed below. These 71 instructions are all implemented serially b~ the micro-processor in a time period which varies according to the specific instruction, to whether or not it is indirect, and to whether or not the skip condition has been met.
Upon completion of the execution of each instruction, the program counter (P register) has been incremented by one except for instructions JMP, JSM, and the skip instructions in which the skip condition has been met. The M-register is left with contents identical to the P-register. The contents of the addressed memory location and the A and B registers are left unchanged unless specified otherwise.
Memory Reference Group The 14 memory reference instructions refer to a specific address in memory determined by the address-field ~mb, by the ZERO/CURRENT
page bit, and by the DIRECT/INDIRECT bit. Page addressing ~nd indirect addressing are both described in detail in the reference manuals for the Hewlett-Packard Model 2116 computer (hereinafter referred to as the HP 2116).
~he address field <m> is a 10 bit field consisting of bits O
through 9. The ZERO/CURRENT page bit i~ bit 10 and the DIRECT/INDIRECT bit is bit 15, except for reference to the A
or B register in which case bit 8 becomes the DIRECT/INDIRECT
bit. An indirect reference is denoted by a <,I> following the address <m>.
REGISTER REFERENCE OF A OR B REGISTER: If the location <A> or <B> is used in place of <m> for any memory reference instruction, the instruction will treat the contents of A o~ B exactly as it would the contents of location <m~. See the note below on the special restriction for direct register reference of A or B.
ADA m,I Add to A. The contents of the addressed memory location m are added (binary add) to contents of the A register, and the sum remains in the A register, If carry occurs from bit 15, the E register is loaded with OOOl, otherwise E is left unchanged.
ADB m,I Add to B. Otherwise idelltical to ADA;

~OS~7~6 Memory Reference Group (continued) CPA m,I Compare to A and skip if unequal. The contents of the addressed memory location are compared with the contents of the A register. If the two 16-bit words are different, the next instruction is skipped; that is, the P and M
registers are advanced by two instead of one. Otherwise, the next instruction will be executed in normal sequence.
CPB m,I Compare to B and skip is unequal. Otherw~se identical to CPA.
LDA m,I Load into A. The A register is loaded with the contents of the addressed memory location.
LDB m,I Load into B. The B register is loaded with the contents of the addressed memory location.
STA m,I Store A. The contents of the A register are stored into the addressed memory location. The previous contents of the addressed memory location are lost.
STB m,I Store B. Otherwise identical to STA.
IOR m,I "Inclusive OR" to A. The contents of the addressed location are combined with the contents of the A register as an "INCLUSIVE OR" logic operation.
ISZ m,I Increment and Skip if Zero. The ISZ instruction adds ONE to the contents of the addressed memory location. If the result of this operation is ZERO, the next instruction is skipped; that is, the P and M registers are advanced by TWO instead of ONE. The incremental value is written back into the addressed memory location. Use of ISZ with the A or B register is limited to indirect reference; see foot-note on restrictions.
AND m,I Logical "AND" to A. The contents of the addressed location are combined with the contents of the A register as an "AND" logic operation.
DSZ m,I Decrement and Skip if Zero. The DSZ instruction subtracts ONE from the contents of the addressed memory location. If the result of this operation is zero, the next instruction is skipped. The decremented value is written back into the addressed memory location Use of DSZ with the A or B register is limited to indirect reference; see footnote on restrictions.

, .

lOS8766 JSM m,I Jump to Subroutine. The JSM instruction permits jumping to a subroutine in either ROM or R/W memory. The contents of the P register is stored at the address contained in location 1777 (stac~ pointer). The contents of the stack pointer is incremented by one, and both M
and P are loaded with the referenced memory location.
JMP m,I Jump. This instruction transfers control to the contents of the addressed location. That is, the referenced memory location is loaded into both M and P registers, effecting a jump to that location.

Shift-Rotate Gro~
The eight shift-rotate instructions all contain a 4 bit variable shift field <n> which permits a shift of one through 16 bits;
that is, 1 < n < 16. If <n> is omitted, the shift will be treated as a one bit shift. The shift code appearing in bits 8,7,6,5 is the binary code for n-l, except for SAL and SBL, in which cases the complementary code for n-l is used.

AAR n Arithmetic right shift of A. The A register is shifted right n places with the sign bit (bit 15) filling all vacated bit positions. That is, the n+l most significant bits become equal to the sign bit.
ABR n Arithmetic right shift of B. Otherwise identical to AAR.
SAR n Shift A right. The A register is shifted right n places with all vacated bit positions cleared. That is, the n most significant bits become equal to zero.
SBR n Shift B right. Otherwise identical to SAR.
SAL n Shift A left. The A register is shifted left n places with the n least significant bits equal to zero.
SBL n Shift B left. Otherwise identical to SAL.
RAR n Rotate A right. The A register is rotated right n places, with bit O rotated around to bit 15.
RBR n Rotate B right. Otherwise identical to RAR.

~, ~

Alter-Skip Group The sixteen alter-skip instructions all contain a 5-bit variable skip field <n> which, upon meeting the skip condition, permits a relative branch to any one of 32 locations. Bits 9,8,7,6,5 are coded for positive or negative relative branching in which the number <n> is the number to be added to the current address, (skip in forward direction), and the number <-n> is the number to be subtracted from the current address, (skip in negative direction). If <n> is omitted, it will be inter-preted as a ONE.
<n>=O CODE=OOOOO REPEAT SAME INSTRUCTION
<n>=l CODE=OOOOl DO NEXT INSTRUCTION
<n>=2 CODE=OOO10 SKIP ONE INSTRUCTION
<n>=15 CODE=Ollll ADD 15 TO ADDRESS
<n>=-l CODE=lllll DO PREVIOUS INSTRUCTION
<n>=-16 CODE=10000 SUBTRACT 16 FROM ADDR~SS
<n>=nothing CODE=OOOOl DO NEXT INSTRUCTION
The alter bits consist of bits 10 and bits 4. The letter <~>
following the instruction places a ONE in bit 10 which causes the tested bit to be set after the test. Similarly the letter <~j will place a ONE in bit 4 to clear the test bit. If both a set and clear bit are given, the set will take precedence.
Alter bits do not apply to SZA, SZB. SIA, and SIB.
SZA n Skip if A zero. If all 16 bits of the A register are zero, skip to location defined by n.
SZB n Skip if B zero. Otherwise identical to SZA.
RZA n Skip if A not zero. This is a "Reverse Sense" s~ip of SZA.
RZB n Skip if B not zero, Otherwise identical to RZA.
SIA n Skip if A zero; then increment A. The A register is tested for zero, then incremented by one. If all 16 bits of A were zero before incrementing, skip to location de~ined by n.
SIB n Skip if B zero; then increment B. Otherwise identical to SIA.
RIA n Skip if A not zero; then increment A. This is a "Reverse Sense" skip of SIA.
RIB n Skip if B not zero; then increment B. Otherwise identical to RIA.
SLA n,S/C Skip if Least Significant bit of A is zero, If the least significant bit (bit O) of the A register is zero, skip to location defined by n, If either S or C is present, the test bit is altered accordingly after test.

lOS87~i6 Alter-Skip Group (continued) SLB n,S/C Skip if Least Significant bit of B is zero. Other-wise identical to SLA.
SAM n,S/C Skip if A is Minus. If the sign bit (bit 15) of the A register is a ONE, skip to location defined by n. If either S or C is present, bit 15 is altered after the test.
SBM n,S/C Skip if B is Minus. Otherwise identical to SAM.
SAP n,S/C Skip if A is Positive. If the sign bit (bit 15) of the A register is a ZERO, skip to location defined by n.
If either S or C is present, bit 15 is altered after the test.
SBP n,S/C Skip if B is Positive. Otherwise identical to SAP.
SES n,S/C Skip if Least Significant bit of E is Set. If bit O of the E register is a ONE, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively.
SEC n,S/C Skip if Least Significant bit of E is Clear. If bit O of the E register is a ZERO, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively.
Complement-Execute-DMA Group.
These seven instructions include complement operations and several special-purpose instructions chosen to speed up printing and extended memory operations.
CMA Complement A. The A register is replaced by its One's complement.
CMB Complement B. The B register is replaced by its One's complement.
TCA Two's Com~lement A. The A register is replaced by its One's Complement and incremented by one.
TCB T~o's complement B. The B register is replaced by its One's Complement and incremented by one.
EXA Execute A. The contents of the A register are treated as the current instruction, and executed in the normal manner.
The A register is le~t unchanged unless the instruction code causes A to be altered.
E B Execute B. Otherwise iden~ical to EXA.
DMA Direct Memory Access. The DMA control in Extended Memory is enabled by setting the indirect bit in M and giving a WTM
instruction. The next ROM clock transfers A~M and the following two cycles transfer B~M. ROM clock then remains inhibited until released by DMA control.

Note: Special Restriction for Direct Register Reference of A or B
For the five register reference instructions which involve a write operation during execution, a register reference to A or B must be restricted to an INDIRECT reference. These instructions are STA, STB, ISZ, DSZ, and JSM. A DIRECT register reference to A or B with these instructions may result in program modification.
(This is different from the hp 2116 in which a memory reference to the A or B register is treated as a reference to locations O
or 1 respectively.) A reference to location O or 1 will actually refer to locations O or 1 in Read Only Memory.

Input/Output Group (IOG) The eleven IOG instructions, when ~iven with a select code, are used for the purpose of checking flags, setting or clearing flag and control flip-flops, and transferring data between the A/B
registers and the I/O register.
TF <SC> Set the flag. Set the flag flip-flop of the channel indicated by select code <SC>.
LF <SC> Clear the flag flip-flop of the channel indicated by select code <SC>.
FC <SC> Skip if flag clear. If the flag flip-flop is clear ~n the channel indicated by <SC>, skip the next instruction.
FS <SC> H/C Skip if flag set, If the flag flip-flop is set in the channel indicated by <SC>, skip the next instruction, H/C indicates if the flag flip-flop should be held or cleared after executing SFS.
LC <SC> H/C Clear control. Clear the control flip-flop in the channel indicated by <SC>. H/C indicates if the flag flip-flop should be held or cleared after executing CLC.
STC <SC> H/C Set Control. Set the control flip-flop in the channel indicated by <SC>. H/C indicates if the flag flip-$10p should be held or cleared after executing STC.
OT* <SC> H/C Output A or B. Sixteen bits from the A/B register are output to the I/O register. H/C allows holding or clearing the flag flop after execution of OT*.
The different select codes allow different functions to take place after loading the I/O register.
.......
SC=OO Data from the A or B register is output eight bits at a time for each OT*
instruction given. The A or B register is rotated right eight bits.

~05876~

Input~Output Group (IOG), continued SC=Ol The I/O register is loaded with 16 bits from the A/B registers.
SC=02 Data from the A/B register is output one bit at a time for each OT* instruction for the purpose of giving data to the Magnetic Card Reader. The I/O register is unchanged.
SC=04 The I/O register is loaded with 16 bits from the A/B register and the control flip flop ~or the printer is then ~et.
SC=08 The I/O register is loaded with 16 bits from the A/B register and the control flip flop for the display is then set.
SC=16 The I/O reglster is loaded with 16 bits from the A/B register and then data in th~
I/O register is transferred to the switch latches.
LI* <01> H/C Load into A or B. Load 16 bits of data into the A/B register from the I/O register. H/C allows holding or clearing the flag flop aiter Ll* has '' been executed. ' LI* <00~ The least significant 8 bits of the I/O register are loaded into the most significant locations in the A or B register.
MI* <01> H/C Merge into A or B. Merge 16 bits of data into the A/B register from the I/O register by "inclusive or". H/C allows holding or clearing the' flag ~lop after Ml* has been executed.
MI* <00~ The least significant 8 bits of the I/O register are combined by inclusive OR with the least significant 8 bits of the A or B register, and rotated to the most significant bit locations of the A or B register.

.~ .

105876~

MAC Instruction Group A total of 16 ~C instructions are available for operation (a) with the whole floating-point data (like transfer, shifts, etc), or (b) with two floating-point data words to speed up digit and word loops in arithmetic routines.
NOTE: <Ao 3> means: contents of A-register bit O to 3 AR 1 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1744 to 1747 (octal) AR 2 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1754 to 1757 (octal) Di means: mantissas i-th decimal digit;
most significant digit is Dl least significant digit is D12 decimal point is located between Dl and D2 Every operation with mantissa means BCD-coded decimal operation.
RET Return 16-bit-number stored at highest occupied address in stack is transferred to P- and M-registers. Stack pointer (=next free address in stack) is decremented by one.
~A>, <B>, <E> unchanged.
MOV Move overflow The contents of E-register is transferred to A . Rest of A-register and E-register are filled by zeros. 3 <B> unchanged.
CLR Clear a ~loating-point data register in R/W memory on location <A>
ZERO~<A>, <A>+l, <A>+2, <A>+3 <A>,>B>,<E> unchanged XFR Floating-poi~t data transfer in R/W memory from location <A> to location <B>, Routine starts with exponent word transfer.
Data on location <A~ ls unchanged.
<E> unchanged.

lOS~76ti MRX ARl mantissa is shifted to right n-times. Exponent word remains unchanged.
CBo 3> = n (binary co~ed) 1st shift: <Ao_3>~Dl; Di~Di+l; ~12 s jth shift: 4 ~ Dl; Di~Di+l; D12 nth shift: ~ Dl; Di~Di+l; D12 Ao_3 4} ~ E, A4_15 each shift: <Bo_3> - 1 ~ Bo_3 <B4_15> unchanged MRY AR2 mantissa is shifted to right n-times~
Otherwise identical to MRX
MLS AR2 mantissa is shifted to left once.
Exponent word remains unchanged.
; Di ~ Di-l; Dl 0_3 <B> unchanged DRS ARl mantissa is shi~ted to right once Exponent word remains unchanged 4 ~ Dl; Di ~ Di+l; D12 0-3 ZERO ~ E and A4_15 ~B> unchanged DLS ARl mantissa is shifted to le~t once. Exponent word remains unchanged.
> ~ D12; Di ~ Di-l; Dl 0_3 ~ ~ E, A4 15 <B> unchanged FXA Fixed-point addition Mantissas in pseudo-registers AR2 and ARl are added together and result is placed into AR2. Both exponent words remain unchanged. When overflow occurs "OOOl"
is set into E-reg., in opposite case <E> will be zero.
~AR2> + <ARl> + DC ~ AR2 DC = ~ i~ <E> was OOOO be~ore routine execution DC 3 1 if <E~ was 1111 before routine execution <8>, <ARl> unchanged ;;

lOS~3766 FMP Fast multiply Mantissas in pseudo-registers AR2 and ARl are added together <Bo 3>-times and result is placed into AR2.
Total decimal overflow is placed to Ao 3. Both ex-ponent words remain unchanged.
<AR2> + <ARl~ * <Bo 3>+DC ~ AR2 DC = O if <E> was 0000 before routine execution DC = l if <E> was 1111 before routine execution ZERO ~ E~ Ag_l5 <ARl> unchanged FDV Fast divide Mantissas in pseudo-registers AR2 and ARl are added together so many times until iirst decimal overflow occurs. Result is placed into AR2. Both exponent words remain unchanged. Each addition without over-ilow causes +l increment of <B>~
1st addition: <AR2> + <ARl> + DC ~ AR2 DC = 0 if <E> was 0000 before routine execution DC = l if <E> was llll before routine execution next additions: <AR2> + <ARl> ~ AR2 ZERO ~ E
<ARl> unchanged CMX 10's complement of ARl mantissa is placed back to ARl, and ZERO is set into E-register. Exponent word remains unchanged <B> unchanged CMY lO's complement of AR2 mantissa.
Otherwise identical to CMY
MDI Mantissa decimal increment.
Mantissa on location <A> is incremented by decimal ONE
on Dl2 level, result is placed back into the same location, and zero is set into E-reg.
Exponent word is unchanged.
When overilow occurs, result mantissa will be 1,000 0000 0000 (dec) and 0001 (bin) will be set into E-reg.
<B> unchanged.
NRM Normalization Mantissa in pseudo-register AR2 is rotated to the left to get Dl ~ 0. Number of these 4-bit leit shifts is stored in Bo_3 ln`binary form (<B4_15~=O) when<B0_3>= 0,1,2,, ~ . , 11 (dec) ~ <E> = 0000 When<B0 3>= 12 (dec) ~mantissa is zero, and ~E>=0001 Exponent word remains unchanged <A> unchanged.

--17g--~05~37t;~

The binary codes of all of the above instructions are listed in the following coding table, where * implies the A or B register, D/I means direct/indirect, A/B means A register/B register, Z/C means zero page (base page) current page, H/S means hold test bit/set test bit, and H/C means hold test bit/clear test bit. D/I, A/B, Z/C, H/S, and H/C are all coded as 0/1.
CODING TABLE
.
GROUP OCTAL INSTR ~ 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEMORY -O---- AD* I D/I O O O A/B Z/C + MEMORY ADDRESSREFERENCE -1---- CP* ¦ D/I O O 1 A/B Z/C
GROUP -2---- LD* ¦ D/I O 1 0 A/B Z/C
-3---- ST* I D/I O 1 1 A/B Z/C

4_ _ ISZ D/I 1 0 0 1 Z/C

SHIFT- 07---0 A*R O 1 1 1 A/B-- + SHIFT ~- O O O O
ROTATE CODE
GROUP 07---2 S*R O 1 1 1 A/B-- - O 0 1 0 07---4 S*L O 1 1 1 A/B-- - O 1 0 0 07---6 R*R O 1 1 1 A/B-- - O 1 1 0 _ .
ALTER- 07---0 SZ* O 1 1 1 A/B O SKIP~ 0 1 0 0 0 SGKROUP 07---0 RZ* O 1 1 1 A/B 1 CODE 0 1 0 0 0 07---0 SI* O 1 1 1 A/B O 1 1 0 0 0 07---0 RI* O 1 1 1 A/B 1 1 1 0 0 0 07---1 SL* O 1 1 1 A/B H/ l H/C 1 0 0 1 07---2 S*M O 1 1 1 A/B H/ l H/C 1 0 1 0 07---3 S*P O 1 1 1 A/B H/ l H/C 1 0 1 1 07---4 SES O 1 1 1 A/B H/ l H/C 1 1 0 0 07_--5 SEC O 1 1 1 A/B H/ l H/C 1 1 0 1 . .

CONTINUED

lOS~7f~6 CODING TABLE - CONTINUED
.. .

._ COMP 07-016 EX* O 1 1 1A/B - - _ _ O 0 1 1 1 0 EXECUTE 070036 DMA 0 1 1 1 O - _ _ _ 0 1 1 1 1 0 DMA 07-056 CM* O 1 1 1A/B - - _ 1 0 1 1 1 0 07-076 TC* O 1 1 1A/B - - _ _ 1 1 1 1 1 0 .. _ _ _ . .. _ _ _ _ .
INPUT 1727-- STF 1 1 1 1 _ 1 0 1 1 1 1 ; SELECT )OUTPUT 1737-- CLF 1 1 1 1 _ 1 1 1 1 1 1 CODE

17-1-- OT* 1 1 1 1A/B 1H/C O O 1 1 17-2-- LI* 1 1 1 1A/B 1H/C 0 1 0 17-0-- MI* 1 1 1 1A/B 1H/C O O O
. _ _ .. _ . .

~058766 Each o~ the 71 basic instructions employed by the calculator is implemented by one or more o~ the above-described microinstructions and associated control signals issued by the microprocessor. The manner in which th~s is accomplished is shown and described in detail in the flow charts of Figures 138A-H. Each rectangular box o~ these ~low charts represents a state of RO~ 200 of the microprocessor and includes the mnemonic o~ the microinstructions and con-trol signals stored in that RO~ state. The number at the upper right-hand corner o~ each o~ these rectangular boxes represents the number o~ shi~t cloc~ pulses required by the microinstructio~s of that RO~ state. A slmpli~ied overview of these detailed ilow charts is shown in Figure 7.
PROGRA~ABLE CLOC~
Given a computing system organized to process binary data serially and under controI of microinstructions stored in RO~ 200 as shown in Figures 3A-B and 136, the implementation o~ a general purpose instruction set requires that some number of bits be shi~ted into or out of the storage registers.
Depending on the operation being per~ormed, the number o~ bits may vary from zero to n, where n is the number of bits in a single machine word.
If each clock period of the ROM clock corresponds to a one bit shi~t, a count loop must be emplo~ed to provide the desired number of shi~ts. A rather large number o~ such count loops would e~ist in order to implement an ent~re instruction set. An alternative method is to provide additional hardware which permits assignment o~ the desired number of shifts in a single state oi ROM 200. Such an arrangement regu~res a variable cycle time ~or each state of ROM 200, but results -, :

in a very substantive saving in total number of ROM states.
To implement a variable number of shift clocks in a single state of the microprocessor, two separate clocks are required. The shift clock is applied to the data storage registers in the memory, the shift register block, the arith-metic logic unit and the input/output block. The ROM clock is applied to the ROM address flip-flops in the microprocessor, and occurs once for each state in the microprogram. The number of shift clock pulses that occur in any given ROM state is determined by a 4-bit clock code sent to the clock decoder from the microprocessor.
If no shift clocks are desired, a separate signal from the microprocessor inhibits the shift clock output, independent of the clock code issued in that state. In this way, any number of shifts between and including zero and 16 may be implemented with a 4-bit clock code and an inhibit signal.
This inhibit signal offers an additional powerful ~eature when gated by the qualifier test logic in the micro-processor as shown in Figure 1360 The qualifier test logic includes a 4-bit qualifier code from ROM 3 that selects one of 16 qualifier inputs to the data selector. The data selector output QN (qualifier not met) will be high if the selected qualifier input was low. By using the QN signal to gate the inhibit microinstruction~ IQN, the shift clock will be inhibited only when the qualifier is not met. Thus all microinstructions requiring shift clocks that are issued in a given RO~ state may be either executed or inhibited, depending on the logical state of the qualifler under test.
The RO~ clock is applied to the eight J-K flip-flops .. ..
. . ~ . - ..

which addxess the 256 word microprocessor ROM. During ~ny given state, the compleme~ting (J-K) inputs to the 4 pri-mary address flip-flops are set up by the quali~ier code or q-register code. The 4 secondary address flip-flop inputs are determined by the ROM 4 outputs, the BRC microinstruction, and the data seIector output QN. Where ROM clock goes low, the negative edge-triggered flip-flops will cause transi-tion o~ the ROM address to the next ROM state.
~s shown in the block diagram of Figure 139 and the detailed schematic diagram o~ Figures 140A-C, a crystal con-trolled system clock output is inverted to generate memory clock, MCE. This signal is again inverted to clock a D
flip-~lop haYing an output (control clock), which will go low if the end-of-count signal (borrow) ~rom the down counter has occurred at the D input. The RO~ clock will also go low at this time, initiati~g a new RO~ state in the microprocessor.
Control clock will normally remain low for one system clock period, a~d in turn generates a load signal which is delayed a hal~ period from control clock by means of a second D flip-flop. The 4-bit clock code from the microprocessor is pre-set into the counter while the load signal is low.
As the load signal goes high, RO~ clock also goes high, completing the ~ixed interval portion of R~ clock and shi~t clock as shown in Figure 141. A series o~ clock pul~es are now gated onto shift cloc~, SCK, until the preset counter has counted down to zero, causing control clock to again go low, completing the ROM cycle.
The inhibit signal, ~R~-, from memory may lengthen the normal ~ixed Interval of ROM clock by clearing the D flip-~lop and holdin~ control clock low~ This may occur during .

105~3766 memory refresh or e~tern~l test operationsO In this situation, the counter remains preset and the correct number of shifts will be generated when the inhibit goes away.
SHIFT REGISTER UNIT
As shown in the detailed schematic diagrams of Figures 137A-D and 142A-D, A-register 122, B-register 124, P-.
register 126, Q-register 128, and E-register 130 comprise bipolar status registers, the contents of which are recir-culated when data is output to the R-bus or the S-bus.
Full control o~ these registers in use and type of opera-tions perfor~ed is maintained by the microinstructions ~rom the from the microprocessor. The number of bits to be shifted in any one ROM state of the microprocessor is determined by the number of shift clocks from the clock de-coder. This shi~t clock appears at the shi~t clock input of each shift register that is enabled by the microprocessor during that ROM cycle.
M ITE~ETIC LOGIC UNIT
The development of complex read-only memory arrays on a single chip haYe made possible a hardw ~e implementa-tion of ce~tral processing units (CP~s) and arithmetic logic units (AL~s) with far fewer components than were previously possible. In this application, two bipolar read-only memory chips are combined ~ith carry flip-~lops and adapted to perform one-bit binary logic and arithmetic operations as well as four-bit binary coded decimal (BCD) arithmetic opera-tions. The two bipolar read-only memory ch~ps may comprise, for example, Eewlett-Packard 16-pin dual~ line pack~ged bipolar RO~s or anized into 256 words by 4-bits and of the same . .
type a~ shown and described in U.S. Patent 3,721,964 isqued Mbrch 20, 1973.

~, .. . .. . . .. _ ... _ _ .. . _ _ . . . ..

The binary/BCD Arithmetic Logic Unit consists of ~ive integrated circuits connected as shown in the block diagram of Figure 143 and the detailed schematic diagram of Figures 142A-D. Specifically, the pac~ages consist of two 1024-bit ROMs, a dual D-type flip-flop and two quad two-input ~AND gates. The function code input '~CD" selects be~ween the binary mode and BCD mode of operation In the binary mode, the ~unction code inputs ACO, ACl~ and AC2 select the desired logical i'unction or arith-metic operation as give~ in Figure 144. The binary input data enters ROM ~1 on the caxry, S-bus and R-bus i~put lines, and the binary result appears on the T-bus aud bi~ary carry output lines. RQ~ ~2 is not used in the bi~ary mode.
In the BCD mode oi operation, the two function code lines ACO and ACl are d~sabled from the ~icro-processor and these two lines carry the T02 and T03 bits o~ BCD data from the T-Regi~ter.
The AL~ function code line AC2 is used to select the desired BCD operation. If AC2 is lo~, the ~our-bit output ~0~ 2~3 will be the BCD sum of the two BCD data ijputs. I~ AC2 is high a~d decimal carry has beeD set, the ~our-bit output EoJ~ 2,E~
will be the ~CD Tens Complement o~ the BCD data from the T-Register. In the 8CD mode, the bi~ary carry output will be disabled and the decimal carry output will be enabled to ROM ~1.
Although only one-~ourth o~ the available registers in RO~ #l are required ~or the eight bi~ary operations, the concept o~ adding a second 1024-bit ~0~ to perform the BCD
operations grew ~rom several basic concepts:
1) The least significant BCD sum bit, ~0, is always identical to the binary sum bit; therefore, only three ad~itional outputs, rl, ~ , and E3 need be generated~ For BCD complement opcrations, the decimal carry flip-~lop defines whether or not the - least significant bit should be complemented.

-~05-,. . ..

lOS8766 2) In formin~ thc "nine's complemollt" Or tlle T-~e~istcr BCD data in ROM #l, it can be seell that for 8~21 code the second least significant bit TOl is the same before and after forming the complement. Thus only two bits, T02 and T03 need be complemcntcd prior to input into ROM #2. The ten's complement with add is then found by presetting decimal carry and performing a BCD sum of the three most significant digits in ROM ~2.

3) With only eight ROM inputs available, some sharing of inputs is required for ROM #l. During binary operations, all four function codes and only one bit of T-Register data is required. During BCD
operations, all four bits of T-Register data and only two function codes are required. Use of two NAND
gates in wire-OR connection with the open collector function codes ACO and ACl permits sharing of the two inputs.
This arrangement left one input still available to ROM ~2.
By programming this input to always make output DCI true, the micro-instruction UTR can se~ve two purposes--placing units on the R-bus and also set decimal carry if BCD is true. When BCD is false, cloc~ is inhibited to decimal carry. This feature permits saving decimal carry information during all binary operations. Similarly, binary carry is saved during the four binary operations AND, IOR, XOR, and ZTT by connecting AC2 such that when AC2 is false the shift clock is inhibited to the binary carry flip-flop In summary, the mode select input "BCD" performs the following functions:
l) Addresses the proper 128 word set of word lines in ROM #l.
2) Enables the T02 and T03 data lines to ROM #l only in BCD mode.
3) Enables clock to decimal carry flip-flop only in BCD mode.
4) Selects binary carry or decimal carry into ROM #l as appropriate.
) BCD mO~Ire ou put~ ~0~ 2~3 to A Re~istcr only in -~06-The remaining three ALU function codes select the proper set of wor~ .in'es in RO~ to perform tne eight binary functions listed in Figure 144. In addition, the AC2 input performs the following functions.
1) Enables clock to binary carry flip-flop only during the four carry-related binary functions and the BCD comp/add function.
2) In the BCD mode, AC2 causes BCD data bit TOO, TO2 and TO3 to convert to nine's complement form.
The ALU has a total of 15 inputs which include 8 data inputs, 2 clock inputs and 5 microinstructions. Four data output lines are required, and two additional output lines from carry flip-flops are available as qual-ifier inputs to the microprocessor. The ALU and shift register mnemonics are listed in the following table:
SHIFT REGISTERS & ALU BOARD MNEMONICS
TRE T-Register to E-Register to R-Bus TO0 Bit 0 of T-Register TBE T-Bus to E-Register to R-Bus TTX - TEST T-Bus to A/B-Register from Tester TTX - I/O T-Bus to A/B-Register from I/O (Board #12) TTX - ROM T-Bus to A/B Register from ~-Processor - (Board #13) TTX Logical "OR" of Three TTX Signals AB Status of AB-Flip-Flop AB = O A-Reg. Operation AB = 1 B-Reg. Operation XTR A/B Register to R-Bus UTR Logical "1" to R-Bus TQR Q-Register to Primary Address Flip-Flops AB Complement of AB
TTP T-Bus to P-Register SCK Shift Clock QP0 Qualifier, Bit 0 of P-Register PTR P-Register to R-Bus , .

~58~66 SHIFT REGISTERS ~ ALU BOARD MNEMONICS (Continued) Q00 . Q-Register Bit 0 QTR Q-Register to R-Bus RCK ROM Clock QAB Q-Register to Ab-Flip-Flop, also clears decimal carry.
SCB Set Binary Carry QDC Qualifier, Decimal Carry BCD Decimal Arithmetic AC2 ALU Operation Code QBC Qualifier, Binary Carry S-BUS Data Bus ACl ALU Operation Code ACP ALU Operation Code T02 Bit 2 of T-Register T03 Bit 3 of T-Register SDR Signal to Disable ROMs TOl Bit 1 of T-Register T-BUS Data Bus ALU Arlthmetlc Logic Unit ( ) Indicates Negative True Signal Figure 145 lists five dual-in-line integrated circuits that may be employed in the ALU. The following table giYes an example of how the two ALU ROM chips shown in Figures 142-143 can be constructed to implement the above described ALU functions .
(in this table each "1" represents a "low" state and each "O"
represents a "high" state):

-40~-ROM ~1 / 1000; 1/ 0000; 2/ ~000; 3/ 1000 4/ 100~; 5/ 0000; 6/ 0000; 7/ 1000 8/ 0000; 9/ 0000; 10/ 0000; 11/ 1000

12/ 0~0; 13/ 00~0; 14/ 0000; 15/ 1000 16/ 00~0; 17/ 1000; 18/ 1000; 19/ 10~0 2~/ 00~0; 21/ 1000; 22/ 1000; 23/ 1000 24/ 1000; 25/ 1000; 26/ 100~; 27/ 1~0 28/ 1000; 29/ 100~; 3~/ 10~0; 31/ 1000 32/ 1000; 33/ 0000; 34/ 00~0; 35/ 10~0 36/ 1000; 37/ 0000; 38/ 0000; 39/ 1~00 40/ 0000; 41/ 0000; 42/ 0000; 43/ 1000 44/ 0000; 45/ 0000; 46/ 00~0; 47/ 1~0~
48/ 0000; 49/ 1000; 50/ 10~0; 51/ 1000 52/ 0000; 53/ 1000; 54/ 1000; 55/ 1000 56/ 1000; 57/ 1000; 58/ 1000; 59/ 1000 60/ 1000; 61/ 1000; 62/ 10~0; 63/ 1000 64/ 1100; 65/ 1100; 66/ 1100; 67/ 1100 68/ 1100; 69/ 1100; 70/ 1100; 71/ 1100 72/ 0000; 73/ 0000; 74/ 0000; 75/ 1000 76/ 0000; 77/ ~000; 78/ 000~; 79/ 1000 80/ 0100; 81/ 0100; 82/ 0100; 83/ 1100 84/ 0100; 85/ 0100; 86/ 0100; 87/ 1100 88/ 0000; 89/ 1000; 90/ 10~0; 91/ ~100 92/ 1000; 93/ 0100; 94/ 0100; 95/ 1100 96/ 1100; 97/ 1100; 98/ 11~0; 99/ 1100 100/ 1100; 101/ 1100; 102/ 1100; 103/ 1100 104/ 00~0; 105/ 0000; 106/ 0000; 107/ 100 108/ 0000; 109/ 000~; 110/ 0000; 111/ 1000 112/ 0100; 113/ 0100;114/ 010~ 115/ 1100 116/ 0100; 117/ 0100;118/ 0100, 119/ 110~
120/ 0000; 121/ 1000;122/ 1000; 123/ 0100 124/ 1000; 125/ 0100;126/ 01~0~ 127/ 1100 128/ 0000; 129/ 0000;130/ 0000, 131/ 0000 132/ 0000; 133/ 0000;134/ 0000; 135/ 0000 136/ 0010; 137/ 1010;138/ 1010; 139/ 0110 140/ 1010; 141/ 0110;142/ 0110; 143/ 1110 144/ 0001; 145/ 1001;146/ 1001; 147/ 0101 148/ 1001; 149/ 0101;150/ 0101; 151/ 1101 152/ 0011; 153/ 1011;154/ 1011;155/ 0111 156/ 1011; 157/ 0111;158/ 0111; 159/ 1111 160/ 0000; 161/ 0000;162/ 0000; 163/ 0000 164/ 0000; 165/ 0000;166/ 0000; 167/ 0000 168/ 0010; 169/ 1010;170/ 1010;171/ 0110 172/ 1010; 173/ 0110;174/ 0110; 175/ 1110 176/ 0000; 177/ 0000;178/ 0000; 179/ 0000 180/ 0000; 181/ 0000;182/ 00~0;183/ 0000 184/ 0011; 185/ 1011;186/ 1011;187/ 0111 188/ 1011; 189/ 0111;190/ 0111;191/ 1111 192/ 0000; 193/ 0000;194/ 0000;195/ 0000 196/ 0000; 197/ 0000;198/ 0000;199/ ~000 200/ 1010; 201/ 0010;202/ 0110;203/ 1010 204/ 0110; 2~5/ 1010;206/ 1110;207/ 0110 208/ 1011; 209/ 0010;210/ 0111;211/ 1011 212/ 0111; 213/ 1011;214/ 1111; 215/ 0111 - 216/ 1001; 217/ 0001;218/ 0101;219/ 1~01 220/ 0101; 221/ 10~1;222/ 1101;223/ 0101 224/ 0000; 225/ 0~0~;226/ 0000;227/ 0000 228/ 0000; 229/ 0000;230/ 0000;231/ 0000 232/ 1011; 233/ 0011;234/ 0111;235/ 1~11 236/ 0111; 237/ 1011;238/ 1111;239/ 0111 240/ 0000; 241/ 000.0;242/ 0~00;243/ 0000 244/ 0000; 245/ 0000;246/ ~000;247/ 0000 248/ 1010; 249/ 0~10;250/ 0110;251/ 1010 ~52/ 0110;253/ 1010;254/ 1110;255/ 011 . . ~

;

10587~6 - ROM #2 / ~000; 1/ 0000; 2/ 000~; 3/ 0000 4/ 000~; 5/ 0~0~; 6/ 0000; 7/ 0000 8/ 0~00; 9/ 00~0; 10/ 0000; 11/ 0000 12/ 0000;13/ 0000; 14/ 0000; 15/ 0000 16/ 0000;17/ 000~; 18/ 0000; 19/ 0000 20/ 00~0;21/ 0000; 22/ 0000; 23/ ~000 24/ 0000;25/ 0000; 26/ ~000; 27/ 0000 28/ 0000;29/ 0000; 30/ 0000: 31/ 0000 32/ 000~;33/ 0000; 34/ 0000; 35/ 0000 36/ 0000;37/ 0000; 38/ 0000; 39/ 0000 40/ 0000;41; 0000; 42/ 0000; 43/ 0000 44/ 0000;45/ 0000; 46/ 0000; 47/ 0000 48/ 0000;49/ 0000; 50/ 0000; 51/ 0000 52/ 0000;53/ 0000; 54/ 0000; 55/ 0000 56/ 0000;57/ 0000; 58/ 00~0; 59/ 0000 60/ 0000;61/ 0000; 62/ 0000; 63/ 0000 64/ 00~0;65/ 0000; 66/ 0000; 67/ 0000 68/ 0000;69/ 0000; 70/ 0000; 71/ 0000 72/ 0000;73/ 0000; 74/ 0000; 75/ 0000 76/ 000~;77/ 0000; 78/ 0000; 79/ 0000 80/ 000~;81/ 0~0~; 82/ ~000; 83/ 0000 84/ 0000;85/ 0,00~; 86/ 0000; 87/ 0000 88/ 0000;89/ 0000; 90/ 0000; 91/ 00~0 92/ 0000;93/ 0000; 94/ 0000; 95/ 000~
96/ 0000;97/ 0000; 98/ 0000; 99/ 0000 100/ 0000;101/ 0000; 102/ 0000; 103/ 0000 1~4/ 0000;105/ 0000; 106/ 0000; 107/ 0000 108/ 0000;109/ 0000; 110/ 0000; 111/ 0000 112/ 0000;113/ 0000; 114/ 0000; 115/ 0000 116/ 0000;117/ 0000; 118/ 0000; 119/ 0000 120/ 0000;121/ 0000; 122/ 000~; 123/ 0000 124/ 0000;125/ 0000; 126/ 0000; 127/ 0000 128/ 1111;129/ 1101; 130/ 1011; 131/ 1~01 132/ 0111;133/ 000~; 134/ 0000; 135/ 0000 136/ 1101;137/ 1011; 138/ 1001; 139/ 0111 14~/ 1110;141/ ~000; 142/ 0000; 143/ 0000 144/ 1011;145/ 1001; 146/ 0111; 147/ 1110 148/ 110~;149/ 0000; 150/ 0000; 151/ 0000 152/ 1001;153/ 0111; 154/ 1110; 155/ 1100 156/ 1010;157/ 0000; 158/ 0000; 159/ 0000 160/ 0111;161/ 1110; 162/ 1100; 163/ 1010 164/ 1000;165/ 0000; 166/ 0000; 167/ 0000 168/ 0000;169/ 0000; 170/ 0000; 171/ 0000 172/ 0000;173/ 0000; 174/ 0000; 175/ 0000 176/ 0000;177/ ~00; 178/ 0000; 179/ 0000 180/ 0000;181/ 0000; 182/ 0000; 183/ 0000 184/ 0000;185/ 0000; 186/ 0000; 187~ 0000 188/ 0~00;189/_ 0000; 190/_ 0000; 191/ 0000 192/ 11~1;193/ 1011; 194/ 1001; 195/ 0111 196/ 1110;197/ 0000; 198/ 0000; 199/ 0000 200/ 1011;201/ 1001; 202/ 0111; 203/ 1110 . 204/ 1100;205/ 0000; 206/ 0000; 207/ 0000 208/ 1001;209/ 0111; 210/ 1110; 211/ 1100 212/ 1010;213/ 0000; 214/ 000~; 215/ 0000 -216/ 0111; 217/ 1110;218/ 1100; 219/ 1010 220/ 1000, 221/ 0000;222/ 00~0; 223/ 0000 224/ 111~, . 225/ 11~0;226/ 1010; 227/ 1000 228/ 0110; 229/ 0000;230/ 0000; 231/ 0000 232/ 0000; 233/ 0000;234/ 0000; 235/ 00~0 236/ 0000; 237/ 0~00;238/ ~00; 239/ 000 240/ 0000; 241/ 0000;242/ ~000; 243/ 000 244/ 0000; .245/ 0000;2~6/ 0000; 247/ 0~00 248/ 0~00, 249/ 0000;250/ 0000; 251/ 0000 ~52/ 0000, 253/ 000~;254/ 0000; 255/ 0000 " 1058766 ME~ORY UNIT
The calculator uses an all semiconductor memory system. Peripheral circuitry is bipolar and the memory con-sists of n-cha~nel MOS read only memory (ROM) and p-channel MOS read/write memory (RWM).
Addressing and physical layout of the memory module is done so that the number o~ words can be increased ~rom 3 in the basic machine to 7.5K in the largest machine. The smallest lncrement o~ memory that can be added is 512 words.
Provisions have been made to contain all add-on RWM within the memory module. Add-on RO~Z is external to the memory module, behind the display.
The basic machine contains 3K words o~ memory, organized into 2K x 16 ROM, 512 x 16 and 512 x 6 RWM. The 16 bit RWM words are divided into 109 user registers (4 words) and 76 words ior processor use. The 6 bit RW~ words are program steps. The largest machine contains 5R words o~
ROM and 2.5K words of RWM, o~ which 512 words are 16 bit.
Read~rite ~emory As shown in ~igures 146-150 memory is made up o~ 1024 g 1, dynamic, Read/write mèmory chips (Intel 1103). These devices are P-channel, hZO5 using silicon gate technology. To maintain the contents o~ memory, the device must be re~reshed every 2 ms. This is accomplished by per~orming a read cycle at a given address. On each chip are 32 re~esh ampli~iers so that each read cycle, 32 cells get re~reshed. The entire chip is then re~reshed by cycling through the lower 5 address bits and reading each distinct address. The re~resh period i3 20 ~s at l-ast ~very 2 ms.
Logic levels on all input lines to the RW~Z chips ~re lOS8766 0 to + 16v. This includ~s the 3 clock lines (chip select~
Y-enable or write, and precharge), 10 address lines, and i~put data. The output data, however, is a current of 600 ~a or more into lK ohms or less. This low level output is ~'wire-or able~' with other chips to build larger systems.
Read Only Memory As sho~n in Figure 146, 147, 151, and 152 ROM chips are 4096 bit, ~-channel MOS arranged 512 x 8. The devices are static and consume no power when not enabled. Data is retrieved from the ROMs by pulling the chip enable line from O to + 12v tturning the chip on), addressing the desired cells (0 or 4v levels) and selecting which output devlces are to be enabled (4v or 0v). The output le~els are suf- -ficient to drive one TTL gate directly, and can be "wire-or/ed" for large systems.
As further sho~n in Figures 153 and 154A-D, each ROM ~hip comprises six input bu~fers. These input buffers generate both the input and its complement. On the basis of the 64 possible combinations of the 6-inputs Io-I5, one of the 64 lines in the decoder is selected. The selected line enables one of the vertical lines in the 64 x 64 bit storage array.
For example, let Io - I5 ~ 0 and I~ - I8 be "don't cares".
This means line ~00 tocta-l) is selected The two 8 out of 32 select decoders must choose 16 lines from the 64 hori~ontal lines selected by the vertical line X00. (The 8 out of 32 select decoder is actually a 2 out of 8 decoder repeated 4 times in each of the sections A - B.) The o~utput ~rom four MOS FET's a, b, c, and d are 'r ire or/ed". MOS devices a', b', c', and dr are also con-nected similarly. r~ I6 and I7 ~ 0, horizontal lines lXX, .

2XX, 3XX, 5XX, 6XX, 7XX are grounded in eacll of the four sections A-B. This insures that MOS FET's b, c, d, b', c', and d' are non-conductive. This allows signals on lines OXX
and 4XX to pass into the output sections through transistors a and a'.
The output section contains the OUtp~lt buffer, 1 out of 2 decoder, and the output drivers s. The output butter provides a stage of gain and "wire or's" 4 lines from the storage array. The 1 our of 2 decoder clamps the gates of 2 of the 4 output drivers in each section A-B by enabling either line I8 or its complement (~). This disables 1 of 2 signals coming from the output buffer. The output drivers then can be tied together with line (e) for a 512 x 8 organi-zation.
Each of the above-listed constants and rou-tines and subroutines of basic instructions employed by the calculator is stored in these ROM chips. This is accomplished by parti-tioning the O to 16777 octal addresses of the memory map of Figure 4 into 5121oX 81o blocks which is the capacity of each 4096-bit ROM chip. These blocks are represented in the memory map of Figure 155. The next step is the inversion of the 8 bits (if the input was "1", it is now a "O") and com-plimenting of the address (i.e. once the octal addresses O - 16777 are partitioned into 512 x 8 blocks, only the last 3 octal digits are important)~ For this reason, address 7778 goes to 000,7768 goes to 001, ....... , and 000 goes to 7778.
The sixteen bits of each constant and basic instruc-tion are stored in the 5121o x 81o ROM chips by organizing the ROM chips into 64 x 64 bit matrices and computing the ~ 058766 row and column numbers of eacll bit of each matri~ by operating on each address and the particular bit (15 through 8, or 7 through 0) The coIumn number is computed by subtracting the last two digits o~ the address from 18 For example, the column number of address 000 ~ 18 ~ 8 = 100 ~ 641o - and the column number of address 777 - 18 ~ 778 ~ 1. The computation of the row number (referred to as IR in the flow-chart of Figure 156) can best be described by referring to the flowchart of Figure 156 and the associated table of ~igure 157. Once the row and column numbers are found it is a simple matter of storing in that location of the matri~
that particular bit (i.e., a "1" or a "0"). A "O" is stored at a designated location by forming a metal gate to complete a MOS FET device at that location, and a "1" is stored at a designated location by leaving off the metal gate so that a MOS ~ET device is not formed at that location.
~-Register .
As s~own in Figures 146, 147, and 158A-D included on the M-Register bcard is the 16 bit Address or M-Register, all chip enab e decoding and buifering, and address buffers for both RO~ and RWM. The register uses four, four bit, serial in and out, parallel in and out shift Registers. Upon receipt of a TT~ instruction from the microprocessor, serial data from the T-Bus is accepted into the ~-register. Nothing is done with this data until either a read or ~rite instruction is received, then one of two decoders are enabled. These chip Enable decoders uni~uely decode which block of 512 words, - either RON or R~, is being addressed~ If RO~t is being addressed, the signal is inverted and amplified to l12v. For R~3I the Chip Enable enables a gate, which allows a 16 ~olt clock -~14--` 1058766 signal to reach the enabled RWM chips. The clock wa~e ~orm is generated on the control card.
The dynamic characteristic of the RWM cllips, requires that all chips be enabled simultaneously during a refresh cycle, to refresh the entire read/write memory. The buffer circuits in the output of the Chip Enable decoders allow the-chip select clock to reach all of the R~M chips during re~resh but only those being accessed, during a read or write cycle.
Open collector nand gates with resistor pull-ups are used as bu~fers for the ROM address lines. Using the open collector gates, the address lines can be pulled above the re-quired 4~ lev~1. The nand gates àre enabled during a memory cycle so that th~ ROM address lines are inhibited at a 5v level. The R~M address lines must pull from Ov to + 16~.
~igh voltage, open collector, inverters with discrete transistor pull-ups are used as buf~ers for the 5 most significant bits.
- The 5 least significant address bits are bussed to the control card where they ~e used in part of the refresh circuitry.
Control ~ memory cycle consists of a read or write instruction from the processor accompanied by 12 clock pulses from the shi~t clock. As shown in Figures 146, 147, 159A-~ and 160, control uses these pulses and instructions to generate the cloc~s required by the RNM chips. A synchronous 4 bit counter (SN74193) is used to count cloc~ pulses and the 4 outputs are decoded by a 1 of 16 decoder (SN74154) to generate J and K
input to flip-~lops. The outputs from the flip-flops are then bu~fered to become the required clock signals (Precharge, Y-enable, chip select).
Re~reshing the read/write memory is also taken care of by the control card. An asta~ multivibrator with a repetition rate of 500 hæ. minimum generatcs a signal whicIl allows a re-fresh cycle to occur. A ~lip-flop ~enerates the actual signal (REF), but only if the astable multivibrator signal is high, there is no read or write cycle in progress and the processor signal, Z~, is high. ~ goes high betueen processor in-structions, thus it is known that nothin~ i6 going to be in-terrupted when REF is generated. REF is then buffered by an open collector inverter and given to the processor as ~R~ halts the machine and the refresh cycle begins.
The same counter used ~or a memory cycle, is used during refresh to again generate the necessary clocks (Pre-charge aud chip select). When the counter returns to state O
and REF is present~ a second counter is advanced one count.
This second counter provides the re~resh addresses which go to the RWbI only if REF is present. ~hen this counter returns to state 0, it causes REF and ~ to return to preset conditions and the machine continues normal operation.
A $urther function of the control card is to make the 1024X1 me~ory chips appear to the processor like 512 x 2 chips.
This is done by accessing the RWM t~ice during each memory cycle. Hence, half-way through each refresh or memory cycle a flip-ilop changes state to gsnerate one address bit. The ~-register thus provides only 9 address bits and the co~trol card 1 bit, independent o~ the M-register.
Other signals generated on the control card, direct the flow of data in the T-reglster - T-Register Dæta to and from the memory is temporarily stored in the T-register. As shown in Figures 146, 147, and 161A-D four 4-bit, serial in ~nd out, parallel in and out shift registers -~16-~058766 make up the actual T-registcr The registcrs h~ve a mode control (TMC) whicll when low, allows serial data flow and when higll, allows parallel data flow.
Serial data enters the T-register in the presence of a m instruction. Data is serially transmitted to the S-bus during a TTS instruction, and simultaneously recirculated into the T-register to prevent loss of data.
Parallel data is accepted from either ROM or RWM
during a read cycle. The ROM data is buffered by nand gates and the RWM by sense amplifiers followed by the same nane gates. Multiplexing the RWM means that only one-half the data bits are transmitted between RWM and the R-register during each half of the memory cycleO The first half of the read cycle, the odd bits are loaded into the T-register. To com-plete the transfer these bits must be shifted right one place and the odd bits again loaded from the RWM. This is done by allowing the odd bits to appear as data at the input of the even bitso When new data is clocked into the T-register during the second half of the read cycle, the even inputs are also clocked in, filling the T-register. This isn't done with ROM
since all ROM is transferred 16 bits parallelO
Data is written into memory in a manner similar to the way data is read from RWM. The bits are 16v levels, after buffering, and are written by the odd b~ts followed by the even bits. The nand gates between the T-register and the 16v buffers are gates from the control card to handle the write multiplexingO

-~17-INPUT-OU~PUT CONTROL UNIT
The input-output control unit allows the calcu-lator to communicate with the internal input, input-output, and output units and ~ith external peripheral devices. As shown in Figures 140A-C and 162A-D, the input-output control unit is contained on two printed circuit boards; the ~Control and System Clock~' board and the "I/O Register aDd Gate Interface" board. A third board, sho~n in Figure 163, is an I/O motherboard providing room for connectiDg four ex-ternal inter~ace cards to the calculator.
The internal input, input-output, and ouput units are distinguished ~rom peripheral devices by the fact that the I/O language set addresses the~ directly. HeDce each I/O instruction contains an iDternal peripheral address as part of its makeup. The ~ive internal directly-addressable iDpUt, input-output, and output units are the I/O register, the magDetic card reader, the output printer, the x-, y-, and z- register display, and the keyboard mode lights.
The external peripheral devices are i~directly addressable and are connected via cable to an iDter~ace card which is plugged iDto the I/O motherboard at the rear of the calculator. The term indirectly addressable i9 de-~ined here to mean the e~ternal peripheral devices are addressed by lines leading from the ~our most signl~icant bits in the I/O register, thereby re~uiring an address ~ord to be loaded into the directly addressable I/O register.
I/~ CONTROL AND SYSTEM CLOCK SECTION
.
- The fu~nction o~ the I/O Control and System Clock Section is to provide control to the I/O Register an~ Gate Inter~ace Section. This is accomplished by use of an I/O

,. , ~058766 instruction set stored in tlle main me~nory of the calculator.
The microprocessor causes instructions from the memory unit to be loaded into the T-Register and then to be transferred to the Q-Register. The microprocessor deter-mines the type of instruction and causes the proper execution of the instruction. If the instruction is an I/0 type, con-trol is transferred by the microprocessor to the I/0 Control and System Clock Section.
The microprocessor remains in a two state waiting loop while the I/0 Control section is active. Time in the wait loop is between .72 u seconds and 6.5 u seconds.
Bits 5 through 10 from the Q-Register are connected to the I/0 Control section and remain constant during an I/0 instruction execution time. Bits 5 through 8 repre-senting the I/0 instruction code are gated to the I/0 address flip flops and entered on each clock time while the I/0 is inactive. The four outputs of the address flip flops are connected to the address input of a 1 of 16 de-coder and represent the starting state address of the I/0 instruction to be executed. When the I/0 Control Section is enabled, the input gates passing bits 5 through 8 to the I/0 address flip flops are closed and the 1 of 16 de-coder enabled. This allows the starting state I/0 micro instructions to come from the 1 of 16 decoder. The next state address coming from the closed input gates will be the exit state (1111=17~) unless modified by reopening the gates to let the original starting state code through or by modifying the output of one or more of the input gates using a "wire or" connection coming from the 1 of 16 de-coder output. This address is sent to the I/0 address --~ 19--, .
,. ~ - .

lOS~766 flip flops illpUtS nnd cloclced in on tl~e leadin~ edgc of the first half clock cycle. The first half clock cycle turns off the 1 of 16 decoder alld the address changes. The second half clock cycle enables the 1 of 16 dccoder, allowing the next state micro instruction to appear (See Figure 164 for the timing described above.) This process continues until the exit state is encountered. On the exit state, the I/O Control is disabled and control is returned to the microprocessor.
The I/O instructions involving the transfer of data between the I/O and the CPU (OT, LI, MI), require 16 passes through the same state (1 pass for each of 16 bits). This is achieved by checking the output of a 16 bit down counter and then decrementing after each pass through the state.
If the counter indicates "O" has not been reached, it causes the starting state address to be reloaded into the address flip flops by opening the input gates. When 16 passes have been indicated by the counter, the input gates are not allowed to open; however, the next state (1111) is modified by the output of the 1 of 16 decoder through a "wire or"
connection on the 2cd bit to give state 1101. This address is input to the I/O address flip flops as in the preceeding paragraph.
The above-described operation of the I/O control section is also illustrated and further described in the flow chart of Figure 165.
Bit 9 is called a hold/clear bit. It allows a clear flag (CLF) to take place or not to take place after execution of the other I/O instructions. (STF excepted) Bit 10 is used in conjunction with the micro instructions -~20-, TR and XTR to give control to the I/O.
The I/O control and programmable clock mnemonics are given in the following table:

CC0 Clock Code Zero CCl " " One CC2 " " Two CC4 " " Four CC8 " " Eight CCT Control Clock to Tester CEM Call Extended Memory CLC Clear Control CLF Clear Flag DRC Data Register Clock EBT - Eight Bit Transfer EOW End of Word IIO Inhibit Internal OSC
INH Inhibit Clock IPS Inhibit Primary/Secondary ITS Input to S-Bus MCK Memory Clock poP Power On Pulse PTR P-Reg to R-Bus QFG Qualifier Flag Q5 " Five Q6 " Six Q7 " Seven Q8 " Eight Qg " Nine Qlo " Ten QRD " ROM Disable RCA ROM Clock Address 1058~66 I/O CONTROL BOARD MNEMONICS (Continued) RCF ROM Clock Flip Flop SCB Set Carry Bit SCK Shift Clock SCT " " to Tester Service Request Acknowledge STC Set Control STF Set Flag TCK Tester Clock TTO T-Bus to Output TTX T-Bus to A/B Reg.
XTO External OSC
XTR A/B Reg. to R-Bus NOTE:
( ) indicates negative true signal I/O REGISTER AND GATE INTERFACE SECTION
As shown in Figure 162, the directly addressable I/O Register (address Ol) is a 16 bit universal (Parallel in/out, Serial in/out) register that is connected to the calculator processor by the serial-in S-Bus and the serial-out T-Bus. Information is passed non-inverted from the A or B regis-ters bit serial to the I/O Register with the I/O instruction OTX 01. Sixteen lines connected to the parallel outputs of the I/O Register provide data out to the internal input, input-output, and output units and to the external output interfaces. (NOTE: each I/O unit or interface may place only 1 TTL
load on the output lines.) Parallel entry to the I/O Register is through 12 party l~nes con-nected to the 12 least significant parallel inputs. The input lines are negative true with all input ,. .

-~058766 interfaces tying to the line.s through open collcctors.
Care must be taken to insure thexe is no disturbance to the lines while an interface is inactive. Input informa-tion is passed inverted to the A or B Register Bit serial with the I/O instructions LIX 01 or MIX ~1. (The inversion puts positive true information into the A or B register.) Input information is entered into the I/0 Register in three ways:
a) Service Request.
Entry by the service request method is con-trolled by a service inhibit flip flop, When the service inhibit flip flop has been cleared with the I/0 instruction CLF 01, a service re-quest may be initiated by returning the SSI
(Service Strobe Input) party line to ground through an open collector on the.interface.
This signal causes the parallel inputs to be strobed into the I/0 Register and sends a re-quest for service (QNR) to the microprocessor.
The microprocessor prior to receiving a request for service would have been cycling through various instruction paths and checking for a service request after execution of each instruc-tion. Upon receipt of a request for service, the processor interrupts the sequence of instruc-tions it was doing and loads an address into the M-Register which contains the starting address of the service routine. At the same time a sig-nal, ~ (Service Request Acknowledge), turns off the service inhibit flip flop and also sets -~23-the single service flip flop which pcrmits only one service interrupt to the processor per ser-vice strobe input. The single service flip flop is reset when the service strobe is removed.
All lines from an interface using the service re-quest method for entering information are inhib-ited when the Service Inhibit flip flop is set.
b) Return of Channel Flag After Command ~.ras Given to an External Peripheral Device.
This method implies the calculator must control the peripheral That is to say the calculator transmits the indirect address and control en-able (CEO) from the "I/O Register and gate inter-face" section to the interface with the expecta-tion of information being rel-urned by the peri-- pheral through the interface to the I/O Register.
Because of this expectation, only limited instruc-tions may be performed by the calculator while waiting. The Service Request method must be inhibited during this wait so that iput informa-tion is not destroyed by another peripheral using Service Request.
When a controlled peripheral responds, its flag and data are processed at the interface. The signal CFI (Channel Flag In) causes the loading of parallel data from the interface into the I/0 register and clears the control enable flip flop so that the CEO signal is removed from the inter-face. The calculator can interrogate the Control Enable flip flop with the instructions SFS 01 -~2~-:;

or SFC 01 to dctermine when data has been loaded in.
c) Giving the I/O Instruction STF 01.
The instruction STF 01 as described in (a) sets the service inhibit flip flop inbibiting the service request mode of entry. The STF 01 instruction also causes a parallel load of the input lines into the I/O Register.
The I/O Register is used to transfer data and con-trol between the calculator and the directly addressable magnetic card reader (address 02). To record information on a card, the control word and data is transferred from the A Register to the I/O Register. The I/O instruction STC02 clocks this information via MLS into a latch located at the card reader. The strobe bit for the recorded data is output to the I/O Register from the B Register. The I/O instruction STF02 clocks the strobe latch located at the card reader via MCR. The I/O instruction STF01 loads status from the card reader into the I/O Register (see l-C).
This status is transferred to the A or B Register where it is processed.
To enter information from the magnetic card reader a control word is transferred from the A-Register to the card reader latch as above. When a strobe is encountered from the card, the card reader sends a signal, ~FL, to the I/O Register and gate interface section, which sets the magnetic card flag flip flop. The I/O instruction SFS02 is used to determine the state of the magnetic card flag flip flop. When the flip flop is set, data is loaded into the I/O Register with tbe I/O instruction STF01.

-~25-- lOS8766 The dircctly-addressa~le output printer (address 0~) requires 26 bits of parallel information from the calculator.
Sixteen bits come from the I/O Register and 10 bits come from a register at the printer. A 16 bit word with "don't cares" in the least 6 significant bits is transferred to the I/O Register with the I/O instruction OTX 01. A second 16 bit word is transferred to the I/O Register with the instruction OTX 04. Tlle 10 valid printer bits already in the I/O Register overflow into the 10 bit printer register. The significance of the address 04 in the OTX instruction is that it allows the micro instruction EOW (End of Word) to set the printer enable flip flop after the 16th bit has been transferred.
At the end of the printers response it returns a signal (PTF) to the printer enable flip flop clearing it. The printer enable flip flop can also be cleared with the I/O
instruction CLF 04. The state of the printer enable flip flop is checked with the I/O instructions SFC 0~ or SFS 04.
The directly-addressab~e output display (address 08) recieves information from the I/O Register. A 16 bit word is transferred to the I/O Register with the instruction OTX
08. The address 08 allows the display enable flip flop to be set with the micro-instruction EOW after the 16th bit has been transferred. The display enable flip flop sends a signal DEN to the display indicating information is ready in the I/O Register. The display enable flip flop is cleared with the I/O instruction CLF 08.
The directly-addressable keyboard indicator lights (address 16) are used to indicate the modc for various keys.
The lights are driven from a latch or series of latches which get information from the I/O Register. Information is transferred to tlle I/O Register with the I/O instruction OTX 16. After the 16th bit has been transferred, the micro-instruction EOW and address 16 send a signal KLS which strobes the information from the I/O ~egister into the keyboard lights latch.
The keyboard does not have an address. It transfers information to the CPU through the I/O Register using the Service Request method described in (a) above. The keyboard is disabled while the service inhibit flip flop is set except for the stop key which when depressed sends the signal STP
which is processed independent of the service inhibit flip flop.
All external peripheral interfaces are indirectly addressed from the four most significant bits in the I/O
Register. Thus to communicate with an external peripheral, an address (0000 excluded) must be loaded into the I/O.
Register. Data and status will be loaded at the same time i~ the peripheral is to act as a receiver. If the peripheral is to act as a transmitter, only the address and status need be loaded. Next, the I/O instruction STC 01 sets the Control Enable Out flip flop. This flip flop sends a signal CEO
to all external interface slots. The CEO signal and the decoded (from the 4 bit address) address allow the interface to command the peripheral. After the peripheral has responded, information given back to the interface by the peripheral is processed to the I/O Register in the manner described under (b), "Return of Channel Flag After Command was Given to an External Peripheral Device".
The I/O Register and gating control circuit mnemo-nics are given in the following table:

~.:..... . . ..

~058766 I/O REGISTER AND GATE BOARD

CEO Control Enable Out CFI Channel Flag In CLF Clear Flag CO0, 1,2,3 Code Out DEN Display Enable DI0, 1,2,3,4,5,6,7 Data In DO0, 1,2,3,4,5~6,7 Data Out DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word .
IOD I/O Data KLS Key Lights Strobe MCR Mag Card Reset MFL Mag Flag MLS Mag Latch Strobe PEN Printer Enable pOP Power On Pulse PTF Printer Flag Q0 Qualifier Bit 0 Ql " "
Q2 " " 2 Q3 " " 3 Q4 " " 4 QFG " Flag QNR " Not Request SIH Service Inhibit SI0, 1,2,3 Status In SO0, 1,2,3 Status Out SRA Service Request Acknowledge SSI Service Strobe In STC Set ControlSTP Stop STF -428- Set Flag ; . ~ . . , ~ - ~

~058766 -~ I/O R1~GIS'111,n AND G~rr~ 3o~l~D (C'o11lin~
T-~us T-Bus TTO T Bus to Ou~put NOTE:
t ) indicates negative true signal As shown in Figure 166, when addressing a peripheral device, bits loaded into the 4 most significant locations in the I/O register from the CPU constitute the peripheral address code. As part of the output party line system the address code is routed to all I/O interface slots. Each I/O inter-face card decodes the 4 line address code to a unique single line for use on that particular I/O card. The binary codes lO through 15 have been reserved ~or dedicated peripheral addresses which are used by dedicated keys (from the key-board) and dedicated I/O drivers, Binary codes l through 9 are for general use. Code "O" is a non-addressing code and is used in operations that do not involve addressing a specific peripheral. The following table summarizes the address code assignments:
ADDRESS CODE ASSIGNMENTS
ADD- 4-BIT ¦ ASSIGNED PERIPHE;RAL
RESS CODE
HIIHH , TYPElYRlTER
. _

13 }IIILH
12 IIIILL REYBOARD & REY13OARD-LIRE PERIPIIERALS
11 HLaH _ _ HLIIL ~ ~
9 IILLII GENERAL USE; ONE OF NINE SELECTABLE
8 IILLL ..
_ . ~
7 Lllall " _ ... -LIILII ..
_ 4 LIILL .
3 LLIIII ..
.
2 I.LIIL ..
1 LLLII . . _ . . ...
IISI.D ON IN'I`I~.IlllUl''r l/l) lN'I'EllI~ CI. (`Alll)S
B Ll.l,l. I~'lll~`N 'I'IIE l.`l'JI'III Ul''l' !lI,('o`,ll.S ENIIIILEI) -~29-- ~ ,; ~ . .

The general usa~e codes (1-9) are decoded outputs from a 4 line to 1 of 10 decoder (SN 7~2 for examplc). It is in-tended that the codes 1 through 9 be jumpcr selectable. This would allow the user to select a code for his system peripherals or allow him to use more than one of the same peripheral by selecting different address codes.
Since the I/0 register is used to communicate with the internal input, input-output, and output units as well as -peripheral devices, a given peripheral's address code will appear randomly in the I/0 register address field with there being no intention of expecting the peripheral to respond:
Therefore, a second piece of information is necessary for the I/0 interface card to form a unique signal which will indicate to the peripheral to respond. This second piece of informa-tion is control information and is described hereinafter.
The I/0 interface cards contain TTL compatible logic - for manipulating control and data from the calculator and/or the peripheral. All I/0 interface cards which are intended to be used with the calculator must provide storage either on the I/0 interface card or in the peripheral. Thus data being transferred from the calculator to the I/0 card must be stored at the instant the peripheral is requested to respond. Like-wise data coming from a peripheral must be stored until the calculator accepts it. This requirement is important and must be considered on all compatible interface cards.
The calculator can supply up to 100 ma. maximum at ~5 volts to each I/0 interface card. Power exceeding this abso-lute maximum must be supplied by the peripheral.
The following table lists the pin assignments for all I/0 lincs at the plug-in slots on the calculator back plane, lOS8766 as vicwcd from the rcar of the calculatol, lcLt to right.

EXT~I~N~L I/0 INTEI~EACI, PIN ASSIGN~NTS

1 ~ A
2 +5 B ~5 4 USED D ~ a 10/20 O~ 11 D0 5 - M DI 5 13 D0 7 r ~I 7

14 S0 0 R SI 0

15 S0 1 S SI 1

16 S0 2 T SI 2

17 S0 3 U SI 3

18 C0 0 V C0 1

19 C0 2 W C0 3

20 SSI ' X SIH

21 CE0 Y CFI

22 1 Z STP

Figure 167 lists all I/0 lines with brief definitions and specifications and Figure 163 shows the source and rela-tive relationship of the I/0 lines. The output address data lines (Co 0-3) transmit the address code along the party lines to all interface slots. These lines will go high and low ac-cording to information being shifted in or out of the I/0 Register. At anytime a peripheral is addressed tlle lines will -~31-; becomc steady 1 instruction time (8 llS) beLorc control il~forma-tion is passcd to the I/O interface card or boLore data or status is taken from the I/O interface card or before data or status is takcn from thc I/O interface card and will remain constant until the control information is removed. After the control information is removed, the state of the I/O lines become unpredictable until the next addressing takes place.
Address data coming to the 1/0 interface card is positive true and each interface may place 1 TTL load on each address line.
The output data lines (DO 0-7) output data from the A or B accumulator in 8 bit bytes from the 8 least significant locations in the I/O register to all interface card slots.
The logic state is positive true (Data = 1 = High). Each interface card may place 1 standard TTL load on each data line.
The output data status lines (SO 0-3) output status data from the A or B accumulator and are driven from the next four locations above the data out positions in the I/O register.

(DO positions = O thru 7; SO positions = 8 thru 11.) These lines are used for sending additional information to a peri-pheral. The logic state is positive true. One standard TTL
load may be placed on each output data status line. (Special - drivers, fast data transfer, and interrupt do not make use of SO 3.) The input data lines (DI 0-7) transmit input data in 8 bit bytes to the 8 least significant bit positions of the I/O
register (locations O thru 7) from the I/O interface card.
Each "Data In" line has a lK pull up resistor to +5 volts and under the party line system must be driven low for a logical 1 from open collector gates on eacll addressed I~O interface -~32-', ` ~ ~ ':

lOS8'7~;6 card. The logic state is negative true The input data status lines (SI 0-3) rcceive informa-tion from the I/0 interface cards and transmit it to loca-tions 8 through 11 in the I/0 register. Each line has a lK
pull us resistor to ~5 volts~ These lines are used to provide additional information to the calculator about the state of a peripheral. The logic state is negative true.
The negative true "Device Ready" output line (~F~) transmits a control signal, which when combined with an ad-dress code will initiate a peripheral response on the ad-dressed I/0 interface card. Device Ready is controlled by the I/0 interface driver and therefore may look different depending upon the driver. For example, when the calculator wishes to transmit data to the I/0 interface card or to initiate a peripheral response prior to receiving data from the peri-pheral, the calculator causes the "Device.Ready" output line to go low and stay low until the peripheral response is over and the calculator receives the signal "Device Request" (C~I) from the I/0 interface card~ The "Device Ready" flip-flop always receives a clear signal whenever the I/0 register com-pletes a parallel load.
The "Device Request" party line CFI when driven low from an open collector gate on the I/0 interface card will cause the loading to parallel input information into the 12 least significant locations of the I/0 register. The active state of the line is low (negative true)0 The peripheral flag, indicating to the I/0 interface card the peripheral has received data/control or is ready to input data, is gated through an open collector nand gate onto the Device Request (CFI) party line. The open collector gate -~33-is enabled by tlle I/O intcrface card's addrcss a~ld Dcvice Ready (C~O). The Devicc Request line is pulled up inside the calculator by a lK resistor to ~5 volts.
The Device Request (CFI) signal must stay low until Device Ready (~) has been cleared (goes high). At this time data transfer has terminated and peripheral's ~lag and control must be cleared in preparation for the ne~t passO
Since a parallel load in the I/O register causes the Device Ready flip-flop to receive a clear signal, when a Device Request (CFI) is entered, a parallel load takes place and afterward Device Ready (~EO is cleared. The calculator uses Device Request in its general mode of data transfer.
The Half Status output line (~) is a line that goes low when the STOP key on the calculator is depressed. It will stay low for the duration of the key depression. One standard TTL load may be placed on this line by each I/O
interface card.
The Prevent Interrupt output line (~F~), when low in-dicates to the I/O interface card that a request for service must not be given to the calculator. One standard TTL load may be placed on this line by each I/O interface card.
The Service Request (Lo) line (SSI), when driven low, causes the loading of parallel input information into the 12 least significant locations of the I/O register and causes a CPU interrupt for service. The peripheral's request for service is gated with the Prevent Interrupt (~ line onto the Service Request party line through an open collector nand gate~ A
lK pull-up resistor to +5 volts is connected to the line in-side the calculator.
The line 10/20 is used on the I/O inter~ace card to -93~-~' , .' ``" 1058766 differentiate between the present calcul~tor and other cal-culators, thereby permitting the use of compatible I/O intcr-~ace c~rds. It is grounded in the case of the present cal-culator and open in the case o~ others.
The general format for all data trans~er consists of 8 bit parallel bytes (this calculator, like the ~ewlett-Packard model 9100 calculator uses a 7 bit ~ield) Other data formats are handled by specially developet drivers, such as the RO~ plug-in module employed for driving the type-writer.
The state o~ a peripheral is generally ch~cked be~ore attempting an output. This is done by first inhibiting the interrupt system. The address o~ the I/O interface card is shi~ted into the I/O register. The decoded address code en-ables the open collector gates on the I/O inter~ace card. The status of the peripheral is passed to the Status In lines and loaded into the I/O register with an I/O instruction issued by the calculator. The I/O register information is trans-ferred to the A or B accumulator and processed. If the peri-pheral is ready, the output data uord consisting o~ the ad-dress code, output status (i~ necessary) and the eight bit data byte is formed in the A or B accumulator The output data word is transferred to the I/O register after which the Device Ready (~E~) flip-~lop is set. The I/O inter~ace card receives the data, address code and Device Ready and a peri-pheral response is inttiated. The calculator interrogates the state of the Device Ready ~lip-~lop to detèrmine ~hen the I/O
inter~ace card has received the informàtion and the peripheral response is done. The peripheral I/O inter~ace card signals the calculator it is done ~y transmitting th~ Device Request -~35- -105876~

(CIF) signal to the calculator. The output waveforms are shown in Figure 168.
Before inputing data from an I/0 interface card it is necessary to determine if the peripheral has responded and is ready to input data.
After a peripheral response has been initiated, as described previously, the calculator waits for the Device Request (CFI) which loads the data into the I/0 Register and clears the Device Ready (CE0). The calculator checks the state of Device Ready and when it goes false (CE0 = HIGH), the cal-culator knows data is present in the I/0 Register and proceeds to shift it into the A or B accumulators for processing. The input waveforms are shown in Figure 169.
When blocks of data are to be transferred between a peripheral and the calculator, the interrupt is turned off, and transfer rates as high as 100,000 bits/sec may be possible. Before either input or output of a block of data can start, it is necessary for the calculator to check the status of the peripheral to see if it is turned on and ready. Register will remain unchanged during the block transfer. A single I/0 instruction shi~ts the 8 bit byte of data from the 8 least significant locations in A
or B to the 8 data locations in the I/0 Register; gives Device Ready (CE0 goes low) 120 ns after the shift is completed; and shifts the 8 most significant bits in A or B to the 8 least significant locations in A or B in preparation for the next transfer. (Note the Address and status field in the I/0 Register are not disturbed in the shifting.) Dev~ce Ready stays true (low) until the peripheral has received the data and is ready for more.
The I/0 inter-, ... . .................. . .

face card then returns Device Request (CFI) to the calculator. The receiving of Device Request by the calculator causes loading of the parallel input party lines into the input status and input data locations of the I/0 Register, and clears the Device Ready signal (CE0 goes high). The logic sense of Device Ready is observed by the calculator and when it goes false (CE0 = High) the CPU proceeds to output the next eight bit byte of data.
If the output I/0 interface card is not returning information on the input lines all input lines will be high when the loading, described in the preceeding paragraph, takes place. Therefore, if at the beginning the code in the output status field is being used by the I/0 interface card and must remain something other than all high it will be necessary for the I/0 interface card to receive the output status from the calculator and return it back to the status inputs so that when Device Request occurs the status field does not get changed in the I/0 Register.
Input: After determining if the peripheral is ready to start transferring a block of data the calculator turns off the interrupt and shifts the ad-dress code into the I/0 Register. (The Address code remains unchanged during the block transfer.) The Device Ready is given (CE0 = Low) to the ; calculator when the 8 bit data byte is ready for input. The Device Request signal causes the input data and status to be loaded into the I/0 Register and causes Device Ready to go false (~ = High). The calculator by checking when Device Ready goes false knows the data has been loaded. A
single I/0 instruction shifts the 8 bit data byte from the I/0 Register into the 8 most significant locations ill the A or B accumulators (shifting the previous information in A or B 8 placcs to thc rigllt) and causes Device Ready to go true (C~0 = Low) 120 ns after the last bit l1aS been shifted into A or B. As before if output status is to be retained on the I/0 interface card lt must be returned to the I/0 Register upon each input data transfer.
Wave forms illustrating high speed operations resemble the wave forms for the calculator in Figures 8 and 9.
The interrupt system is controlled by the Service Inhibit flip-flop. An interrupting peripheral is allowed to request service for input from the processor anytime the Pre-vent Interrupt line is disabled (~IH = High). The calculator allows only those peripherals which use the calculator key-codes to interrupt, and these must be user controlled such that only one interrupt at a time is taking place. Data (keycodes) is loaded into the I/0 Register at the instant the Service Request is given by the I/O interface card (~SI = Low) if Prevent Interrupt is disabled (SIH = High) or if Prevent Interrupt having been enabled (~ = Low) goes high while Service Request is being givenO At the same time a qualifier is routed to the CPU indicating a request for service is active.
Recognizing the request for service the CPU branches to the service routine which enables Prevent Interrupt (~ ow) and loads the starting address for the software service routine into the M-Register. After servicing the interrupt entry the Prevent Interrupt is disabled (SIH = High) and the next inter-rupt a'lowed to take place~ The interrupt waveforms are shown in Figure 170.
The following table lists the general I/0 instruction set and the associated codes:

I/O INSTRUCTION SE:T

-Nl~ME lNSTRUCl`ION INSTnUCTION CODE
EXEClr~'ION
TIME 15 14 13 12 11 10 9 8 7 (; 5 4 3 2 1 _ ~_ ~ ~ ~
STF 9 ,us II II H Il - II L II H II II S~Ll~CT CD
CLF 9 ,us II II II H - H H II H Il Il .
SFC 9 ,us H H H It - H II/C II H H L
SFS 9 lls H II H H - H H/C II L H L
.
CLC 9 lls H H H H - H H/C H L H II
..
STC 9 ,us H H H H - H H/C H H L L
. ... ~
OT* . 15 ,us H H H H A/B H H/C L L H II
. . _ _ ., LI* 15 ,us H H N H A/B H H/C L H L H "

MI* 15 ,us H H H Il A/B H H/C L L L H "

The following describes the function of each I/0 instruction with the 5 allowable select codes.
STF <SC> Set the flag. STF is a 240 ns positive true pulse which accomplishes the following with the various select codes.
STF 00 Not used by the calculator.
STF ~1 a. Sets the Service Inhibit flip-flop to the true state (SIH = Low; interrupt not allowed).
b. Causes parallel input data and status to be loaded into the I/0 Register.
STF 02 Generates a 240 ns positive true MCR pulse for the magnetic card reader.
STF 04, ~8, 16 Not used by the calculator.
CLF <SC> Clear the flag. CLF is a 240 ns positive true pulse which accomplishes the following with the various select codes.
CLF o~ Not used by the calculator CLF Pl a. Clears the Service Inhibit flip-flop to the false state. (~h = High; interrupt allowed.) b. Loads address locations in I/0 Register with 0's. (~ = Low) c. Clears Device Ready flip-flop (CE0 = High).
CLF P2 Clears magnetic card reader flag flip-flop.
CLF p4 Clears Printer Enable flip-flop (PEN = Low).
CLF P8 Clears Display Enable flip-flop (DEN = High).
.

'.,' . - ~ ~ ~ -~058766 CLF 16 Generates a 240 ns positive true KLS pulse.
SFC <SC> H/C Skip if flag clear. SFC is a 240 ns positive true pulse which accomplishes the following with the various select codes. If C is given a 240 ns CLF pulse ~s given after SFC.
SFC ~0 Causes the next instruction to be skipped if the STOP~key has not been depressed.
SFC 01 Causes the next instruction to be skipped if Device Ready is true (CEO = Low).
SFC P2 Causes the next instruction to be skipped if the magnetlc card reader flag flip-flop is clear.
SFC 04 Causes the next instruction to be skipped if the printer enable flip-flop is clear. (~E~ = Low).
SFS <SC> H/C Skip is flag set. SFS is a 240 ns positive true pulse which accomplishes the following with the various codes. If C is given then a 240 ns CLF
Pulse is issued after SFS.
SFS p0 Causes the next instruction to be skipped if the STOP key is depressed.
SFS pl Causes the next instruction to be skipped if Device Ready is false (CEO = High).
SFS 02 Causes the next instruction to be skipped if the magnetic card reader flag flip-flop is set.

..... . .
,, ,."
. "", ~058766 SFS 04 Causes the next instruction to be skipped if the printer enable flip-flop is set (PEN = High).
CLC <SC> H/C Clear Control. CLC is a 240 ns negative true pulse and is not used by the calculator. If C
is given then a 240 ns positive true CLF pulse is given after CLC.
STC <SC> H/C Set the Control. STC is a 240 ns positive true pulse which accomplishes the following with the various select codes. If C is given a 240 ns CLF pulse is issued after STC.
STC 00 Not used by the calculator.
STC 01 Sets the Device Ready flip-flop (CEO = Low).
STC 02 Generates a 240 ns positive true MLS pulse for the magnetic card reader.
STC 04, 08, 16 Not used by the calculator.
OTX <SC> H/C Output A or B causes data bits from A or B to be shifted to the I/O Register and accomplishes the following with the various select codes. If C
is given, a 240 ns CLF pulse is given after OTX is executed.
OTX 00 The 8 least signlficant bits in the A or B register are shifted non-inverted to the 8 least significant locations in the I/O Register, and 120 ns after the 8th shift the Device Ready flip-flop is set = Low). The 8 most significant ' ~ ' ' 1()58766 bits are shifted right 8 places and the least 8 significant bits are recirculated to the 8 most significant locations in the A or B registers.
The 8 most significant bits in the I/O Register are untouched.
OTX 01 Sixteen bits from the A or B register are shifted non-inverted to the I/O Register. The data in A
or B recirculates.
OTX 02 Not used by the calculator.
OTX 04 Same as OTX 01 and in addition, 120 ns after the 16th bit has been shifted the printer enable flip-flop is set.
OTX 08 Same as OTX 01 and in addition, 120 ns after the 16th bit has been shifted the display enable flip-flop is set.
OTX 16 Same as OTX 01 and in addition, 120 ns after the 16th bit has been shifted the 240 ns KLS signal is generated.
LIX <SC> H/C Load into A or B. Loads data bits from the I/O
Register into the A or B Registers and accomplishes the following with the various select codes. If C is glven, a 240 ns CLF pulse is given after LIX
is executed.
LIX 00 The eight least significant bits in the I/O Register are shifted inverted to the eight most significant locations of A or B, and 120 ns after the 8th shift the Device Ready flip-flop is set (CE0 = Low). A
or B is shifted right eight places as the I/0 Register data comes in. The 8 mcst significant bits in the I/0 Register are untouched.
LIX 01 The 16 bits of the I/0 register are transferredinverted to the A or B register. Data in the I/0 Register is lost.
LIX p2, 04, 08, 16 Not used by the calculator.
MIX <SC> H/C Merge into A or B. Merges data from the I/0Register into A or B registers and accomplishes the following with various select codes. If C is given, a 240 ns CLF pulse is given after MIX is executed.
MIX P0 The eight least significant bits in the I/0 register are merged with the eight least signifi-cant bits of the A or B register and shifted to the 8 most significant locations of A or B; 120 ns after the merge takes place the Device Ready flip-flop is set (~ = Low). A or B shifts right 8 places as the data is merged and shifted to the most significant locations. The 8 most significant bits of the I/0 Register are untouched.
MIX 01 The 16 bits of the I/0 Register are merged with the 16 bits of the A or B register and contained in the A or B register.

lOS8766 MIX 02, ~4, ~8, 16 Not used by the calculator. Examples of various drivers which transfer data are given below:
Example 1: Typical Subroutine to Get Status of I/O Device.
Calling Sequence:
LDB Select Code JSM Stat Stat STF 1 Turn off the interrupt system.
OTB 1 Load I/O Register with select code.
STF 1 Load I/O Register with status of I/O device.
LIA 1 Load A Register with status information.
CLF 1 Turn on interrup.
RET Return.
Example 2: Typical Subroutine to Output an 8 bit character.
Calling Sequence:
OTA 1 Output 16 bits to the I/O Register.

SFS 1 Loop until I/O flag is set by the JMP *-1 output device.

20 Example 3: High speed output where the calculator is faster than output device.
Calling Sequence:
ST* I -(Number of 16 bit words to be output) +1 ST* J Address of first word in the array.
LDB SC Select Code OUT2 JSM STAT Get status of output device RAR 9 and position it.

.

1058'766 Example 4A: Typical subroutine to input an 8 bit character.
Calling sequence is:
LDB Select code JSM In ... Return is made with the data in the A Register.
IN STF 1 Turn off interrupt system OTB 1 Load I/O Register with the select code ~~ STC 1. C Pulse the flag & turn interrupt system on JSM STAT Get status off the input device RAR 9 and position it.
SAP *-2, C If device is busy then continue to loop SAR 7 else position data bits RET Return.
SAP OUT2 IF device is busy, continue to loop STF 1 Turn off interrupt system.
OTB 1 Output select code LDB 1 B+Counter for number of words to be output LDA J, I Load next data word SEC *+1, C E+0 OTA P Output 8 bits from A
SFS 1 Loop until device sets JMP *-1 flag.
SEC *-3, 5 If E=0 and E+J then loop to output last 8 bits ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished.
CLF 1 Turn on interrupt system RET Return ExamPle 3B: If the output device is faster than the calculator then fewer in-structions can be used.

.

OTA ~ Output first 8 bits OTA 0 Output second 8 bits.

Example 5A: High speed input where the calculator is faster than the input device.
Calling sequence:
ST* I -(Number of 16 bit words to be input) ~ 1 ST* J Address LDB SC Select code JSM In2 In 2 JSM STAT Get status of input device RAR 9 and position it.
SAP In2 If device is busy, continue to loop STF 1 Turn off interrupt system OTB 1 Output select code STC 1 Command device to read LDB I RtCounter for number of words to be input SEC *~1, C E~0 SFS 1 Loop until input JMP *-1 device sets flag LIA 0 Load 8 bits from I/O Register SEC *-3, S If E=0 and E l then loop to input last 8 bits STA J, I Save data word in array ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished.
CLF 1 Turn on interrupt system RET Return Example 5B: If the input device is faster than the calculator then the number of instructions can be reduced.

~OS8766 LIA 0 Input first 8 bits LIA 0 Input second 8 bits All output I/0 interface cards which are to be fully inter-changeable with both the present and other calculators must have storage either on the I/0 interface card or in the peripheral to which information is being transmitted. Figure 171 illustrates the logic used to interface an X-Y plotter which has storage on the I/0 interface card.
Blocks (A) and (B) are the storage latches which store information coming from the I/0 register. When the output of gate (C) goes high, data ~s latched; when low, the outputs of the latch track the inputs. Gates (D) decode the Address code (14 = 1110) and pass it positive true to gate (E).
Device Ready (~) is also passed positive true to gate (E). Gates (H) are open collector and pass status and Device Request (GFI) onto the input party lines. An example of a 9810A output would be: Output the address 14 which enables status gates (H) and see ~f the power is on. If on, output address, status, and data to gates (A), (B), and (D). The output of (C) is low allowing data and status to pass. Next give Device Ready (CE0 = Low) this enables flip-flop (G), clocks flip-flop (F) which causes (A) and (B) to latch, and sends control to the peripheral. The peripheral acknowledges receipt of control by returning FLAG (FLAG = H~gh) in a busy state this continues to keep (A) and (B) latched and clears control flip-flop (F). When , -, - . . .
. - . , . .

~058766 thc pcripheral is donc aCtillg, tllC FLAG is rcturned to thc not busy state (FL~G = Low) which clocks flip-flop (G) and causes output at (C) to go low enabling (A) and (B)o The output of (~) drives the CFI gate which has been enabled from (E) and CFI goes low. CFI is received by the calculator which responds by returning CE0 high. This causes the output of (E) to go low, clearing flip-flop (G) and returning CFI
high. This completes 1 output cycle.
All input I/0 interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/0 interface card or in the peripheral from which information is being received. Figure 172 illustrates the logic required on a general purpose interface card with storageO
Block (A) is used to store information coming from the peripheralO (B) stores status coming from the I/0 register which may be needed by the peripheralO The output tracks the input whenever the enable on the latch is low.
Block (C) decodes the address code into one of lO addresses which are jumper selectable. An example of a calculator input would be as follows. The ad~ ess code would be de-coded by (C). The calculator would load status through the open collector input status gates (D). If the peripheral is on and ready, the address code and output status (if necessary) would be sent to (B) and (C). The decoded address is passed, positive true, to gate (E). The enable at (B) is low so that status is passed to the peripheral. The Device Ready is given (~ = Low) and comes to (E) positive true. The output of (E) clocks flip-flop (F) through gate (H)u The output of (F) givcs control to the peripheral and also enables . ~ ...- ~ . :
. ~- . .

1058'766 (A) to receivc data. Thc periphcral respollds in a b~lsy state (FLAG = ~ligh). Whcn data is ready to ~e input the FLAG is driven lowO Data is latched when the FLAG goes low in (A). Also when FLAG goes low, (G), having been enabled by the output of (II), is clockcd driving (J) from its Q output. (I) is enabled by the output of (Il) and so ~ is driven low. Data is loaded into the I/O
register from open collector gates (I) and ~ driven high as a result of the calculator receiving CFI~ This clears flip-flop (G) and disables the input gates (I) completing an input cycleO
Figure 173 illustrates the logic required, on an I/O interface board, to input using the interrupt.
A power preset circuit, block (A), will be neces-sary on this card to prevent an interrupt when the peripheral power is turned off or on. This can usually be done by sensing the peripherals' +5 volts and presetting when the voltage drops below 3 to 4 volts.
The calculator must be in a display routine such that the Prevent Interrupt is false (~ = High) before an interrupt can take place. This enables the flip-flop (B) to be clocked from the peripheral FLAG. The clock inputs to (E) and (F) have been high enabling the storage latches prior to the receipt of FLAG. FLAG clocks (B) causing (E) and (F) to latch, enabling open collector gates (H) through gates (I) and (J), and drives gate (G) which sends Service Interrupt (~ = Low) to the calculator.
The calculator responds by loading the data into the I/O
register and returning Prevent Interrupt true (~r~ = Low).
This clears (B). Prevent Interrupt is rcturncd false a~ter the entry has been proccssod and the cyclc is complctc.

' . 1058766 KEYBOARD INPUT UNIT
The keyboard input unit is shown in Fi~ures 174A-D and 175. It includes a contactless keyboard of the type shown and described in U.S. Patent 3,668,697, issued June 6, 1972.
The contactless keyboard is made up of an array of printed circuit trans~ormers. Each transformer has its secondary and primary interlaced in a spiral coil as shown in Figures 176-177. The secondaries o~ all the coils are tied in series to ~orm the sense line. The primaries o~ the coils are arranged in separate pairs. Each coil is connected in series, with ~pposite polarity, to its pair as shown in Figure 178.
Every pair has a drive and sink line, which is being selected and driven by the scanner.
Centered above each coil is a metal disc at the end o~ the key shaft. When a key is depressed the disc pro~i-mates the coil. The disc acts like a shorted turn and re-duces the coupling of the coil, and unbalances the pair.
This unbalance is ampli~ied by the comparator, when it is greater than the on bias. The comparator triggers the one shot, which turns o~f the scanner and lowers the on bias.
The scanner remains at its present state, whlch corresponds to the dri~e and sink line o~ the key depressed. This state is the keycode of the key pressed. When the key is released a spring retracks the key and disc. When the un~ilance is less than the new bias, the comparator turns o~ and the scanner starts again ready ~or a new key. Tlié two bias levels give the key mechanical hysteresis ~hen two keys are depressed the ~irst one do~vn will -~51-~oss766 be entered, alld as long as a key is down no otlle~r key can ~e entercdO An exception is wllen tlle other kcy is its pair. In this case the two keys will cancel each other. Whcll the first key is released, the second one ~vill be entcred. When the first key is released, while more than one other key is down, the next key to be entered will be the next in the scan sequence, not necessarily the second key down.
For the keyboard to work each pair of primary coils must be balanced To balance a pair of coils the following rules should be used when laying out the printed circuit board:
1. Sense lines must run in pairs. The closer the better.
They should be thin traces.
2. The sense windings of a pair of coils can be anywhere on the sense line. For best results they should be close.
3O Drive lines should be in pairs when possible. Drive clamp and source lines should be grouped together well away from the sense lines. When a drive line crosses a sense line it should be at right anglesO
4. Conne~t to spiral so to add a turn (or part of a turn) not to subtract. Try to duplicate additional turns on a spiral pair. Connect to spiral at a right angle~ from a distance.
5. For a pair of spirals separated by some distance, run the common connection away from the sense line and in the drive grouping 6. Check each pair of spirals for errors in drive or sense polarity. This can cause either an incorrect code (least digit), or a constant full output. One method to check for proper polarity is to assign current direction for both drive and sense. Then at eacll spiral check for proper polarity. This is illustrated in Fi~ure 179.

,.''.~ ' " ' , 1~8766 MAGNETIC CARD READING AND RECORDING UNIT
The magnetic card reading and recording unit is shown in the block -~ diagram of Figure 180 and in the detailed schematic diagram of Figure 1~1.
The manner in which it interacts with the calculator and operates to record and load secure and unsecure programs and to separately record and load data is shown and described in the block diagram of Figure 182, the flow charts of Figures 60-61 and 63-65, and in the memory map of Figure 62.
Operation of the card reader is largely automatic. It is only necessary to specify the type of operation and the limlts desired. These commands are entered via the calculator keyboard. The calculator then determines the necessary commands required to cause the magnetic card reader to perform the desired operation.
Several modes of operation are possible. Programs can be recorded on magnetic cards and loaded back into the calculator. Similarly, program and data information can be recorded and loaded, or data alone. Very long programs or blocks of data can be stored on several cards. The information is loaded back into the calculator by inserting the cards into the reader in the same sequence as they were recorded. The proper linking of the information stored on the cards is automatically performed by the calculator.
Information is stored on the magnetic card in 3 bit bytes. Three tracks record the information and a fourth track provides a timing mark. Two bytes form six bit words in the calculator. The card reader automatically begins and terminates the record~ng, irrespective of the length of card used.
Different card lengths can be mixed together without affecting ~'S~S~--tlle OpCl'atiOII oE tlle rOa(lCr, Ca.l~ds lllay l)C ill1:Cl'Cil;l.l~,CCI from one calculator to anotller.
No mechanic;ll s~vitcllcs are uscd in tl~o card readcr, The only movin~ psrt is tllc card drive motor alld capstanO
The mecllanical assembly and clectrol ics assembly are modular and can be replaced as separate and independent Ullits in tLle calculator, 10587~6 OUTPUT DISPLAY UNIT
As shown in Figures 18~ and 184A-B, the output display unit includes three fifteen-character rows of seven-segment ligllt-emitting diode arrays. Each array requires an anode driver ~or each of its seven segmen~s and one for the decimal point.
The cathodes are common to all the diodés in one character~
Respective anodes for the characters o~ a register are tied together to one driver. A series PNP transistor enables one o~ three sets of eight anode drivers each. The cathodes o~ a column of three characters are tied together to one of ~i~teen cathode drivers.
The data requ~red to operate the display is as follows:
1. Four bits to determine the column to be enabled.
2. O~e oi three bits to determine the register.
3. Eight bits to determine the diodes of a character to be lighted.
4. A line to enable the display when the data is present.
The duty cycle is less than 1/45 requiring pulses o~
more current than a character c~uld stand continuously. A
retrig~erable one shot is ~ired at e~ery display enable pulse and will disable the column drivers a~ter 1/2 ms. i~ the machine han~s up.

OUTPUT PRI~TE~ UNIT
Several methods have been described for producing printed characters by thermal means (see particularly UOS.
Patent 3,161,457 issued to H. Schroeder et al) but they typically employ a rectangular matrix of resistors to form an entire character at once. Commercial versions of this sort o~ printer are marketed by National Cash Register and Texas Instruments, As described in Schroeder's patent, a matrix five elements wide and seven elements high is typically em-ployed.
The output printer unit employed in this calculator isconqtructed as qhown in Figures 185, 186, 187A-B, 188, 189A-D, and 191A-B. It includes a row or print elements distributed linearly acro3s a printing head, as shown in Figure 188, to print a 16-character line. Each print element is an electrical resistor, of a size and shape intended to produce a dot on thermally-sensitive paper moved at right angles to the line of print element~. Dots are formed in the conventional manner by pulsing the resistor element with a pulse of electrical ~urrent, which raises its temperatur by joule heating.
Each o~ the sixteen characters o~ each line is ~ormed in a 5 ~ 7 dot matrix. For ex~mple, as illustrated in Fi~ure 192 the letter A is produced by printing the darkened dots in the top row and then stepping down to the ne~t row, etc.
Each line of print contains sixteen 5 x 7 matrices.
The matrices are made o~ seven rows o~ 80 dots spaced in five dot groups to produce sixteen characters. The printer pro-.
duces each line`of print by printing the top row of all six-teen characters and then stepping down to print row 2 until all seven ro~s are printed. Three blank steps are then added ,. .. .
: ., , ~ ,, to produce thc sp~cc bctwcen lines.
Eacll of thc seven rows oE printing contains 80 dots (5 for each of tlle sixteell characters) wllicll may or may not be printedO This requires that eighty information bits be sup-plied for each row printed. To accomplisll this, each row is split into four groups of twenty dots (four characters).
(Since the I/0 Register of the calculator is only sixteen bits long an extra ten bit shift register is contained in the printer hardware.) Each group of 20 bits is transmitted to the printer along with the group number by the I/0 Register and is printed when the printer enable signal is given.
The printer then prints that group of dots and returns a printer flag signal to the calculator. The next group of in-formation is then supplied until all 28 groups have been printed. The three step commands are then given to provide the space between linesO
The printer requires the following information to print any group of dots:
(1) Dots to be printed, (2) Group number, and (3) Printer enable.
As shown and described in the flow chart of Figure 193, this information is transmitted to the printer through the cal-culator I/0 register. Since the total number of information bits needed is greater than the I/0 registers length, two 16 bit words are transmitted to the printerO The first 16 bit word contains the dot patterns for characters 1 and 2 as shown in the following table:

: ;
-~57-1058~66 CON'l'hN~' OF 1/0 R~GlSTl3R AFTJi:R I~ ST I~DING
Cll~ractcr 2 Char~cter 1 ¦ L l~ t¦Dot¦ I L ¦Dot¦ ~ ¦ 0 ¦ 0 ¦ 0 ¦ 0 ¦ 0 C03 C02 COl CO~ S03 S02 SOl S00 D07 D06 D05 D04 D03 DOZ DOl DO~
- 0 - Don't Care Character one is contained in bits S02-SOO and D07, D06 with the left dot in bit S02 and the right dot in DOG. Character 2 is contained in bit C03-COO and S03 with the left dot in C03 and the right dot in S03. When the I/O Register is loaded with the second 16 bit word these bits will appear in the internal 10 bit shift register. The second 16 bit word contains the dot pattern for characters 3 and 4 and the group number as shown in the following table:
I/O REGISTER AFTER SECOND LOADING

Character 4 Character 3 Group ¦ L H~ R H L H¦ l l ¦R H¦ I l ¦ ¦ O ¦ 1 Dotl l l ¦Dot Dot¦ l l ¦Dot¦ 0 ¦ 0 ¦ 0 ¦ 0 ¦ 1 ¦ O

C03 C02 COl C00 S03 S02 SOl S00 D07 D06 D05 D04 D03 D02 DOl D00 0 - Don't Care Character 3 is contained in bits S02-SOO and D07, D06 with the left dot in S02 and the right dot in D06. Character 4 is contained in bits C03-COO and S03 with the left dot in C03 and the right do* in S03. The group number is contained in bits DOO and D02, Groups are numbered as follows:
GROUP PRINTED CHARACTERSDOl DOO
From Left to Right l 1, 2, 3, 4 o O
2 5, 6, 7, 8 0 3 9, 10, 11, 12 1 0 4 13, 14, 15, 16 When group 4 is detected the printer automatically steps to the next line. The time inter~al between printer enable and the return of printer flag is extendcd to allow the system 30to physically move~

.: , ; , , ,: .

The printin~ sp~d is ~iven iD the ~ollowin~ t~ble:
Group 18 ms Group 28 ms Group 38 ms Group 418 ms Row 1 42 ms Row 2 42 ms Row 3 42 ms Row 4 42 ms Row 5 42 ms Row 6 42 ms Row 7 42 ms Space 18 ms Space 18 ms Space 18 ms Total Time to Pri~t 1 line 348 ms Lines per second2.87 ms As shown in Figures 185-186, paper is loaded into the output printer unit by li~ting the wire bucket cover 220 and placing a roll o~ paper 222 with the ~ree end into the paper bucket formed by the front and rear buc~et halves, 224 and 226 respectively. The only care needed by the operator is to be sure that the paper uprolls ~orward ~rom the bottom. The wire bucket cover per~orms a dual ~unction o~ keeping the ~ree end of the paper in the bucket wbile loading and after the paper is loaded prevents the ~ree end ~rom reloading itself through the mechanism.

Thc wei~l~t ol tlle p~l~c~ c11 Stl'CtCIlCS tllC xubbcr s 2Z8 ~J1cl tllc Jo]l Or ]~ cl l~oll.c; folw.~ il it rcsts agail1st thc pap(l ~;uidc 230. The p;lpCl' 1'0115 fOrW.ll'd dlle to the "dow~ il]" slopc oJ thc bc]t from thc top Or tl1e rear idlel pullcy 232 1;o 1he botlom oL the papcr gllidc.
With tlle roll ol papcr in thc position dcsclibcd above the belts moving forward, thc free cnd of tlle paper i~ con-straincd by tl~e belts, paper guidc and roll to move below the papel guide and betweel1 it and thc bclts.
The belts are drivell by tlle drivc pullcy 234 wllich is in turn drivcn by a gcnr set Lront thc p~atell 236. The platen is driven by the motor 238 via a belt and gear set.
The diameter and speed oi the platen is such that its sur-~ace speed is approximately 5% faster than 1:hnt ~F 1-h~ t..
to insurc that tlle paper is always ullder tension after loading is completed. The drive and rear idler pulleys are crowned so that the belts will bc sel~-centering. The front idler pulley 270 is flat and serves to Iceep the lower portion of the belt out o~ the bucket area.
The print head 242 is pressed against the paper and platen by means o~ a spring, hence it is necessary to remove the print head from the platen while loading paper. This is accomplished hy the head lifter and paper de~lector 244 such that when it is rotated on its axis it cams the print head of~ the platen and positions a small plate in the path o~ the paper which guides the paper up and between the platen and print head.
The paper is guided througll tlle mechanism while loading and while the printer is working by edge guiding the paper. Ordinarily paper docs no* lend itself well to edge guiding due to its very 10VJ compressive strength. To over-come this the paper is bent around the convex bottom sur-face of the paper guide and the belt, which is under tension is very near thc edge thereby preventing the paper from buckling. The relationship of the paper, papcr guide and belts can be seen by looking at Section AA o~ Figure 186.
When se]ccting materials for the various parts o~
the loading mechanism it is important to be sure that the coef~icients o~ friction between the various parts are compatible. The C.F. between the paper and paper guide should be low relative to the C.F between the paper and belts in order that thc belts can drive the paper throu~ll the mechanisn~ Similarly, the C.F between the paper and platen should be higll relative to the C F. between print head and paper in order that the paper can be driven through while printing In addition, the drag introduccd by the belt and paper guide due to the paper moving faster than~the belt while printing must not be so great as to tear the paper or impose an impossible load on the motor.

-~60-'; `

Thc rigllt hnlf of top pnnel 90 of thc calculator housing is hinged at the back and provided with a handle 246 at the front so that it may readily be raised by the user and stopped at an obliquc upright pOSitiOll to expose and facili-tate replenishment of the supply of thermal-sensitive paper for the output printer unit and also to serve as a music stand for holding operating or program-running instructions or any other material the user desired. A transparent plastic retainer is mounted on the underside of the hinged right half of the top panel 90 to hold such materialO

-4Gl-POWER SUPPLY
The power supply system employed in the calculator is constructed as shown in Figures 194-196 and 197A-B. As shown in Figure 194, a centertapped transformer secondary is connected to terminals 2-3, 2-1, 2-2, and 2-4, The AC voltage from the transformer is rectified by diodes CRl and CR2 and filtered by capacitor Cl. The output o~ this rectifier/filter circuit is nominally 18 volts DC at 2.7 amps with a 2 volt peak to peak ripple.
Ql and Q2 serve as a s~itch to connect the five volt output bus to the 18 volt unregul~ted supply through inductors Ll and ~2. CR3 serves to clamp the input of Ll to ground when Qi and Q2 are switched o~. Current flow in Ll and L2 are substantially constant and equal to the load current.
Loss in high current transistor Q2 is mini~ized be-cause Q2 can be completely saturated. Loss in driver tran-sistor Ql is min~mized becanse Ql can also be saturated. Re-sistor R~ limits the maximum drive current to Q2. Losses i~
R7 can be minimized by proper positioning o~ the tap on Ll consistent with transistor parameters and circuit require-ments, ICl is a linear difierential ampli~ier integrated circuit to drive Ql and Q2. Any di~erential ampli~ier with su~icient voltage capability and bandwidth will work. Since the ampli~ier employed is linear, R7 and R4 have been included in the circuit to provide su~icient hysteresis ~or reliable s~itching. This hysteresis stabilizes the switching frequency and thus stabilizes the switching losses.
~ Bec~use hysteresis has been added to the circuit, a signi~icant ripple signal (at the switching ~requency~ must ,, ,;
:

be present on tho feedb~ck sign~l to the ~mplifier. This need for a ripple slgnal limits the amount of capacity that can appear betweell the output of Ll and ~round. L2 ser~es to isolate this point from the rest of the system. The amount of capacity that can appear between the output of L2 and ~round is essentially unlimited and si nificantly reduces power supply ripple, and greatly improves response to load transients.
The second ~inding of L2 is a path ior the ~eedback from the remote sensing. The required ripple signal is added to the feedback signal by transformer action in L2. Another possible configuration is shown in Figure 198.
The power supply also includes an overvoltage crowbar circuit (Qr, CR4, and R9) and a short circuit shut-down circuit (using Q5). In the event that the +5 volt bus is grounded, or the crowbar is triggered, Q5 saturates and locks ICl off.
The resistor R8 makes a current generator o~ ICl. Re-sistors R5 and R6 discharge the bases of Ql and Q2 respecti~ely.
IC2 and its associ~ted components generate a "power on pulse"
to initialize the instrument. ICl is re~erenced and powered ~rom an external l12 volt supply. Powering the IC from ~12 rather than the unregulated ~18 reduces power dissipation in ICl.
The +24 volt supp}y o~ Figure 196 is referenced by the +16 volt supply with the ampli~ier common returning to +12 volts to minimize power loss and voltage stress in ICl of Figure 196. Thè tl2 volt supply o~ Figure 197A references the -12, ~5, and +16 supplies directly. The +12 amplifier ICl of Figure 197A may be biased either from the unregulated supply :

105876~;

for thc +12 volt s~ ply or Lrom tllc operating -~lG volt supply.
Diodes CR5 and CR~ dctermille the appropriate source. This provides a grcater power supply margin for the +12 volt supply.
Similarly the ~16 volt amplifier is biased from the +20 to give that supply greater margill.
All supplies except the +20 volt supply are current limited. The +24 volt supply is current limited at a value greater than the rating of its series fuse. If a short circuit occurs in the +24 volt supply, it will current limit until the fuse opens, The average current from this supply is 1.1 amps with transients to 2 ampsO The current limit is set to 2.5 amps. There is not sufficient thermal capacity available to allow Ql of Figure 196 to carry sustained short circuit current so the fuse has been included to protect the various power supply components. All supplies except the +20 volt supply are crowbar protected against over-voltage.

-~6~-TYPEWRITER INT~RFACE
This interface couples the Facit-Odllner model 3841 output typewriter to the calculator.
The unit mounts directly on the back of the typewriter.
Communications with the calculator are made through about fi~e feet o~ cable which is terminated by the I/O plug containing a board for buffering and some logic.
Referring to Figures l99A-B and 200A-c, charactersfrom the calculator appear on the data lines as ASCII codes. These codes are recoded by a ROM into the si~ bit Facit*typewriter code for the 46 type bars, and one bit for upper case shift.
Functions such as space, tab, line feed, etc. are recoded for easy recognition in the interface since each function must be driven by a separate line. A data latch after the ROM
holds codes for processing. If new data arri~es during this processing, the two codes are compared to determine if they both drive the same type bar and if they are both numbers.
Non-repeating numbers can be typed at 14.5 characters per ;second, otherwise typing speed is 12 characters per second (reduce these speeds 17~ for 50HZ operation). Codes in the iatch are gated to the program solenoids or the function solenoids by the control logic.
To understand the coding, notice that two blocks of codes on the Facit typewriter code map are empty. If all function codes are put in these blocks, they can be identified by control logic by testing for (~-4). Each function code puts a 1 on one of five lines and this line opens the correct solenoid gate.~Bit 8 is used to discriminate between two sets of function gates. In the case of a program solenoid code, bit 8 identifies numerals.
* trade mark The control clock is provided by a sync. pulse which is generated in the typewriter by a vaned wheel attached to the end of the main drive shaft. The vanes interrupt a light beam. When a type cycle is initiated, a modulo eight counter counts sync. pulses and the count is decoded by a 1 or 8 decoder. At each of the eight states, combinational logic can enable solenoid gates, set or clear flag flip-flops or change the counter to state zero, or state 6, or inhibit the counter.

.

Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A programmable calculator comprising: keyboard input means for entering information, including programs and control commands, into the calculator; memory means for storing information, including programs, that has been entered into the calculator; processing means, coupled to said keyboard input means and memory means, for processing information stored in the memory means to perform selected functions; magnetic reading and recording means for selectively loading a program stored on an external magnetic record member in the memory means and recording a program stored in the memory means onto an external magnetic record member; and output means, coupled to the processing means, for selectively providing an indication of the results of information processed by the processing means and a printed listing of a program stored in the memory means; the keyboard input means including program recording control means for designating a program stored in the memory means as being a secure program when that program is recorded onto an external magnetic record member; the processing means including logic means for recognizing a program loaded into the memory means from an external magnetic record member as being a secure program and for subsequently inhibiting the listing and re-recording of that secure program.

2. A programmable calculator as in claim 1 wherein the program recording control means includes a control key and a record key and the processing means is responsive to sequential actuation of the control key and record key for causing the magnetic reading and recording means to record a program stored in the memory means onto an external magnetic record member and to further record information onto the external magnetic record member to indicate the secure status of the program recorded thereon.

3. A programmable calculator as in claim 2 wherein the memory means stores a security word and the logic means is operative for setting the security word to a predetermined state at the time that a secure program stored on an external magnetic record member is loaded into the memory means and is further operative for interrogating the security word whenever the calculator is commanded to list or to record on an external magnetic record member a program stored in the memory means.