CA1058760A - Programmable calculator with definable keys - Google Patents

Abstract

SUBSTITUTE
REMPLACEMENT
SECTION is not Present Cette Section est Absente

Description

- ~,os~760 Backgr _nd of the Invention This invention relates generally to calculators and improvements therein and more particularly to programmable calculators that may be controlled both manually from the keyboard input unit and automatically by a stored program loaded into the calculator from the keyboard input unit or an external record member.
Conventional programmable calculators generally have less capability and flexibility than is required to meet the needs of many users. For example, they typically cannot be readily expanded and adapted by the user to separately in-r crease the amount o~ program and data storage memory or to perform special keyboard functions oriented toward the en-vironment of the user. They also typically cannot perform indirectly addressed numeric data register transfers and arithmetic without utilizing a~ailable working registers for addresses rather than data. Th~s seriously limits their ability to efficiently perform complex operations such as file manipulations or matrix arithmetic. Moreover, they ~o typically have a very limited capability for performing _z_ ~

lOS87~(~

direct arithmetic between working and storage memory re-gisters and little or no capability for performing indirect arithmetic between working and storage memory registers.
In some conventional programmable calculators a pro-gram stored within the calculator can be recorded onto an external magnetic record member and can later be reloaded back into the calculator from the magnetic record member.
However, data and programs stored within these calculators typically cannot be separately recorded onto an external magnetic record member and later separately reloaded back into the calculator therefrom. Moreover, these calculators have no provision for making a program secure when it is recorded onto an external magnetic record member Any user may therefore re-record the program or obtain an indication of the individual program steps once the program is reloaded into the calculator.
Conventional programmable calculators with self-contained output printer units typically have a very limited alpha capability of only a few selected characters confined to certain columns of the printer. They are therefore typi-cally unable to print out both a numeric and a distinct mnemonic representation of every program step of every pro-gram stored within the calculator. Furthermore, they are typically unable to print out labels for inputs to and out-puts from the calculator or messages informing the user how to run programs with which he may be unfamiliar. Such features would be very helpful to the user both in editing programs and in simplifying their use.
In some conventional programmable calculators a pro-gram stored within the calculator may be edited by single stepping forward through the program while viewing an output l~S876~
display representing the last-encountered program step and its associated address and, in one case, also the presently-encountered program step and its associated address. How-ever, these calculators typically cannot single step back-ward through the program or display the next program step to be encountered and its associated address. Moreover, they typically have no provision for inserting program steps into the program without reloading portions of the program and no provision for finding every occurrence of any de-signated program step. Such features would also be veryhelpful to the user in editing programs.
Conventional computer systems have or may be pro-grammed to have much more capability than conventional pro-grammable calculators. However, they are larger, more ex-pensive~ and less efficient in calculating elementary mathematical functions than conventional programmable cal-culators. Moreover, a skilled programmer is typically required to utilize them. Due to these factors, conventional computer systems are best suited for handling large amounts of data or making highly iterative or very complex mathema-tical calculations.

Summary of the Invention An object of an aspect of this invention is to provide an improved programmable calculator that has more capability and flexibility than conventional programmable calculators and that is smaller, less expensive, more efficient in cal-culating elementary mathematical functions, and easier to utilize than conventional computer systems.
An object of an aspect of this invention is to provide a programmable calculator in which the amount of program 105876~) and data storage memory available to the user may be sepa-rately expanded and in which additional program and data storage memory made available to the user is automatically accommodated by the calculator and the user informed when he has exceeded the capacity of either the program or data storage memory.
An object of an aspect of this invention is to provide a programmable calculator in which the functions performed by the calculator may be readily expanded by the user and oriented toward the environment of the user and in which the added functions are automatically accommodated by the cal-culator.
An object of an aspect of this invention is to provide a programmable calculator in which the user may define key-board functions to be performed by the calculator and may protect them from subsequently being inadvertently altered or destroyed.
An object of an aspect of this invention is to provide a programmable calculator capable of employing extensive in-direct addressing to permit efficient manipulation of filesand matrix operations.
An object of an aspect of this invention is to provide a programmable calculator in which the user may employ either absolute or symbolic addressing and in which program jumps or subroutine calls may be made to absolute or symbolic ad-dresses.
An object of an aspect of this invention is to provide a programmable calculator capable of performing both direct and indirect storage, recall, and exchange between working and storage memory registers.

1C~58760 An object of an aspect of this invention is to provide a programmable calculator capable of performing both direct and indirect arithmetic bidirectionally between working and storage memory registers.
An object of an aspect of this invention is to provide a programmable calculator capable of performing serial binary arithmetic, parallel-by-digit binary-coded-decimal arithmetic, and logic operations.
An object of an aspect of this invention is to provide a programmable calculator in which either programs or data stored within the calculator may be separately recorded on an external magnetic record member and, subsequently, sepa-rately reloaded back into the calculator therefrom.
An object of an aspect of this invention is to provide a programmable calculator in which the user may designate any progra~ stored within the calculator as being secure when it is recorded onto an external magnetic record member for subsequent re-entry into the calculator and in which the user is prevented from re-recording any secure program or obtaining any lndication of its individual program steps once it is reloaded into the calculator An object of an aspect of this invention is to provide a programmable calculator capable of printing out every alphabetic and numeric character and many other symbols in-dividually and in messages.
An object of an aspect of this invention is to provide a programmable calculator capable of printing out both a numeric and a mnemonic representation of each keyboard entry in a key-log listing.
An object of an aspect of this invention is to provide a -10587~iC) programmable calculator capable of printing out a numeric representation of each numeric keyboard entry and calculated numeric result and a mark distinguishing each numeric key-board entry from each calculated numeric result.
An object of an aspect of this invention is to provide a programmable calculator capable of printing out both a numeric and mnemonic representation of each step in a program stored within the calculator and a numeric indication of the address of each program step in a program listing.
An object of an aspect of this invention is to provide a programmable calculator capable of editing programs stored within the calculator more efficiently than conventional programmable calculators.
An object of an aspect of this invention is to provide a programmable calculator in which the user may single step either forward or backward through an internally stored program in a program entering mode to check the program and may single step forward through the program in a program-controlled operating mode to check the program execution.
An object of an aspect of this invention is to provide a programmable calculator in which the last program step en-countered, the program step presently encountered, and the next program step to be encountered, while single stepping either forward or backward through a program stored within the calculator, may be displayed.
An object of an aspect of this invention is to provide a programmable calculator in which the user may insert program steps and automatically locate every occurrence of a de-signated program step in a program stored within the calculator.

lOS87~;0 Other and incidental objects of this invention will become apparent from a reading of this specification and an inspection of the accompanying drawings.
In accordance with one aspect of this invention there is provided an electronic calculator comprising: key-board input means including a plurality of keys for entering information into the calculator; memory means for storing information that has been entered into the calculator;
processing means, coupled to the keyboard input means and memory means, for processing information stored in the memory means to perform selected functions; output means, coupled to the processing means, for selectively providing an indication of the results of information processed by the processing means; the keyboard input means including a plurality of definable keys, each of which may be associated with a function defined by the user, and a plurality of control keys for defining a function and for associating that defined function with a selected one of the plurality of definable keys; the processing means being responsive to actuation of a selected one of the plurality of definable keys that has previously been associated with a defined function for performin~ that associated defined function.

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-lO5S760 Disclosed hereinafter is an embodiment in which there is employed a keyboard input unit, a magnetic card reading and recording unit, a solid state output display unit, an output printer unit, an input-output control unit, a memory unit and a central processing unit to provide an adaptable programmable calculator having manual operating, automatic operating, program entering, magnetic card reading, magnetic card recording, and alphameric printing modes.
The keyboard input unit includes a group of data keys for entering numeric data into the calculator, a group of control keys for controlling the va rious modes and operations of the calculator and the format of the output display, and a group of definable keys for controlling additional functions that may be added by the user. All of the data keys and nearly all of the control keys may also be employed for programming the calculator, many of the control keys being provided solely for this purpose. The keyboard input unit also includes a group of indicator lights for informing the user of the status of the calculator. These indicator lights and all of the keys are mounted on a front panel of a housing for the calculator.
The magnetic card reading and recording unit includes a reading and recording head, a drive mechanism for driving a magnetic card from an input receptacle in the front panel of the calculator housing past the reading and recording head to an output receptacle in the front panel, and reading and recording drive circuits coupled to the reading and -8a-lOS8760 recording head for bidirectionally transferring information between the magnetic card and the calculator as determined by the control keys of the keyboard input unit. It also in-cludes a pair of detectors and an associated control circuit for disabling the recording drive circuit whenever a notch is detected in the leading edge of the magnetic card to pre-vent information recorded on the magnetic card from being inadvertently destroyed. Such a notch may be provided in any magnetic card the user desires to protect by simply pushing out a perforated portion thereof.
The solid state output display unit includes three rows of light emitting diode arrays and associated drive circuits for selectively displaying three separate lines of numeric information. Numeric data may be displayed in either a fixed or a floating point format as determined by the con-trol keys of the keyboard input unit.
The output printer unit includes a stationary thermal printing head with a row of resistive heating ele-ments, a drive circuit for selectively energizing each heating element, and a stepping mechanism for driving a strip of thermal-sensitive recording paper past the stationary thermal printing head in seven steps for each line of alphameric in-formation to be printed out. Every alphabetic and numeric character and many other symbols may be printed out indivi-dually or in messages as determined by the control keys of the keyboard input unit or by a program stored within the calculator.
The input-output control unit includes a si~teen-bit uni-versal shift register serving as an input-output register into which information may be transferred serially from the central _g _ 105876~) processing unit or in parallel from the keyboard input and magnetic card reading and recording units and from which in-formation may be transferred serially to the central pro-cessing unit or in parallel to the keyboard indicator lights and to the solid state output display, magnetic card reading and recording, and output printer units. It also includes control logic responsive to the central processing unit for controlling the transfer of information between these units.
The input-output control unit may also be employed to per-form the same functions between the central processing unit and peripheral units including, for example, a digitizer, a marked card reader, an X-Y plotter, a magnetic tape unit, and a typewriter. A plurality of peripheral units may be con-nected at the same time to the input-output control unit by simply plugging interface modules associated with the selected peripheral units into receptacles provided therefore in a rear panel of the calculator housing.
The memory unit may employ both direct and indirect decimal and symbolic addressing. It includes a modular random-access read-write memory having a program storage section for storing a plurality of program steps and having a separate data storage section including a plurality of working registers, a plurality of associated display re-gisters, and a plurality of storage registers for manipulating and storing data. These program and data storage sections of the read-write memory may be separately expanded without increasing the overall dimensions of the calculator by the addition of program storage modules or by the alteration of the data storage memory control. Additional read-write memory made available to the user is automatically accommodated -~ lOS~760 by the calculator, and the user is automatically informed when the program or data storage capacity o~ the read-write memory has been exceeded.
The memory unit also includes a modular read-only memory in wh~ch routines and subroutines of basic instruc-tions for performing the various functions of the calculator are stored. These routines and subroutines of the read-o~ly memory may be expanded and adapted by the user to per-~orm additional functions oriented toward the speci~ic needs of the user. This is accomplished by simply plugging ad-ditional read-only memory modules into receptacles provided therefor in the top panel of the calculator housing; Added read-only memory modules are automatically accommodated by the calculator and may be associated ~ith the de~inable keys o~ the keyboard input unit or employed to e~pand the opera-tio~s associated with other keys. An overlay is employed with oach added read-onl~ memory module assoc~ated ~ith the de~inable keys of the keyboq~d input unit to identi~y the additional functions that may then be per~ormed by the cal-culator.
Plug-in read-only memory modules includtng, for eæample, an alpha module, a mathematics module, a statistics module, a de~inable functions module, and a typewTiter module may be added to the read-only memory. The alpha m~dule en-ables the calculator to print out every alphabetic character ~ndi~idually or in messages. It employs address~ng enabling it to redefine most of the ~eys of the keyboar~ input unit ~o that it may be e~mployed at the same time as other plug-in read-only memory modules. The mathematics module enableq the calculator to perform trigonometric functions, coordinate l~S876~

transformations, vector arithmetic, and many other mathe-matical functions. Similarly, the statistics module enables the calculator to perform random number generations, ac-cumulations of sums, sums of products and sums of squares for up to five variables, linear and multiple linear re-gressions, and many other statistical functions. It also permits the use of a correct key, included among the de-finable keys of the keyboard input unit, to automatically delete data ~rom a statistical analysis. The definable functions module enables the user to store programs of his own choosing in the program storage section of the read-write memory, associate them with some of the definable keys of the keyboard input unit, and protect them from sub-sequently being inadvertently altered or destroyed. It also permits the use of an insert key and a find key, in-cluded among the definable keys of the keyboard input unit, to insert program steps in a program stored in the read-write memory and to find every occurrence of any designated program step in the stored program. The typewriter module enables the calculator to control the entire keyboard of a properly interfaced typewriter.
The memory unit further includes a pair of recir-culating sixteen-bit serial shift registers. One of these registers serves as a memory address register for serially receiving information from an arithmetic-logic unit included in the central processing unit, for parallel addressing any memory location designated by the received information, and for serially transferring the received information back to the arithmetic-logic unit. The other of these registers serves as a memory access register for serially receiving -12_ information from the arithmetic-logic unit, for writing in-formation in parallel into any addressed memory location, for reading information in parallel from any addressed memory location, and for serially transferring information to the arithmetic-logic unit. It also serves as a four-bit parallel shift register for transferring four bits of binary-coded-decimal information in parallel to the arithmetic-logic unit.
The central processing unit includes four recir-culating sixteen-bit serial shift registers, a four-bit serial shift register, the arithmetic logic unit, a programmable clock, and a microprocessor. Two of these sixteen-bit serial shift registers serve as accumulator registers for serially receiving information from and serially transferring in-formation to the arithmetic-logic unit. The accumulator re-gister employed is designated ~y a control flip-flop. One of the accumulator registers also serves as a four-bit paral-lel shift register for receiving four bits of binary-coded-decimal information in parallel from and transferring four bits of such information in parallel to the arithmetic-logic unit.
The two remaining sixteen-bit serial shift registers serve as a program counter register and a qualifier register, re-spectively. They are also employed for serially receiving in~ormation from and serially transferring information to the arithmetic-logic unit. The four-bit serial shift regi-ster serves as an extend register for serially receiving in-formation from either the memory access register or the arithmetic-logic unit and for serially transferring infor-mation to the arithmetic-logic unit.
The arithmetic-logic unit is employed for per-forming one-bit serial binary arithmetic, four-bit parallel binary-coded-decimal arithmetic, and logic operations. It may also be controlled by the microprocessor to perform bi-directional direct and indirect arithmetic between any of a plurality of the working registers and any of the storage registers of the data storage section of the read-write memory.
The programmable c~ock is employed to supply a variable number of shift clock pulses to the arithmetic-logic unit and to the serial shift registers of the input-output, memory, and central processing units. It is also employed to supply clock control signals to the input-output control logic and to the microprocessor.
The microprocessor includes a read-only memory in which a plurality of microinstructions and codes are stored~
These microinstructions and codes are employed to perform the basic instructions of the calculator. They include a plurality of coded and non-coded microinstructions for trans-ferring control to the input-output control logic, for controlling the addressing and accessing of the memory unit, and for controlling the operation of the two ac-cumulator registers, the program counter register, the ex-tend register and the arithmetlc-logic unit. They also include a plurality of clock codes for controlling the operation of the programmable clock, a plurality of qualifier selection codes for selecting qualifiers and serving as primary address codes for addressing the read-only memory of the micropro-cessor, and a plurality of secondary address codes for ad-dressing the read-only memory of the microprocessor. In re-sponse to a control signal from a power supply provided for the calculatorg control signals for the programm~ble clock, and qualifier-control signals from the central-processing 105876~
and input-output control units, the microprocessor issues the microinstructions and codes stored in the read-only memory of the microprocessor as required to process either binary or binary-coded-decimal information entered into or stored in the calculator.
In the manual operating mode, the calculator is controlled by keycodes sequentially entered into the cal-culator from the keyboard input unit by the user. The solid state output display unit displays a numeric repre-1~ sentation of the contents of three of the working registersand their associated display registers. These working re-gisters and their associated display registers may contain the last-entered numeric operand and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The out-put printer unit may be controlled by the user to selectively print out a numeric representation of any numeric data entered into the calculator from the keyboard input unit, a numeric representation of any result calculated by the cal-culator, and a mark distinguishing numeric data entries fromcalculated numeric results. If the alpha read-only memory module is plugged into the calculator, the output printer unit may also be controlled by the user to print out labels for inputs to and outputs from the calculator and any other alphabetic information that may be desired.
When the calculator is in the manual operating mode, it may also be operated in a key-log alphameric printing mode.
The output printer unit then prints out a numeric representa-tion of each keycode as it is entered by the user. If the alpha read-only memory module is plugged into the calculator, .

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the output printer unit also prints out a mnemonic representa-tion of each such keycode.
In the automatic operating mode, the calculator is controlled by automatically obtaining keycodes stored as steps of a program in the program storage section of the read-write memory. During automatic operation of the cal-culator, data may be obtained from the memory unit as de-signated by the program or may be entered ~rom the keyboard input unit by the user while the operation of the calculator is stopped for data either by the program or by the user.
The solid state output display unit displays the final con-tents of the three working registers and their associated display registers. This may include the final calculated numeric result and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The output printer unit prints out calculated numeric results and other numeric information designated by the program. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out any alphabetic information de-signated by the program.
When the calculator is in the automatic operating mode, the user may also employ a step program control key of the keyboard input unit to single step forward through the program being e~ecuted. This enables the user to check the execution of the program step by step in order to determine whether the program, as entered into the calculator, does in fact carry out the desired sequence of operations.
In the program entering mode, keycodes are sequen-tially entered by the user into the calculator from the lOS8760 keyboard input unit and are stored as steps of a program inthe program storage section of the read-write memory. The program may include sequences of program steps that will be intrepreted, when the program is executed, as alphabetic information to be printed out by the output printer unit if the alpha read-only memory module is plugged into the cal-culator This alphabetic information may include labels for inputs to and outputs from the calculator, alphabetic messages for facilitating the use of the program and the opera-tion of the calculator, or any other alphabetic informationthat may be desired While the user is entering a program into the calculator in the program entering modej the solid state output display unit displays a numeric representation of the last-entered program step and its associated address and the addresses of the next two program steps to be entered and the present contents of those addresses.
In the program entering mode, the user may also employ the step program control key and a back step control key of the keyboard input unit, to single step either for-ward or backward through any sequence of program steps storedin the program storage section of the read-write ~emory.
While the user is single stepping forward or backward through a sequence of program steps~ the solid state output display unit displays a numeric representation of the last-encountered program step, the program step presently encountered, the next program step to be encountered, and the addresses of these program steps. If the definable functions read-only memory module is plugged into the calculator, the user may also employ the insert and find keys described above by switching to the manual operating mode. These features ~o5~76o greatly facilitate the editing of programs stored in the program storage section of the read-write memory.
When the calculator is in the program entering mode, it may also be operated in a key-log alphameric printing mode. The output printer unit then prints out a numeric representation o~ each program step and its associated ad-dress as it is entered into the calculator from the keyboard input unit by the user. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each such program step.
When the calculator is in the program entering mode, it may also be operated in a list alphameric printing mode.
The output printer unit then prints out a numeric repre-sentation of e~ery program step then stored in the program storage section of the read-write memory and a numeric re-presentation of the addresses of those program steps. If the alpha read-only memory module is plugged into the cal-culator, the output printer unit also prints out a mnemonic representation of each such program step.
In the magnetic card reading mode, the magnetic card reading and recording unit may be employed by the user to separately load either data or programs into the calculator from one or more external magnetic cards. Data and programs 90 loaded are separately stored in the data storage and pro-gram storage sections of the read-~Tite memory.
In the magnetic card recording mode, the magnetic card reading and recording unit may be employed by the user to separately record either data or programs, separately stored in the data storage and program storage sections of the read-write memory, onto one or more external magnetic cards. Programs stored in the program storage section of the read-write memory may be coded by the user as being secure when they are recorded onto one or more external magnetic cards. The calculator detects such programs when they are reloaded into the calculator and prevents the user from re-recording them or obtaining any listing or other indication of the individual program steps.
Description of the Drawings Figure 1 is a front perspective view of an adaptable programmable calculator according to the preferred embodiment of this invention.
Figure 2 is a rear perspective view of the adaptable programmable calculator of Figure 1.
Figures 3A-B are simplified block diagrams of the adaptable programmable calculator of Figures 1 and 2.
Figure 4 is a memory map of the memory unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 5 is a detailed memory map of the dedicated portion of the data storage section of the read-write memory employed in the memory unit of Figures 3A-B and 4.
Figure 6 is a detailed memory map of the dedicated portion of the program storage section of the read-write memory employed in the memory unit of Figures 3A-B and 4.
Figure 7 is a simplified operational logic flow chart illustrating the operation of the microprocessor employed in the central processing unit of Figures 3A-B.
Figure 8 is a plan view of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2 and 3A-B showing how the keyboard input unit may be redefined by 1~58~60 an alpha plug-in read-only memory module ~hat may also be employed ln the adaptable programm~hle calculator.
Figure 9 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a definable functions plug-in read-only memory module that may be employed in the adaptable pro-grammable calculator.
Figure 10 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a mathematics plug-in read-only memory module that may be employed in the adaptable programmable calculator.
Figure 11 (sheet 7) is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B and the overlay associated with a statistics plug-in read-only memory module that may be employed in the adaptable programmable calculator.
Figure 12 (sheet 9) is a plan view of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B
showing how the keyboard input unit may be redefined by a typewriter plug-in read-only memory module that may also be employed in the adaptable programmable calculator.
Figure 13 is a simplified flow chart of the overall control sequence employed for keycode processing in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 14 is a flow chart of the display routine of Figure 13.
Figuresl5A-C are flow charts of the display list building routine of Figure 14.
Figure 16 is a map of the output bit assignment for - ~ 0 -. , ,., ' .

~05~760 the seven-segment display employed in the adaptable programmable calculator ..
o~ Figures l, 2, and 3A~
Figure 17 is a map of the display list built in the read-write memory of Figures 3A-B, 4, and 5.
Figure 18 is a map of the internal structure of the display list of Figure 17.
Figures l9A-B are flow charts of the monitor routine employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 20A-B are flow charts of the interpreter routine of Figure 13.
Figures 21A-D are flow charts of the program mode key, run mode key, floating-point display key, and fixed-point display key processing routines, respectively, of Figure 13.
~ Figure 22 is a map of the status word register of Figure 5 illustrating .~ how it is employed by some of the routines of Figures 21A-D.
Figure 23 is a flow chart of the back step key processing routine . of Figure 13.
. Figure 24 is a flow chart of the clear key processing routine . selectable by the interpreter routine of Figure 13.
Figure 25 is a flow chart of the end key processing routine select-able by the interpreter routine of Figure 13.
~ Figure 26 is a flow chart of the stop key processing routine select-able by the interpreter routine of Figure 13.
Figure 27 (sheet 23) is a flow chart of the integer x key processing routine selectable by the interpreter routine of Figure 13.
` Figure 28 (sheet 22) is a flow chart of the pi key processing '' 105~3760 . routine selectable by the interpreter routine o~ Figure 13.
. Figure 29 (sheet 22) is a flow chart of the clear x key processing routine selectable by the interpreter of Figure 13.
Figures 30A-B are simpli~ied ~low charts o~ the number entry processing routine selectable by the interpreter ; o~ Figure 13.
Figures 31A-C are ~low char~s o~ portlons o~ the magnitude processing portions of the number entry routine o~
Figures 30A-B.
Figures 32A-B are ~low charts of e~ponent processing portions o~ the number entry routi~e o~ Figures 30A-B.
Figure 33 is a flow chart o~ the change-sign pro-cessi~g portion o~ the number entry routine o~ Figures 30A-B.
~ igure 34 is a ~low chart o~ the termination portion o~ the number entry routine o~ Figures 30A-B.
Figure 35 is a ~low chart o~ the up-key processing routine selectable by the interpreter o~ Figures 13.
Figure 36 is a ~low chart o~ the down-key processing ,`'~';l ~ routine selectable by the int~rpreter routine o~ Figure 13.
:
:.~ 20 Figure 37 is a ~low chart o~ the roll-up key.pracessing ~ routine selectable by the interpreter routi~e of Figure 13.
: F~gures 38A-B are simplified ~low charts o~ the re-' gister traas~er a~d reg~ster arithmetic rout~nes selectable by the interpreter routi~e o~ Figure 13.
. Figures 39A-B are ~low charts o~ the register transfer and automatic address termination routi~e employed i~ con-nection with the register transfer arithmetic key processi~g routine o~ Figures ~8A-B.
; Figure 40 is a ~Io~ chart of the indirect-key pro-cessing routine selectable by the interpreter routine o~ Figure 13.

lOS8760 Figure 41 is a ~low chart of the a- and b-register transfer key processing routines selectable by the interpreter routine o~ Figure 13.
Figure 42 is a flow chart of the indirect address computation routine employed in connection with the indirect-` key processing routine of Figure 40.
Figure 43 is a ~lo~ chart o~ the decimal address ~umpand automatic address termination routine employed in con-nection with the go-to and i~ key processing routines selectable by the interpreter routine o~ Figure 13.
Figure 44 is a flow chart o~ the label-key processing routine selectable by the interpreter routine o~ Figure 13.
Figure 45 is a ~low chart of the if key processing routine selectable by the interpreter routine of Figure 13.
~ igure 46 is a ~low chart of the su~routine/retur~
key processing routine selectable by the interpreter routine o~ Figure 13.
Figures 47A-C are ~low chart~ o~ the ~loating point add and subtract key processing routines selectable by the interpreter routine o~ Figure 13.
Figure 48 is a flow chart o~ the ~loating poi~t multi-ply key processing routine selectable by the interpreter routine of Figure 13.
Figures 49A-B are flow charts o~ the ~loatlng point division ke~ processing routine o~ Figure 13.
Figures 50A-C are flow charts o~ the loating point square root key processing routine selectable by the inter-.' . - .
. preter rout~ne of Figure 13.
Figure 51 (sheet 48) i~ a flow chart of the store routine of Figure 13.

_23-lOS~760 i Figure 52 (sheet 47) is a flow chart of the rounding routine employed in connection with several of the routines selectable by the interpreter routine of Figure 13.
Figure 53 (~heet 47) is a flow chart of the x-squared key processing routine selectable by the interpreter routine of Figure 13.
Figure 54 (sheet 47) is a flow chart of the reciprocal-x key processing routine i~electable by the interpreter routine of Figure 13.
Figure 55A-B are ~low charts of the basic ~ormat key processi~g routine selectable by the interpreter routine o~
.. Figure 13.
: Figure 56 is a flow chart of a search routine that may :~ be employed in connection with the basic ~ormat key processing routine o~ F1gures 55A-B.
. ~igure 57 is a memor~ map illustrating the use o~ the search routine o~ Figure 56.
. F~gures 58A-B are flow charts o~ a plotter routine .`, employed in co~nection ~ith the basic format key processing .
routine o~ Figures 55A-B.
` Figure 59 is a map of a memory register em~loyed in con~ection with the plott2r routine o~ Figures 58A-B.
Figure 60 is a ~low chart of the program-step re-cording portion of the record key processing routine o~
Figure 13.
F~gure 61 is a ~lo~ ch æ t of the program-step loading portion of the load key processing routi~e of ~igure 13.
Figure-62 is a memory map o~ the progra~ storage section of the read-write memory of Figures 3A-B and 4-6 illustrating how a secure program is destroyed by an unsecure program.

_24--' lOS8760 Figure 63 is a flow chart of the format record~ng portion oi the record key processing routine o~ Figure 13.
Figure 64 is a ~low chart o~ the data recording portion o~ the record key processing routine o~ Figure 13.
Figure 65 is a ~low chart o~ the data loading portion o~ the load key processing routine of Figure 13.
Figure 66 is a ilow chart showing how a plug-i~
, . read-only memory module employed in the adaptable programmable calculator o~ Figures 1, 2,and 3A-B can obtain keycordes from a program stored in the program storage section of the read-write memory of Figures 3A-B and 4.
Figures 67A-C show how the print routine accesses code in~ormation stored in tables i~ the data storage section o~ the read-write memory o~ Figures 3A-B and 4.
, Figures 68A-B are memory maps of a directive table and a code table respectively, in an alpha plug-in -read-on}~ me~or~ module that may be employed in the adaptable programmable calculator o~ Figures 1, 2,and 3A~B.
Figur~ 69 ~s a ~low chart showi~g how the pri~ter code is accessed by an alpha plug-in read-only memory module .~. . employed in the adaptable programmable calculator o~ Figure~
1, 2,and 3A-B.
Figures 70A-8 are ~low charts of the typewriter -~ormat routine employed in connection with the ~ormat key :. processing routine selectable by the interpreter routine o~
Eigure 13.
Eigure 71 is a memory map o~ a typewriter mnemonic table in a typewrtter plug-in read-only memory module that ma~
be employed in the adaptable programmable calculator of 3~ ~igures 1, 2,and 3A-B.

-25_ . , ,~, , ~.~5~760 Figure 72 is a ~low chart o~ a typewriter list routine that may be performed when the typewriter read- ( only memory module is plugged into the adaptable programmable calculator of Figures 1, ~ and 3A-B.
Figure 73 is a ~low chart of a typewriter print routine that may be per~ormed when the typewriter read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2,and ~-B.
Figure 74 is a ~low chart o~ a typewriter alpha routine that may be per~ormed when the typewriter read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
` Figure 75 is a ~low chart o~ a definable ~eycode entry routine em~loyed when the de~inable ~unctions read-only memory module is plugged into the calculator.
i Figure 76 is a flow chart of a protect key pr~cessing ;~ ~outine that may be performed when the definable functions read-only memory module i5 plugged into the calculator.
Figure 77 i~ a flow chart of a memory search routine that may be performed when the definable functions read-only memory module i5 plugged into the calculator.
Figures 78A-B are ilow charts of a de~inable ~unction calls routi~e that may be per~ormed when the def~able ~unc-tions read-only memory module is plugged into the calculator.
Eigure 79 is a direct~ve table o~ the fu~ction calls that may be performed by the def~uable ~unction calls routine of F~gures 78A-B.
Eigure 80 is a flow chart of a de~inable ~unction return routine employed with the defi~able ~u~ctio~ calls routine of Figures 78A-B.

S~76() ~--Figure 81 is a flow chart of a turn-of~-the-functio~
light subroutine employed by the de~inable ~unction return ` routine o~ Figure 80.
Figure 82 is a flow chart of a function stack checking subroutine employed by the de~inable ~unction calls routlne and the definable function return routine of Figures 78A-B and 80, respectively.
Figure 83 is a ~low chart of a delete-protect routine ~ that may be per~ormed when the definable functions read-only s memory module is plugged into the adaptable programmable ' 10 calculator of Figures 1, 2,and 3A-B.
~igure 84 is a flow chart o~ a turn-off-the-delete-, .
light subroutine employed by the delete-protect routine of Figure 83.
Figure 85 is a ~lo~ chart o~ an empty-the-fuuction-stack ~ubroutine employed by the delete-protect routine o~
: . Figure 83.
Figure 86 is a ~low chart of a find routine that may be performed when the definable functions read-o~ly memory module is plugged into the adaptable programmable calculator of Figures 1, 2,and 3A-~.
Figure 87 is a flow chart o~ a get-the-next-~ey sub-routine employed by the ~ind routine o~ Figure 86.
Flgure 88 is a ilow chart o~ a memory compactor rou~ine that may be performed when the definable functions read-only memory ~odule is plugged into the adaptable programmable calculator of F~gures 1, 2, and 3A-B.
Eigure 89 is a memory map illustrating the use of the memory compactor subroutine o~ F~gure 88, Figures gOA-C are flow charts of a delete routi~e that may be performed when the definable ~unctio~ read-only memory module is plu~ged into tl~e adaptable programmable calculator o~ Figures 1, 2, and 3A-s.

1~5~760 F~gures 91A-e are flow charts of an insert routine that may be performed when the aefinable functions read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 92 is a flow chart of an address calculating subroutine employed by the insert routine of Figures 91A-B.
Figures 93A-B are flow charts of a tangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 94A-B are flow charts of an arctangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figures 95A-B are flow charts of an e-to-the-x-power routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 19 2, and 3A-B.

.1 ! Figure 96 is a flow chart of a natural logarithm x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 97 is a flow chart of a subroutine employed by the tangent x and the e-to-the-x-power routines of Figures 93A-B and 95A-B, respectively.
Figures98A-B are flow charts of a subroutine employed by the tangent x and arctangent x routines of Figures 93A-B and 94A-B, respectively.
Figures 99A-B are flow charts of a subroutine employed by the e-to-the-x-power and natural logarithm x routines of Figures :

' ` 1058760 95A-B and 96, respectively.
~ igure 100 is a ~low chart o~ a subroutine employed by the arctangent x and natural logarlthm x routines o~
Flgures 94A-B and 96, respectively.
Figure 101 is a ~lo~ chart of sine and cosine routines that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-B.
Figure 102 is a ~low chart o~ a table ~(x) routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-B.
~r Figure 103 is a flow chart o~ an arc routine that may - be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~
` Figures 1, 2, and 3A-B.
Figure 104 is a flow chart o~ an arcsine routine that may be performed when the mathematics read-only memory module ls plugged into the adaptable programmable calculator of 0 Figures 1, 2, and 3A-B.
i Figure 105 is a ~low chart of an arccosine routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~ Figures L, 2, and 3A-B.
Figure 106 is a ~low chart o~ a conversion to polar coordinates rout~ne that may be per~ormed when the mathe-matics read-only memory module is plugged into the adaptable ~rogrammable càlculator o~ Figures 1, ~, and 3A-B.
Figure 107 is a ilow chart o~ a conversion to rec-;` . ... . . .
3~ tangul~r coordinates routine that may be per~ormed when the .

. . .
.
.

lOS8760 mathematics read-only memory module is plugged into the adaptable programmabl~ calculator o~ Figures 1, 2, and 3A-B~
Figure 108 is a ~low chart of a ten-to-the -x-power . routise that may be per~ormed when the mathematics read-o~ly memory module is plugged into the adaptable pro-grzmmable calculator of Figures 1, 2, and 3A-B.
Figure 109 is a flow chart of an absolute Yalue y .routine that may be performed when the mathematics read-only memory module is plugged into the adaptable pro-grammable calculator o~ Figures 1, 2, and 3A-B.
Figure 110 is a ~low chart o~ an x-to-the-y-power . . .
routine that may be per~ormed when the mathematics read-only memory module is plugged into the adaptable pro-- grammable calculator of Figures 1, 2, and 3A-B.
Figure 111 is a ~low chart o~ a logarithm-to-the-base-ten routine that may be per~ormed when the mathematics r.e2d-on~ ~2mcry..module is ~lugged into the adaptable pro-grammable calculator of Figures 1, 2, and 3A-B.
Figure 112 is a ilow chart o~ a routine ~or converting degrees, minutes, and seconds to degrees that may be per~ormed - when the mathematics read-only memory module is plugged lnto ;~ the adaptable programmable calculator of Figures 1, 2, and 3A-B. Figure 113 is a ~low chart o~ a routine ior converting degrees to degrees, ~inutes, and.seconds that may be performed ~hen the mathematics read-~ly memory module is plugged into the adaptable progra~mable calculator oi Figures 1, 2, and 3A-B.
Eigure 114 is a ~low chart o~ a.subroutine employed : bg ~he routine.. ~oi Figure 11~ for conYerting degrees to degrees, minutes,a~d seconds.
Pigure 115 is a ~low chart o~ an x ~actorial routine .

~ lOS8760 that may be employed when the mathematics read-only memory module is plu~ged into the adaptahle programmable calculator o~ Fi~ures 1, 2, and 3A-s.
Figure 116 is a flow chart o~ a recall routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator o~
Figuresl, 2, and 3A-B.
Figure 117 is a flow chart of an accumulate plus `. routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calcuIator of Figures 1, 2, and 3A-s.
Figure 118 is a ~low chart o~ an accumulate minus routine that may be employed when the mathematics read-only memory module is plugged into the adaptable.programmable ` calculator o~ Figur~s 1, 2, and 3A-B.
Figqres 119A-B are ~lo~ charts o~ a rounding routine that may be employed when the mathematics read-only memory . ~odule ~s plugged into the adaptable programmable calculator of Figur~ 1, 2, and 3A-B.
. .
: 20 Figure 120 is a ~low chart of a scale routine that may be employed when the mathematics read-only memory module is plugged into the adaptable progra~mable calculator of Figur~ 1, 2, and 3A-B.
Figure 121 is a ~low chart o~ a subroutine employed .
by the scale routine o~ Figure 120.
Figure 122 is a flow chart o~ a clear routine that . may be employed when the mathematics read-only memory module `~ is piugged into~the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 123 is a ~low chart o~ a de~inable i(x) . . .

. .
:

lOS~760 routi~e that may be employed when the mathematics re~d-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-s.
; Figure 124 is a flow chart o~ a do-loop rout~ne that may be employed when the mathematics read-only memory module ~s plugged into the adaptable programmable calculator o~
, Figures 1, 2, and 3A-B.
Figures 125A-B are flow charts of a ~ummation routine that may be per~ormed when the statistics read-only memory module is plugged into the adaptable programmable calculator o~
Figures 1, 2, and 3A-B.
Figure 126 ls a ~low chart of a correct routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 127 is a flow chart o~ a t-pair routine that may be per~ormed when the statistics read-only memory module is plugged into the adaptable prog$ammable calculator of Figures 1, 2, and 3A-B.
Figure 128 is a ~low chart o~ an x s~uared routine that ~ay be per~ormed whe~ the statistics read-only memory module is plugged into the adaptable programmable calculator o~
Figures 1, 2, and 3A-B.
Figure 129 is a ~low chart of a mean value routine.
that may be per~ormed ~hen the statistics read-onl~ memory module is plugged into the adaptable programmable calculato~
.. .. . . .... .
~3 o~ Figures 1, 2, and 3A-B.
Figure i30 is a ~low chart of a maximum/minimum - routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-s.
Figure 131 ls a flow chart of a ~ariance routi~e that may be per~urmed when the statistics read-only memory module is plugged into the adaptable programmable calculator o~ Figures 1, 2, and 3A-s.
: -32-~058760 Figure 132 is a flow chart of an initialize routine that may be - ~ performed when the statistics read~only memory module is plug3ed into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 133 is a flow chart of a regression routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 134 (sheet 113) is a flow chart of a variables routine ; that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 135 (sheet 112) is a flow chart of an r2-correlation routine that may be performed when the statistics read-only memory module is plugged . into the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 136 is a block diagram of the microprocessor of Figures 3A-B.
Figures 137A-D are detailed schematic diagrams of the microprocessor of Figures 3A-B and 136.
i Figure 137'is a figure map showing how the detailed schematic dia-grams of Figures 137A-D fit together.

Figures 1 38A-H are detailed flow charts illustrating the operation of the microprocessor of Figures 3A-B, 136, and 137A-D.

Figure 138'is a figure map showing how the detailed flow charts OT

Figures 138A-D fit together.

Figure 138" is a figure map showing how the detailed flow charts 6 of Figures 138E-H fit together.

Figure 138I shows the macro-instruction coding table, the used data format, and the used address and constants for the micro-processor of Figures 3A-B and 136.

Figure 138J is an instruction table for the microprocessor of Figures 3A-B and 136.

Figure 139 is a block diagram of the programmable clock of Figures 3A-B.

Figures 140A-C (sheets 119 and 129-131) are detailed ' ~s~7~v schematic diagrams of the programmable clock of Figures ~A-B
and 139 and of a portion of the input-output control unit of .
Figures 3A-B.
Figure 140' is a figure map showing how the detailed schematic diagrams of Figures 140A-C fit together.
Figure 141 is a waveform diagram illustrati~g the .
operation o~ the programmable clock of Figures 3A-B, 139, and 140A-C.
Figure~ 142A-D (sheet 119 and 133-136) are detailed schematic diagrams of the ~hift register and aritkmetic-logic units of Figures 3A-B.
; Figure 142' is a figure map sh~wing how the detailed schematic diagrams of Figures 142A-D fi~ together.
~igure 143 is a bloc~ diagram o~ the arith~etic-logic unit o~ Figures 3A-B.
, Figure 144 is a table o~ the ~unction code assignmeuts :` o~ the arithmetic-logic u~it of Figures 142A-D and 143.
Figure 145 is a table of ~ntegra~ed circuits that may `~ be employed to co~struct the ~L~ o~ Figures 142A-D and 143.
. 20 ~igure 146 is a block diagram o~ the memory un~t o~
Figures 3A-B.
~igure 147 ~s a table o~ mnemo~ics used ~n the memory , ~ uuit of Figures 3A-B.
.. Figure 148 is a schematic diagram o~ the read-write memory o~ ~igures 3A-B, 4, and 146.
Figu~e 149 is a schematic diagra~ o~ one o~ the add-on read-urite memory modules o~ Figure 146 that may be plugged . into the calculator to increase the amou~t o~ program storage memory a~ailable to the user.
. 30 ~igure 150 is a schematic diagram of the other add-on read-~rite memory module o~ F~gure 146 that may be plugged i~to the calculator to ~urther increase the amount of program storage memory a~aila~le to the user.
, , : _~A_ ~C)5~760 Figure 151 is a schematic diagram of the read-only memory of FigureB 3A-B, 4 and 146.
Figure 152 is a schematic diagram of the add-on read-only memory modules of Figure 146 that may be plugged into the calculator to increase the number of functions available to the user.
Figure 153 ig a block diagram of one of the read-only memory chips of Figures 151-152.
Figureg 154A-D (gheets 119 and 147-150) are schematic diagrams of one of the read-only memory chips of Figures 151-152.
Figure 154 ' is a figure map showing how the detailed schematic diagrams of Figures 154A-D fit together.
Figure 155 is a memory map of the memory unit of Figureg 3A-B and ~ illustrating how it is partitioned into , the read-only and read-write memory chips of Figures 148-153 and 154A-D.
Figure 156 is a flow chart illustrating how the row ~ numberY of the lists stored in the read-only memory chips are -~; 20 computed.
Figure 157 is a table of bit numbers and actual bits u~ed in connection with the flow chart of Figure 156.
Figures 158A-D are detailed schematic diagrams of the memory address register of Figures 3A-B and 146.
Figure 158' is a figure map showing now the detailed schematic diagrams of Figures 158A-D fit together.
Figures159A-D are detailed schematic diagrams of the control circuitry of Figure 3 and 146.
Figure 159' is a igure map showing how the detailed schematic diagrams of Figures l59A-D fit together.
. , .

l~S8760 Figure 160 is a waveform diagram illustrating the operation of the control circuitry of Figures 159A-D.
Figures 161A-D (sheets 157 and 163-166) are detailed schematic diagrams of the memory access register of Figures 3A-B and 146.
Figure 161' is a figure map showing how the detailed schematic diagrams of Figures 16L~-D fit together.
Figures 162A-D (sheets 157 and 167-170) are detailed schematic diagrams of the input-output register and gating control circuits employed in the input-output control unit of Figure 3 .
Figure 162' is a figure map showing how the detailed schematic diagrams of Figures 162A-D fit together.
Figure 163 is a schematic diagram of the source and relationship of the input~output party lines connected to the peripheral interface module receiving receptacles of Figure 2.
Figure 164 is a waveform diagram illustrating the ~: operation of the control section of the input-output control unit of Figures 3A-B and 140A-C.
Figure 165 is a flow chart illustrating the operation 0 of the cont~ol section of the input-output control unit of Figures 3A-8 and 140A-C.
Figure 166 i8 a schematic diagram of the address code ` decoding for the output selection portion of the interface .. modules employed with the input-output control unit of Figures 3A-B.
Figure 167 is a chart listing and defining all of the input-output lines of the input-output control unit of Figures 3A-B.

- 105~3760 Figure 168 is a waveform diagram o~ some of ~he out-put signals employed by the input-output control unit and . associated interface modules o:~ Figures 3A-B.
Figure 169 is a wave~orm diagram o~ some of the input sign~ls employed,by the input-output control unit and associated inter~ace modules of Figures 3A-B.
Figure 170 is a wave~orm diagram illustrating the operation o~ the interrupt mode of operation of the input-output control unit of Figures 3A-B.
Figure 171 is a schematic diagram of logic that may be used to interface an output peripheral to the input-output control unit of Figures 3A-B.
. Figure 172 is a sche~atic diagram o~ logic that may be used to interface an input peripheral to the input-output control unit of Figures 3A-B.
Figure 173 is a schematic diagram of logic that may be us~d to interXace an interruptlng peripheral to the input-output contro~ unit of Figures 3A-B.
.., . ., .. . _ : Figures 174A-D (sheets 157 and 178-181) are detailed schematic diagrams of the keyboard input unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 174' i~ a figure map showing how the detailed ~chematic diagrams of Figures 174A-D fit together.
Figure 175 (sheet 180) is a schematic diagram of one of the transformer pairs employed in the keyboard input unit of Figures 174A-D.
Figure 176 is a pictorial ~iew of a transformer employed in the keyboard input ~nit o~ Figures 3A-B.
Figure 177 is a schemat~c diagram of the transformer of Figure 176.
Figure 178 is a schematic diagram of a portion o~ the .key~oard i~put unit og Figures 174A-D~

~OS876~) Figure 179 (sheet 179) illus~rates the required polarities for the driv~ and ser,se lines emplo~e~ in tne keyboard input unit of Fi3ures -- 3A-B and 176.
Figure 180 is a block diagram of the magnetic card reading and recording unit employed in the calculator of Figures 1, 2, and 3A-B.
Figures 181A-G are schematic diagrams of the magnetic card reading and recording unit of Figure 180.
` Figure 181' is a figure map showing how the detailed schematic .; diagrams of Figures 181A-G fit together.
Figure 182 is a block diagram illustrating how the magnetic card reading and recording unit of Figures 180 and 181A-G interacts with the calculator of Figures 1, 2, and 3A-B.
Figure 183 is a block diagram of the output display unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
~ Figures 184A-B are detailed schematic diagrams of the output display $~ unit of Figure 183.
~i Figure 184' is a figure map showing how the detailed schematic `I diagram of Figures 184A-B fit together.
" Figure 185 is a block diagram of the output printer unit employed in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
, Figure 186 is a cross-sectional view taken along the line A-A in ::;
Figure 185.
Figures 187A-B (sheets 191, 197, and 198) are detailed schematic Z~ diagrams of the thermal printing head, isolation diodes, four group drivers, and one-of-ten decoder of Figure 185.
Figure 187' is a figure map showing how the detailed schematic diagrams of Figures 187A-B fit together.
Figure 188 is a partial plan view of the thermal printing head of Figure 185.

~ -38-:
:" .
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~5~760 - Figures 189A-D are detailed schematic diagrams of the twenty dot drivers, the internal ten-b;t shift register, the mctor drivers, the motor drive control circuit, and the printer timing circuit of Figure 185.
Figure 190 is a figure map showing how the detailed schematic diagrams of Figures 189A-D fit together.
Figures l91A-B (sheets 191, 204,and 205) are detailed schematic diagrams of the motor drivers of Figure 185.
Figure 191' is a figure map showing how the detailed schematic diagrams of Figures l91A-B fit together.
Figure 192 illustrates how the output printer unit of Figures 185-191 prints out each character.
Figure 193 is a flow chart illustrating the printing operation of the output printer unit of Figures 185, 186, 187A-B, 188, 189A-D, and l91A-B.
Figure 194 is a block diagram of the power supply system employed ~ in the adaptable programmable calculator of Figures 1, 2, and 3A-B.
,~J Figure 195 is a detailed schematic of the five volt power supply ,! of Figure 194.
'! Figure 196 is a detailed schematic diagram of the sixteen, twenty, '~ and twenty-four volt power supplies of Figure 194.
Figures 197A-B are detailed schematic diagrams of the positive and negative twelve volt power supplies of Flgure 194.
Figure 198 (sheet 206) is a schematic diagram of an alternative ripple signal circuit that may be employed in the power supply of Figure 195.
Figures l99A-B are block diagrams of an interface module that may be employed to interface a typewriter to the adaptable programmable calculator of Figures 1, 2, and 3A-B.
Figure 199' is a figure map showing how the block diagrams of Figures l99A-B fit together.
Figures 200A-C are schematic diagrams of the interface module of Figures l99A-B.
Figure 200' is a figure map showing how the schematic diagrams of Figures 200A-C fit together.

, ., , , . ' .

-105~376~) Description of the Preferred Embodiment GENERAL DESCRIPTION
Referring to Figures 1 and 2, there is shown an adaptable programmable calculator lO including both a key-board input unit 12 for entering information into and controlling the operation of the calculator and a magnetic card reading and recording unit 14 for recording informa-tion stored within the calculator onto one or more ex-ternal magnetic cards 16 and for subsequently loading the 10 information recorded on these and other similar magnetic cards back into the calculator. The calculator also includes a solid state output display unit 18 for displaying three ~ lines of numeric in~ormation stored within the calculator and a group of indicator lights 19, serving as part of . the keyboard input unit, for indicating the status of the calculator. It may also include an output printer unit 20 for printing out alphameric information on a strip of thermal-sensitive recording paper 22 All of these input :~ and output units are mounted within a single calculator -. 20 housing 24 adjacent to a curved front panel 26 thereof.
As shown in Figure 2, a plurality of peripheral input and output units 28 including, for example, a digi-tizer, a mar~ed card reader, an ~-Y plotter, and a type-. writer may be connected to the calculator at the same time by simply inserting interface modules 30 associated with the selected peripheral units into any of four receptacles ;~ 32 provided therefor in a rear panel 34 of the calculator housing. As each interface module 30 is inserted into one of these receptacles, a spring-loaded door 38 at the en-. 30 trance of the receptacle swings down allowing passage of , .
`' ~

. . . , ,; , ~OSl~7~V

the interface module. Once the interface module is fully inserted, a printed-circuit terminal board 40 contained within the interface module plugs into a mating edge connector mounted inside the calculator. If any of the selected peripheral units require AC line power, their power cords may be plugged into any of three AC power outlets 42 provided therefor at the rear panel of calculator housing 24.
Referring to the simplified block diagram shown in Figure 3, it s may be seen that the calculator also includes an input-output control unit 44 (hereinafter referred to as the I/O control unit) for controlling the transfer of information to and from the input and output units, a memory unit 46 for storing and manipulating information entered into the calculator and for storing routines and subroutines of basic instructions performed by the calculator, and a central processing unit 48 (hereinafter referred to as the CPU) for controlling the execution of the routines and subroutines of basic instruct10ns stored in the memory unit as required to process informa-tion entered into or stored within the calculator. The calculator also ? includes a bus system comprising an S-bus 50, a T-bus 52, and an R-bus 54 for transferring information from the memory and I/O control units to the ` CPU, from the CPU to the memory and I/O control units, and between different portions of the CPU. It further comprises a power supply for supplying DC
power to the calculator and peripheral units employed therewith and for issuing a control signal POP when power is supplied to the calculator.
The I/O control unit 44 includes an input-output ~' :

. .

~5~37f~V

register 56 (hereinafter referred to as the I/0 register), associated I/0 gating control circuitry 58, and input-output control logic 60 (hereinafter referred to as the I/0 control), I/0 register 56 comprises a universal six-teen-bit shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from keyboard input unit 12, magnetic card reading and recording unit 14, and peripheral input units 28 such as the marked card reader via twelve input party lines 62.
Information may also be transferred from I/0 register 56 either bit-serially to CPU 48 via S-bus 50 or in parallel to magnetic card reading and recording unit 14, solid state output display unit 18, indicator lights 19, output printer unit 20, and peripheral output units 28 such as the X-Y plotter or the typewriter via sixteen output party lines 64.
I/0 gating control circuitry 58 includes control circuits for controlling the transfer of information into and out of I/0 register 56 in response to selected I/0 qualifier control signals from CPU 48 and selected ` I/0 control instructions from I/0 control 60. It also includes an interrupt . control circuit 65, a peripheral control circuit 66, a magnetic card control circuit 67, a printer control circuit 68, a display control circuit 69, and an indicator control circuit 70 for variously controlling the input and output units and issuing control signals QFG and EBT to I/0 control 60 via two output lines 71 and 72. These last mentioned control circuits variously perform their control functions in response to control signal ~F from the power supply, I/0 qualifier control signals from CPU 48, I/0 control instructions . from I/0 control 60, and control signals from keyboard input unit 12. Inter-rupt control circuit 65 '~;

initiates the transfer of information into I/O register 56 from keyboard input unit 12 or interrupting peripheral in-put units 28 such as the marked card reader and issues a qualifier control signal QNR to CPU 48 via output lines 73.
Peripheral control circuit 66 enables interface modules 30 plugged into the calculator to respond to information from I/O register 56, control associated peripheral units 28, transfer information to and/or receive information from associated peripheral units 28, and in some cases initiate the transfer of information to I/O register 56 from the interface modules themselves. Magnetic card control circuit 67 enables magnetic card reading and recording unit 14 to respond to information in I/O register 56 and either read information into I/O register 56 from a magnetic card 16 or record information onto a magnetic card 16 from I/O
register 56. Printer control circuit 68, display control circuit 69, and indicator control circuit ~0 enable output display unit 18, output printer unit 20, and indicator lights 1~, respectively, to respond to information from I/O register 56.
When a basic I/O instruction obtained from memory unit 46 is to be executed, CPU 48 transfers control to I/O
control 60 by issuing a pair of IiO microinstructions PTR
and ~ thereto. In response to these I/O microinstructions from CPU 48, control signal P~F from the power supply, control signals Q~G and EBT from I/O gating control circuitry 58, and I/O qualifier and clock control signals from CPU 48, I/O
control 60 selectively issues one or more I/O control in-structions to gating control circuitry 58 as required to execute the basic I/O instruction designated by CPU 48 and lOS8760 issues control signals ITg, ~Tff, QRD, and SCB to CPU 48 via output lines 74-77. The I/O qualifier control signals issued to I/O control 60 and gating control circuitry 58 by CPU 48 are derived from the basic I/O instruction to be executed. Those qualifier control signals issued to I/O
control 60 designate the specific I/O control instructions to be issued by I/O control 60, while those issued to gating control circuitry 58 designate selected control circuits to be employed in executing the basic I/O instruction.
Memory unit 46 includes a modular random-access read-write memory 78 (hereinafter referred to as the RWM), a mo~ular read-only memory 80 (hereinafter referred to as the ROM), a memory address register 82 (hereinafter re-ferred to as the M-register), a memory access register 84 (hereinafter referred to. as the T-register), and control circu~try 85 for these memories and registers. RWM 78 and RO~ 80 comprise MOS-type semiconductor memories. As shown in the memory map of Figure 4, they are organized into eight 1,024-word pages. The basic RWM 78 contains a data storage section 86 of 512 sixteen-bit words extending from :,' address 1000 to address 1777 on page O and a separate pro-gram storage section 88 of 512 six-bit words extending from address 12000 to address 12777 on page 5. All addresses on the memory map are represented in octal formO
Data storage section 86 contains 49 four-word storage registers available to the user (as user addresses 000-048) for manipulating and storing data, 60 additional four-word storage registers that may be made available to the user (as user addresses 0~9-108) for the same purpose, and 76 words dedicated for use by CPU 48. The 60 additional four-word storage registers may be made available to the 10587t;0 user by altering a control routine i~ the R0~ sectio~ 80.
This is accomplished by removing a top panel 90 o~ the calculator housing shown in Figure 1, remo~ing a printed circuit board.containing the control routine to be altered, and substituti~g another printed circuit ~oard contai~ing the altered control routine. ~dditional data storage modules made available to the user are automatically ac-commodated b~ the calculator.
As s~own in the more detailed memory map o~ Figure 5, the dedicated portion o~ data storage section 86 includes 12 words (addresses 1750-1753, 1740-1743, and 1760-1763) employed as "g", "Y", and "Z" iour-word working registers available to the user a~d 8 words (add~esses 1764-1773) .~ .
em~loyed as "a" and "b" ~our-word storage registers available to the user. It also includes 8 words (addresses 1744-1747 and 1754-1757) employed as "ARl" and "ARZ" ~our-word working registers ~or per~orming binary-coded-decimal arithmet~c;
12 words (addresses 1664-1677) employed as three ("Tl~", "T2"', and "T3"') or more temporary storage registers in connection w1th a de~inable section 91 o~ keyboard input unit 12 (see ~igure 1); 16 words (addresses 1720-1737) e~ployed as ~our ~"Tl", "T2", "T3n, and "T4n) or ~ore tem-porary storage re~isters ~n connection with the remai~ing sections o~ the keyboard tnput unit;,7 words (addresses 1711-1717) employed,as a variable-length "system subrout~ne .. . . . .
, stack" ~or storlng return addresses requ~red by programs stored i~ R0~ 80 and as temporary s-torage ~or housekeepi~g information required by CPU 48; o~e word (address 1~7) em-.
.,. ployed,as a "system stack pointer"; 5 words (addresses 1702-. . .
1706) employed as a "user subrout~ne stack" l'or storing '~' ' : , lOS87f~0 . ..
return addresses required by programs entered into program storage section 88 of RWM 78 by the user; 1 word (address 1710 employed as a "user stack pointer"; 1 word (address 1701) employed as a "user program counter" for program steps entered into program storage section 88 by the user; 1 word (address 1707) employed as an "address of user ~000" register for storing the first address available to the user in program storage section 88; 1 word (address 1700) employed as a "microprocessor store" register for storing housekeeping information required by CPU 48; 1 word (address 1774) employed as an "interrupt store" register for storing information displaced from CPU
48 by some keyboard entries; 1 word (address 1775) employed as an "input buffer" register for storing keyboard information awaiting entry into CPU
48, and 1 word (address 1776) employed as a "status word" register for storing information regarding the present state of the calculator.
As shown in the memory map of Figure 4, program storage section 88 of RWM 78 contains 500 one-word program step registers available to the user (as user addresses 0000-0500) for storing programs and 12 words dedicated for use by CPU 48. An additional 1,536 one-word program-step registers may be made available to the user (as user addresses 0511-2036) in steps of 512 words (addresses 13000-13777) and 1iO24 words (addresses 14000 to 15777).
This is accomplished by removing top panel 90 of the calculator housing shown in Figure 1 and plugging additional program storage modules into the calculator. Added program storage modules are automatically accommodated by the calculator.
As shown in the more detailed memory map of Figure 6, the dedicated portion of program storage section 88 ., . ~058760 - includes 1 word (address 12013) employed as a "security word" register for storing a code designating a program stored in program storage section 88 as being secure. It also includes 1 word (address 12000) employed as an "exe-cution flag" register for storing information indicating whether CPU 48 is being controlled by a program stored in the program storage section or by the keyboard input unit;

2 words (addresses 12001-12002) employed as "normalize flag" and "print flag" registers for storing information about numeric data being processed by CPU 48; 3 words (addresses 12003-12005) employed as "temporary display~ re-gisters for storing housekeeping information about the ~ character position, decimal position, and register loca-; tion of numeric information being displayed by the output ~ display unit; 1 word (address 12006) employed as a "print j code buffer" register for storing housekeeping information about alphameric information being printed out by the out-" put printer unit; and 4 words (addresses 12007-12012) available for other uses.
As shown in the memory map of Figure 4, the basic ROM 80 contains 2,048 sixteen-bit words extending from address 0000 to address 0777 on page 0, from address 4000 ~ to address 5777 on page 2, and from address 16000 to address `~ 16777 on page 7, Routines and subroutines of basic in-struct~ons for performing the basic functions of the cal-culator and constants employed by these routines and sub-routines are stored in these portions of ROM 80. An ad-ditional 3,072 sixteen-bit words of RO~ may also be added on pages 1, 3, and 4 in steps of 512 and 1,024 words. This is accomplished by simply inserting plug-in RO~ modules 92 - lOS87~0 into receptacles 94 provided therefor in top panel 90 of the calculator housing as illustrated in Figure 1 by the partially-inserted plug-in ROM
module on the left. As each plug-in ROM module 92 is inserted into one of these receptacles a spring-loaded door 95 at the entrance of the receptacle swings down allowing passage of the plug-in ROM module. Once the plug-in ROM module is fully inserted as illustrated by the plug-in ROM module on the right, a pr~nted circuit terminal board 96 contained within the plug-in ROM module plugs into a mating edge connector mounted inside the calculator.
A handle 98 pivotally mounted at the top end of each plug-in ROM module 92 facilitates removal of the plug-in ROM module once it has been fully inserted into one of the receptacles 94.
Routines and subroutines of basic instructions (and any needed constants) for enabling the calculator to perform many additional functions ; are stored in each plug-in ROM module 92. The user himself may therefore quickly and simply adapt the calculator to perform many additional functions oriented toward his specific needs by simply plugging ROM modules of his own choosing into the calculator. Added plug-in ROM modules are automatically accommodated by the calculator and associated with definable section 91 of : keyboard input unit 12 or employed to expand the functions performed by this and other sections of the keyboard input unit.
Referring again to Figure 3, M-register 82 of the memory unit com-prises a recirculating sixteen-bit serial shift register into which information may be transferred bit-serially from CPU 48 via T-bus 52 and out of which .

:~ -47-' ` ~058760 information may be transferred bit-serially to CPU 48 via S-bus 50. In-formation shifted into M-register 82 may be employed to address any word in RWM 78 or ROM 80 via fifteen output lines 106.
T-register 84 of the memory unit comprises a recirculating six-teen bit serial shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from any ad-dressed word in RWM 78 and ROM 80 via sixteen parallel input lines 108.
Information may be transferred from T-register 104 either bit-serially to CPU 48 via S-bus 50 or in parallel to any addressed word in RWM 78 via sixteen ., .
`; 10 parallel output lines 110. The four least significant bits of information con-. tained in T-register 104 may comprise binary-coded-decimal information and may be transferred from the T-register in parallel to CPU 48 via three parallel output lines 112 taken with S-bus 50.
. The control circuitry 85 of the memory unit controls these transfers .` of information into and out of M-register 82 and T-register 84, controls the ` addressing and accessing of RWM 78 and ROM 80, and refreshes RWM 78. It performs these functions in response to memQry microinstructions, memory clock pulses, and shift clock pulses from CPU 48.
CPU 48 includes a register unit 114, an arithmetic-logic unit 116 (hereinafter referred to as the ALU), a programmable clock 118, and a micro-:i ~
processor 120. Register unit 114 comprises four recirculating sixteen-bit shift registers 122, 124, 126, and 128 and one four-bit shift register 130.
~ Shift registers 122 and 124 serve as sixteen-bit ,`~

:.

' :' :

.

serial accumulator registers (hereinafter referred to as the A-register and the B-register, respectively) into which information may be transferred bit-serially from ALU
116 via T-bus 52 and out of which information may be trans-ferred bit-serially to ALU 116 via g-bus 54. The ~our least significant bit positions of A-register 122 also serve as a four-bit parallel accumulator register into which four bits of binary-coded-decimal information may be transferred in parallel from ALU 116 via four parallel input lines 132 and out of which four bits of binary-coded-decimal informa-tion may also be transferred in parallel to ALU 116 via three parallel output lines 134 taken with ~-bus 54.
Shift register 126 serves as a sixteen-bit system program counter (hereinafter referred to as the P-register) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via ~-bus 54. In-formation contained in the least significant bit position .
of P-register 126 may also be transferred as a qualifier ~j.
control signal QP0 to microprocessor 120 via output line 135.
.: Shift register 128 serves as a sixteen-bit qualifier ` register (hereinafter referred to as the Q-register) into which information may be transferred bit-serially from ALU
. 116 via T-bus 52 and out of which information may be trans-: ferred bit-serially to ALU 116 via ~-bus 54. Information contained in the five least-significant bit positions of Q-register 128 is transferred to I/0 gating control circuitry-58 as five one-bit I/0 qualifier control signals Q00-Q04 via five parallel output lines 136, and information contained in the six next-least-significant bit positions .

105~376~
of the Q-register is transferred to I/0 control 60 as six one-bit I/0 qualifier control signals Q05-Q10 via six parallel output lines 138. Similarly, information contained in the seven least-significant, the ninth and eleventh least-significant, and the most-significant bit positions of Q-register 128 and information derived from the thirteenth, fourteenth, and fifteenth bit positions of the Q-register may be transferred to microprocessor 120 as eleven one-bit microprocessor qualifier control signals Q00-Q06, Q08, Q10, Q15, and QMR via eleven output l~nes 140. Information contained in the twelfth through the fifteenth least-significant bit positions of Q-register 128 may be trans-ferred to microprocessor 120 as a four-bit primary address code via four parallel output lines 142.
Shift register 130 serves as a four-bit serial exténd registe~ (hereinafter referred to as the E-register) into which information may be transferred bit-serially either ;;~
: from ALU 116 via T-bus 52 or from the least-significant . bit position of T-register 84 via input line 144. In-.; 20 formation may also be transferred out of E-register 130 to ALU 116 via ~-bus 54.
Register unit 114 also includes control circuitry . 146 for controlling the transfer of parallel binary-coded-deci~al information into and out of A-register 122 and the transfer of serial binary information into and out o~ A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130. This is accomplished in response to register microinstructions from microprocessor 120, control signals ~T~ and ~TE from I/0 control 60, and shift clock control pulses from programmable clock 118 105876(~
Control circuitry 146 includes a flip-flop 148 (hereinafter referred to as the A/B flip-flop) for enabling the transfer cf information into and out of either the A-register 122 or the B-register 124 as determined by the state of the A/B
flip-flop. The state of A/B flip-flop 148 is initially determined by information Qll transferred to the A/B flip-flop from the twelfth least-significant bit position of Q-register 128 but may be subsequently complemented one or more times by microinstruction CAB from microprocessor 120.
ALU 116 may perform either one-bit serial binary arithmetic on data received from T-register 84 or M-register 82 via ~-bus 50 and/or from any register of register unit 114 via ~-bus 54 or ~our-bit parallel binary-coded-decimal arithmetic on data received from T-register 84 via output lines 112 taken with ~-bus 50 and/or from A-register 122 via output lines 134 taken with R-bus 54.
It may also perform logic operations on data received from memory unit 46 and/or register unit 114 via any of these linesO The arithmetic and logic operations performed are designated by ALU microinstructions from microprocessor 120 and are carried out in response to these microinstructions, shift clock control pulses from programmable clock 118, and control signal SCB from I/0 control 60. Information is also transferred from ALU 116 to A-register 122 via output lines 132 or to I/0 register 56, M-register 82, T-register 84, or any register of register unit 114 via T-bus 52 in response to microinstructions and control signals applied to these registers. If a carry results while ALU 116 is performing either one-bit serial binary arithmetic or four-bit ~arallel binary-coded-decimal arithmetic, the ALU issues a corresponding .~

' quali~ier control signal QBC a~d QDC to microprocessor 120 via ~ne o~ two output lines 152 and 154.
Programmable cloc~ 118 includes a crystal-controlled system clock 156, a cloc~ decoder and generator 158, and a control gate 160. System clock 156 issues regularly re-curring clock pulses to clock decoder and generator 158 via output line 162. In response to these r~gularly recurring clock pulses Irom system clock 156 and to four-bit clock ., , codes irom microprocessor 120, clack decoder and generator 158 issues trains o~ n shi~t clock pulses to AL~ 116, ~-~ register 82, T-register 82, and all o$ the registers o~
~ register unit 114 via o~tput line 164. These trains o~ n shi~t clock pulses are employed for shi~ting a corresponding '. number of bits o~ serial in~ormation i~to or out o~ any of .1 these registers or Ior shifting a carr~ bit in the AL~. The :~ numDer n OI puises in eacn OI ~nese trains may vary from .~ one to si~teen as determined by the number o~ bits of serial ~ information required during each operation to be per~ormed.
. .:
~; In response to a control signal ~F~ ~rom microprocessor 120, `. 20 control gate i60 prevents any shift clock pulses ~rom being~.
applied to the ALU or any o~ these registers. ~pou comp}etion o~ each train o~ n shift clock pulses, clock decoder a~d generator 1~8 issues a R0~ clock pulse to microprocessor 120 via output li~e 166 and an I/0 cloc~ pulse to.I~0 control - ~ 60 ~ia tput line 168. In response to the regularly re- -curring.cloc~ signa} ~rom syst~m clock.56, clock decoder and generator 158 also issues correspondingly regularly recurring memory clock pulses to ~emory unit 46 via output.line 170 . ~icroprocessor 120 selectively issues two I/~
microinstructtons to I/0 control 60 via two output lines 172, six memory microinstructions to memory unit 46 via six output lines 174, thirteen register microinstructions to register unit 114 via thirteen output lines 176, and : five ALU microinstructions to ALU 116 via five output li~es 17~. It also issues a four-bit clock code associated with each of these microinstructions to clock decoder 158 via four output lines 180. These microinstructions and associated ` clock codes are issued as determined by the control signal POP from the power supply, the eleven microprocessor quali-fier control signals ~rom Q-register 128, the ~our-bit primary address codes from Q-register 128, and the five microprocessor qualifier control signals from I/O control , 60, interrupt control 65, ALU 116, and P-register 126.
. As shown in the simplified flow chart of Figure 7, :~, microprocessor 120 executes a hardware diagnostic routine ~ (stored within the microprocessor itself) in response to the ~. control signal POP. Upon completion of this diagnostic .;; routine, ALU 116 issues the qualifier control signal QBC in-: ;.
.. dicating whether or not the diagnostic routine was suc-cessful, microprocessor 120 thereupon responds to this qualifier control signal by entering the basic machine operating loop and issuing microinstructions causing a six-. teen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128.
Microprocessor 120 thereupon sequentially responds to one or more additional qualifier control signals by issuing microinstructions and associated clock codes ~or executing the instruction then contained in Q-register 128 and causing another sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to the :

:
Q-register. When an instruction requiring multiple branching is contained in Q-register 128, microprocessor 120 issues a pair of microinstructions UTR and XTR causing the micro-processor to respond to a four-bit primary address code from the Q-register by issuing additional microinstructions and associated clock codes for executing the instruction contained in the Q-register.
As illustrated by the basic machine operating loop shown in the flow chart of Figure 7, ~icroprocessor 120 x initially responds to the qualifier control signal QNR
either by iæsuing microinstructions and associated clock codes for interrupting the basic machine operating loop and executing an I/0 service routine or by issuing microinstruc-tions and associated clock codes for loading A~B flip-flop 148 with the information Qll contained in Q-register 128.
The manner in which microprocessor 120 responds is deter-mined by the condition of the qualifier control signal QNR, which in turn indicates whether or not the basic machine :
` operating loop should be interrupted.
Assuming the basic machine operating loop is not to : be interrupted, microprocessor 120 loads the in~ormation Qll into A/B flip-flop 148 and responds to the qualifier control signal QMR either by issuing microinstructions for transferring an address portion of the instruction contained in Q-register 128 from T-register 84 into M-register 82 or by responding to another qualifier control signal Q15.
Again, the manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QMR, which in turn indicates whether or not the instruction contained in Q-register 128 is a memory reference instructionO

-~4-;)58760 ; Assuming the instruction contained in Q-register 128 is a memory re~erence instruction, microprocessor 120 transfers the required address in~ormation into the M-register 82 and responds to quali~ier control signal Q10 either by issuing microinstructions and associated clock codes to select the base page o~ the memory (i.e. page 0) ~r by issuing microinstructions a~d associated clock codes to select the cllrrent page of the memory (i.e. the page ~rom which the instruction contained in Q-register 128 was obtained). In either case, the microprocessor then issues microinstructions as required to read data from the preset page of the memory at the address designated by the address in~ormation last transferred into ~-register 82. Upon completion of this operation, microprocessor i20 responds to qualifier control signal QlS by issuing additional micro-instructions and associated clock codes to execute an in-direct memory access operation if the condition of this qualifier control signal indicates that the address informa-tion contained in M-register 82 is indirect.
Assuming the address in~ormation contained in ~-register 82 is direct (or upon completion o~ the indirect memory access operation), microprocessor 120 issues micro-instructions a~d associated clock codes causing the micro-processor itself to respond to a four-bit prlmary address code ~rom the Q-register. The microprocessor responds by issuing additional microinstructions and associated - cloc~ codes for executing ~hichever one of ten possible memory reference lnstructions ~s contai~ed in Q-register 128 and designated by the four-bit primary address code.
Following execution of the designated memory reference .

.

~ 1058760 j ,1 instruction, microprocessor 120 issues microinstructions and associated clock codes causing another sixteen-bit instruction . stored in ROM 80 to be loaded into T-register 84 and trans-ferred from there to Q-register 128 thereby beginning another . cycle of the basic machine operating loop.
.,' .. As illustrated by other possible paths of the basic ;` machine operating loop shown in Figure 7, microprocessor 120 sequentially responds to other qualifier control signals .
when other types of instructions are contained in Q-register `. 10 128. For example, when an I/O instruction is contained in Q-register 128, microprocessor 120 sequentially responds to quallfier control signals QNR, QMR, Q15, Q10, and QRD by issuing microinstructions and associated clock codes to execute the I/O instruction. It should be noted that the .: microprocessor qualifier control signals not shown in the ; simplified flow chart of Figure 7 are variously contained within those flow chart blocks requiring decisions as will hereinai'ter become apparent.

.

:: .

XEY OPER~TIONS
All operations performed by the calculator may be controlled or initiated by the keyboard input unit and/or by keycodes entered into the calculator ~rom the keyboard ~nput unit, the magnetic card reading and recording unit, or peripheral input units such as the mar~ed card reader and stored as program steps in the program storage section of the RWM. The calculator responds to keycodes in basically the same manner whether obtaining them ~rom the keyboard , .
input unit or from the program storage section o~ the R~.
An operational description o~ the keyboard input unit is therefore now given with specific re~erence to Figures 1 and 8 ' except as otherwise indicated.
!~, Line Switch y An o~-o~ e switch 182, which may be considered as part o~ the keyboard input unit, controls the applica-tion o~ power to the calculator and hence initiation o~ the control signal POP ~rom the power supply. The ~ndicator ~` lights 19 serve as a pilot light s~nce at least two o~ themare always turned on while power is applied to the cal-culator.
~s show~ i~ Figure 2, the calculator may be operated at 230, 200, 115, or 100 volts t 10% as determined by a pair o~ e voltage selector switches mounted at rear panel 34 o~ the calculator housing and at a line ~requency within the range o~ 48 to 66 Hertz. The calculator is provided with a ~-amp fuse and either a l-amp fuse for operation at a line voltage of 200 or 230 volts ~ lOZ or a 2-amp fuse or opera-tion at a line voltage of 100 or 115 volts 1 10%. It is .
'` 30 3150 provided with a three-conductor power cable 184 which, .
-~7-~ ~058760 :
~
when plugged into an appropriate AC power outlet, grounds the calculator housing. The maximum power consumption of the calculator is 150 voltamps. No more than a total of 610 voltamps may be drawn from AC power outlets 42 pro-vided for peripheral units 28.
- Mode Keys (RUN, PRGM KEY LOG) When the calculator is first turned on, it is automatically initialized and placed in a manual operating mode. If the calculator is switched to some other opera-ting mode, it may subsequently be placed in the manual operating mode again by simply depressing the RUN mode key.
In the manual operating mode, operation of the calculator is manually controlled by the user from the keyboard input unit. During this mode the output display unit displays a decimal numeric representation of the contents of the x-, y-, and z-registers (or of associated memory registers in which the actual or intended contents oi' the x-, y-, and z-registers are temporarily stored and, for simplicity of description, are then considered to be the contents of the x-, y-, and z-registers). The contents of the x-, y-, and z-registers are displayed ad;acent to the corresponding register designators "keyboard x","accumulator y", and ~` "temporary z", respectively, in the display window. De-., `` pression of the RUN mode key also conditions the calculator for operation in an automatic operating mode, a first key-log printing mode~ a program-list printing mode, a magnetic card reading mode, and a magnetic card recording mode as determined by other keys hereinafter explained. A run in-` dicator light 19 positioned immediately below the RUN mode key is turned on when the calculator is operating in any :

, .

~5876~) of the RUN modes.
The PRGM mode key is depressed to place the cal-culator in a program entering mode. In this mode keycodes se~uentially entered by the user ~rom the keyboard ~nput r unit axe stored as program steps in successive program-. .
step registers o~ the program storage section o~ the RUM as speci~ied by the user program counter. As described above, 500 program-step registers (user addresses 0000-0499) are ava~lable, and 1536 additional program-step registers (user ,, addresses (0500-2035) may be made a~ailable, to the user ~or this purpose. The program step register into which each program step is to be stored and from wh~ch each program step is to be obtained in any progra~-related operat~on is always speci~ied by the user program counter. Thus, be~ore entering a program or subprogram into the calculator, the x~ user progra~ counter must be set to the address o~ the pro-gram step register into which it is desired to store the { initial program step of the program or subprogram to be ~ntered (this address is hereinafter re~erred to as the de-sired starting address nnnn of the program). This may be ac-complished, when the calculator is in a keyboard-controlled run mode, by depress~ng the GO TO key ~ollowed by the decimal-digit keys 0-9 speci~ying the desired start~ng address nnnn .
o~ the program. I~ the desired starting address is 0000, this may also be accomplished, when the calculator is in the ~anual operating mode by simply depressing the EN~
key.
;~, .
Once the user program counter is set to the desired starting address Dnnn, the user may proceed to enter the pro-gram or su~program by sequentially per~orming basically the . ..

~OS876~) . .
same key operations that he would normally perform in the ; manual operating mode. Thus no special language need belearned to program the calculator. During the program entering mode the output display unit displays a decimal numeric representation of the last-entered program step and its associated address and the addresses of the next two program steps to be entered and the present contents of those addresses.
Depression of the PR&M mode key also conditions the calculator for operation in a second key-log printing mode and the program-list printing mode as determined by other keys hereinafter explained. A program mode indicator light 19 positioned immediately below the PRGM mode key is turned on when the calculator is operating in any of the PRGM
modes.
The KEY LOG mode key is depressed, when the cal-culator is in the manual operating mode, to place the cal-~ culator in the first key-log printing mode. In this mode, .,~
the output printer unit prints out an octal numeric repre-sentation of each keyboard operation as it is performed by the user. This provides a permanent record of all keyboard operations (including regular data print-out operations)~
as illustrated by the following example:
\
Keyboard entry Key log : 2 02 ~ 27 7 ; 3 03 `~ ~058760 Keyboard entry (Cont'd) Key log (Cont'd) ~ 4 04 + 33 PRINT

5.00000 If the alpha ROM module enabling the calculator to print out every alphabetic character and many symbols indivi-dually or in messages is plugged into the calculator, the ;
`. output printer unit also prints out a mnemonic represen-:~ tation o~ each keyboard operation as it is performed by .:~
the user. This is illustrated by the following example:
;..................... Keyboard entry Key log ' ~ UP 27 . .
.~ 3 3 03 t 4 4 04 + + 33 ~ 05 . DIV 35 PRl~l PNT 45 5.00000 In the first key-log printing mode the output display unit displays the same information as during the manual operating mode.
The ~EY LOG mode ~ey is depressed, when the cal-culator is in the program entering mode, to place the calculator in the second key-log printing mode. In this ~058760 mode the output printer unit prints out an octal numeric representation of each keycode as it is entered into the calcula$or from the keyboard input unit and a decimal numeric representation of the address at which each such keycode is stored as a program step in the program storage section of the RWM. This provides a permanent record of all keyboard-entered program steps, as illustrated by the following example:
Keyboard entry Key log ., .

: 2 0002 --------- 02

3 0004 --~ --- 03

4 0005 --------- 04 . , .
c + 0006 --------- 33 0007 --------- 05.
x~y 0008 --------_ 30 ` ~FDF~ 0009------______ ~; 20 STOP 0010 --------- 41 If the alpha RON module is plugged into the calculator, the output printer unit also prints out a mnemonic representa-: tion of each keyboard-entered program step. This is illus-trated by the following example:
: Keyboard entry Key log CL~AR 0000-- CLR --- 20 ~ 0003-- UP --- 27 llD58760 Keyboard entry (Cont'd) Key log (Cont'd) + 0006-- + --- 33 x~y 0008----XEY-----30 END OOll-- END --- 46 In the second key-log printing mode the output display unit displays the same information as during the program entering mode.
The KEY LOG mode key is a toggling on-off key (i.e.
3 repeated depressions of the key alternately switch the calculator in and out of either the first or the second key-log printing mode). A key-log indicator light 19 `~ positioned immediately below the KEY LOG mode key is turned on when the calculator is operating in either key-log printing modeO
Program Keys (LIST LOAD RECORD) .~ .
The LIST program key is depressed, when the cal-culator is in the manual operating mode, first key-log print-ing mode, second key-log printing mode,or program entering mode, to place the calculator in the program-list printing mode. In this mode, the output printer unit prints out an octal numeric representation of keycodes then stored as program steps in the program storage section of the RWM and a decimal numeric representation of the addresses of these program steps. These program steps and addresses are printed out in a list beginning with the address initially . . .

~05876~

specified by the user program counter and ending with the address specified by the user program counter when an E~D
program step is encountered or the STOP key is depressed.
The user may select the starting address nnnn of the list by depressing the GO TO key followed by the decimal digit keys (0-9) designating the desired starting address nnnn, or simply by depressing the END key if the starting address is OOOO. Similarily, the user may terminate the list at any time by depressing the ~TOP key. When the program-list :
operation is terminated either by an END program step or by depression of the STQP key, the calculator reverts to its original manual operating, first or second key-log printing, or program entering mode. I~ the program-list operation is terminated by an END program step, the user program counter specifies the address of the END program step. However, if the program-list operation is terminated by depression of the STOP key, the user program counter specifies the address .~
of the next program step to have been encountered had the ~TOP key not been depressed.
2G The list pr~nted out by the output printer unit serves as a permanent record of a sequence of program steps stored as a program, subprogram, or part thereo~ in the program ,~
storage section of the RWM and the address of these program steps. A typical list is illustrated by the right- and left-hand columns of numbers printed out on the strip of thermal-sensitive recording paper 22. If the alpha RO~ module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each of these program steps. This is illustrated by the central column of alpha-meric characters printed out on the same strip of thermal-sensitive recording paper.

--- lOS87~;~
The LOAD program key is depressed, when the cal-culator is in the manual operating moda or the ~irst key log printing mode, to place the calculator ~n the magnetic ., .
card reading mode. During this mode, progræm steps re-corded on one or more external mag~etic cards 16 are read by the magnetic card reading and recording unit and stored in the program storage section of the RW~. In order to properly accomplish this program loadin~ operation:
1. The user program counter is set to the desired starting address nnnn of the program storage section to be loaded. This ma~ be accomplished b~ depressing the GO T0 key ~ollowed by those decimal degit keys designating the desired starting address nnnn,or simply by depressing the END key if the desired starting address is 0000.
2. ~ recorded magnetic card 16 inserted i~to an input receptacle 186 o~ the magnetic card reading and re- -cord~g ~nit with the ~irst side 187 to be read placed i~
the ~perati~e reading and recording position as shown in Figure 1.
3. The LOAD key is depressed, thereby causing t~e magnet~c card reading and recording unit to ~egin reading the ~irst recorded side of the magnetic card and turning on an INSERT CARD indicator light 19 positioned immediately below and between the ~OAD and RECORD program ~eys. This program reading operation will terminate a~d the INSERT
CARD i~dicator light will turn off when an E~D (i.e. terminating) program step is read~ The calculator will thereupon revert to the original manual operating or ~irst key-log printing mode with the user program counter speci~yi~g the address of the END program step. In any case, the magnetic card ~5876V
:i will be partially ejected at an output receptacle 188 of -~ the magnetic card reading and recording unit after each reading pass has been completed.
4. If the INSERT CARD indicator light remains on `~ and the magnetic card reading and recording unlt continues to run, the partially ejected magnetic card is retrieved ~3 from output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into input receptacle 186 with the next side 189 to be read placed in the operative reading and recording position. The magnetic card reading and recording unit thereupon begins reading this next recorded side. This program reading operation is repeated, if necessary, until - it is terminated by reading an END program step. If desired, program reading operation may also be terminated by depressing the STOP key. The calculator will thereupon also revert to the original manual operating or first key-log printing mode, but with the user program counter specifying the address of the ne~t program step to have been read and loaded into the program storage section of the RWM had the program reading operation not been so termi-nated.
When the program reading operation is terminated by an END program step, the user program counter is le~t speci-fying the address of this END program step so that additional program steps, subprograms, and pro B ams may be chain-loaded into the calculator without extra effort by simply repeating steps 2, 3, and 4 above. The first additional program step will over-write the last encountered END program step there-by leaving only a final END program step at the completion of the composite program. Similarly, when the program reading operation is terminated by depressing the STOP key, the user program counter is also left specifying the address of the next program step to have been read so that ad~
ditional program steps, subprograms, and programs may also be chain-loaded by simply repeating steps 2, 3, and 4 above.
The RECORD program key is depressed, when the ` calculator is in the manual operating mode or the first key-log printing mode, to place the calculator in the magnetic card recording mode. During this mode program steps stored in the program storage section of the RWM
are recorded on one or more external magnetic cards by the magnetic card reading and recording unit. In order to properly accomplish this program recording operation:
- 1. The user program counter is set to the starting i address nnnn oflthe stored program to be recorded. This may be accomplished by depressing the GO TO key followed by the decimal digit keys designating the required address nnnn, or simply by depressing the END key if the starting address is 0000.
2 A magnetic card 16 is inserted into input re-ceptacle 186 of the magnetic card reading and recording unit ~ith the first side 187 of the card to be recorded placed in the opera~ive reading and recording position as shownO
3. The RECORD program key is depressed, thereby causing the magnetic card reading and recording unit to be-gin recording the stored program o~to the first side of the magnetic card and turning on the INSERT CARD indicator light 19. This program recording operation will terminate and the INSERT CARD indicator light turn off when an END

~. .

1~58760 program step is recorded. The calculator will thereupon revert to the original manual operating or first key-log printing mode with the user program counter speci~ying the address of the END program step. In any case, the magnetic card will be partially ejected at output receptacle 188 o~
the magnetic card reading and recording unit a~ter each recording pass has been completed.
4. I~ the INSERT CM D indicator light remain9 on, and the magnetic card reading and recording unit continues to run, the partially e~ected card is retrieved ~rom output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into i~put receptacle 186 ~ith the next side 189 to be recorded ; placed in the operati~e reading and recording position.
` The magnetic card reading and recording unit thereupon be-gins recording on this next side. This program recording operation is repeated, i~ necessary, until it is terminated by recording an E~D program step. If no END program step i9 encountered, the calculator will continue to request 20- more magnetic card recording passes until 2,036 program steps are recorded, regardless of the actual amount of pro-gram storage memory installed in the calculator. I~ de-sired, the recording operation can be terminated at any time by depressing the STOP key. The calculator will there-upon also revert to the original manual operating or first key-log printing mode but with the user program counter left speci~ying the address of the next program step to haYe been recorded had the recording operation not been so termi-i nated.
3~ Once the progr~m is recorded on one or both sides , .

~o5876 of one or more magnetic cards 16, it may be protected against undesired erasures by punching out a perforated portion l90 at the leading edge of each side on which it is recorded If a protected (notched) magnetic card is inserted into input receptacle 186 of the magnetic card reading and re-cording unit and the RECORD key depressed, the STATUS
.1 (error) indicator light l9 will turn on and will remain on while the magnetic card reading and recording unit drives the magnetic card to output receptacle 188, whereupon the STATUS light will be extinguished~ Nothing will be recorded on the protected magnetic card during this recording pass nor will there be any impairment of the calculator itself or the information previously recorded on the protected magnetic card. The calculator and the magnetic card unit will simply continue to wait for a nonprotected magnetic card to be inserted into input receptacle 186 for the mag-` netic card reading and recording unit.
Automatic Operating Mode Control Keys (CONTINUE STOP~ END, PAUSE) The CONTINUE key is depressed, when the calculator is in the manual operating mode or the first key-log printing ` mode, to start the automatic execution of a program or sub-program stored ~ithin the program storage section of the ` RWM. ~utomatic execution begins at the address specified by the user program counter. Thus, in order to execute a desired program or subprogram stored within the program storage section of the RWM;
`~ 1. The user program counter is set to the starting address nnnn of the desired program or subprogram. This is accomplished by depressing the GO TO key followed by those decimal digit keys designating the starting address ; ~

~ -69-~C~58760 :' nnnn of the desired programO If the starting address is 0000, this may be accomplished by simply depressing the : END keyO
2. The CONTINUE key is depressed, when the cal-culator is in the manual operating mode or the ~irst key-; log printing mode, to place the calculator in the automatic operating mode and begin automatic execution of the stored program or subprogram at the address nnnn specified by the ` user program counter. Automatic execution will continue until a STOP or END program step is encountered or a STOP
key is depressed as described below.
The STOP key is depressed, when the calculator is in the automatic operating mode, to halt the automatic execution of a stored program or subprogram immediately after completion of the program step then being executed.
Automatic execution of a stored program or subprogram is similarly halted when a STOP program step is encountered.
In either case the calculator will thereupon revert to the original manual operating or first key-log printing 20 ~ mode with the program counter specifying the address of the next program step to be encountered. The user may ; then operate the calculator in the manual operating mode to enter data required by the program being executed or to i.
perform other calculations. So long as the user does not depress the GO TO or END key or perform some other opera-tion altering the last setting of the user program counter, he may resume automatic operation of the calculator at any time by simply depressing the CONTINUE key again.
As described above, the STOP key may also be de-pressed, when the calculator is in the program-list printing ':

.;.' ~ -; .

-- ` 1 [358760 mode, the magnetic card reading mode, or the magnetic card recording mode to halt the program-list printing operation, the magnetic card reading operation or the magnetic card recording operations, respectively. In each o~ these cases the calculator will revert to the mode it was in immediately prior to the halted operation with the user prvgram counter speci~ying the address o~ the next program step to have been printed, read, or recorded had the STOP key not been depressed.
The END key is depressed, when the calculator is in the manual operating mode, to set the user program counter to address oOoo in the program storage .! section of the RWM (this is e~uivalent to depressin~
the GO T0, o, o, o, and o keys). An E~D program step terminates the automatic execution of a stored program by the calculator and resets the user program counter to the ~irst a~ailable address 0000 in the program storage section of the RW~. The calculator thereupon reverts to xi the original manual operating or first key-log printing mode, from which automatic operation was initiated. Auto-matic execution may then be resumed by depressing the ii CO~TINUE key, if the desired starting address is 0000 or by repeati~g steps 1 apd 2 described above i~ connection wlth the CONTINUE key lf the desired starting address is not 0000. An END program step also clears any subroutine return-address to which return has not by then been made.
As described above, it also terminates the program listing, magnetic card ~eading, and magnetic card recording opera-tions.
The PAUSE key is typically used only as a program . . .

:, ~ [358~;~60 step. Automatic execut~ion OI a stored program or sub-program is automatically halted for a 1/4 second pause i~ter~al whenever a PAUSE program step is encou~tered or the PAUSE key is depressed. This enables partial results ; o~ a calculation to be displayed by the output display unit during automatic execution of the stored program or subprogram. ~uccessive PAUSE program steps may be employed to increase the duration of the pause interval by 1/4 second increments. Automatic execution o~ the stored pro-gram or subprogram automatically resumes after the pause ; interval.
A PAUSE program step may also be used as a con-dit~onal stop permitti~g the user to sto~ the automatic operation o~ the calculator immediately after execution of any PA~SE program step. This is accomplished by simply depressing any key (other than STOP) during automatic execution of the program until the P~USE program step has been executed. In other words, a PAUSE program step im--~ mediately followed by depression of any key other than STOP
has the same e~ect as depresstng STOP, with the ad~antage that automatic execution o~ a stored program or subprogram may thereby be precisely halted at one or more predetermined program steps if the user so desires. Automatic execution of the stored program may then be resumed by depressing the CONTI~UE key.
Decimal Display Keys (F~OAT, FI~ () ) These keys are employed to control the format of ~umbers displayèd by the output display unit when the caI-culator is in the manual operating a~d first key-log printing ; 30 modes. Either a fixed or a ~loating decimal point ~ormat .. :

~0587~;0 may be used. A fixed point indicator light 19 positioned immediately below the FIX () key is turned on when the fixed decimal point format is being used. Similarly, a floating point indicator light positioned immediately below the FLOAT key is turned on when the floating decimal point format is being used.
In the fixed decimal point format, numbers appear in the form in which they are most commonly written. The decimal point is fixed in its correct position. In the floating decimal point format, numbers appear in a normalized form with the decimal point located immediately after the most significant non-zero digit of the normalized number.
Each normalized number is followed by an exponent comprising a positive or negative power of ten and representing the number of digit places that, and the direction in which, the decimal point must be moved to express the normalized number in the fixed decimal point formatO The following ~ examples illustrate the relationship between numbers ex--3 pressed in both the fixed and floating decimal point for-mats.
~: FIXED DECIMAL FLOATING ~ECIMAL
POINT FORMAT POINT FORMAT
1234.5 =1.2345 x 103 0 0012345 =1.2345 x 10-3 -1.2345 =-1.2345 x 10 When the calculator is turned on and automatically initialized, the output display unit displays numbers in the floating decimal point format. If the output display is switched to the fixed decimal point format, it may subsequently be switched back to the floating decimal point format by simply depressing the FLOAT key. Every :' 10587~;0 number displayed in the floating decimal point format in-cludes the sign (if negative) and ten most significant digits of the normalized number followed by the sign (if negative) of the exponent and two exponent digits. This is illustrated by the following examples:

NUMBERS TOFLOATING DECIMAL
BE DISPLAYED POINT DISPLAY

1234.5 1.234500000 03 0.00123~5 1.234500000 -03 ; 10 -1.2345 -1.234500000 00 The output display may be changed to the fixed decimal point format by depressing the FIX () key followed by a decimal digit key designating the desired number n (0-9) of digits to be displayed to the right of the decimal point. Less significant digits are not displayed, and the ' least significant digit to be displayed is rounded up if the j nondisplayed next least significant digit is fi~e or greater.
`~' This is illustrated by the following examples for different values of n:

NUMBERS TO VALUES FIXED DECIMAL
BE DISPLAYED OF n POINT DISPLAY

` 123.4567~4 2 123.46 y -6.703256 2 -6.70 123.456784 5 123O45678 -6.703256 5 -6.70326 ; 123.456784 0 123.

... .
-6.703256 0 -7.

If the FIX () key is depressed but not followed by a decimal - digit key, the calculator will automatically treat the next key depressed as being the O key (i.e. n will thereupon equal O as in the last example), 1~587~;0 Numbers of up to (and including) ten significant digits and their signs (if negative) may be displayed in the fixed decimal point format. Thus, (10-n) digits may be displayed to the left of the decimal point. If a number to be displayed has more than (10-n) digits to the left of the decimal point (i.e. is too large for the selected value of n), the display of that number (not the whole display) overflows and thereupon reverts to the floating decimal point format. This is illustrated by the fixed ~ 10 decimal point display of Figure 1 wherein the numbers con-`~ tained in the x and Y registers have overflowed and are i~
therefore displayed in the floating decimal point format.
It is also illustrated by the following example:
NUMBER TO VALUE ACTUAL
BE DISPLAYED OF n NUMBER DISPLAYED
1234567.89 5 1.23456789 06 If the first non-zero digit of a number to be displayed is more than n digits to the right of the decimal point (i.eO
i~ is too small for the selected value of n), the display of that number (not the whole display) underflows. In this case only zeros will be displayed. This is illustrated by the following example:
NUMBER TO VALUEACTUAL
BE DISPLAYED OF nNUMBER DISPLAYED
. . .
0.0000012 3 0.OOO
Regardless of the way in which numbers are displayed, the calculator always stores all numbers and performs all cal~-ulations in the floating decimal point format. Further-more, regardless of the number of digits entered or displayed, each number is stored with twelve significant digits, their 58~60 associated sign, a two-digit exponent, and its associated sign. Up to (and including) ten significant digits, their associated sign, the two-digit exponent, and its associated sign can be displayed (however, no sign is displayed for positive numbers or exponents). The remaining two digits (called guard digits) are not displayed. They are employed to maintain greater than ten-place accuracy during cal-culations and also to automatically round the tenth dis-played digit.
The calculator has a dynamic range of from +10 98 to +9.999999999(99) x 1098. Whenever this range is ex-ceeded during a calculation the STATUS indicator light 19 turns on.
'A Numeric Data Entry Keys (0-9), ., ENTER EXP, CHG SIGN, ~) i The decimal digit keys 0-9 are depressed to enter ~; numbers into the x-register. Numbers are entered serially, the last digit entered becoming the least significant digit.
For example, the number 1325 is entered by sequentially depressing the decimal digit keys 1, 3, 2, and 5. A number ~ 20 entered into the x-register is terminated as soon as any - non-data-entry key is depressed. Another number entered i into the x-register will automatically replace a terminated number, but will become a part of any non-terminated number.
The decimal point (.) key is depressed to enter the decimal point into the x-register. For example, the number 1.234 is entered by sequentially depressing the 1, ., 2, 3, and 4 keys. Regardless of the display format, it is not necessary to use the decimal point key when entering integers.
If the decimal point key is not used, the decimal point will be assumed to have followed the last-entered digit. When , the ~ixed decimal point display format is used, the cal-culator automatically positions the decimal point, Simi-larly, when the ~loating decimal point display format is used the calculator automatically corrects the exponent according to the position of the decimal point.
The ENTER EgP key is depressed ~ollowed by one or two decimal digit keys to enter a one- or two-digit .~
exponent (power o~ ten) into the x-register, the last digit entered becoming the least signi~icant digit. I~ a third digit is entered, it will terminate entry o~ the exponent and begin a new numeric data entry. A non-terminated number in the x-register may be multiplied directly by successive powers o~ ten by simply entering successive e~-ponents For example, the product of 8.3 x 102 x 1014 may be obtained by sequentially depressing the 8, ., 3, ENTER
.: ~
EXP, 2,ENT~R ~P, 1, and 4 keys. I~ the ENTER E~P key is depressed as the first key o~ a numeric data entry (i.e.
before any of the decimal digit keys have been depressed or following a terminated number),the number 1 is entered into the x-register. For example, the number 1 ~ 1016 may be entered by depressing the ENTER EXP, 1, and 6 keys.
T~e CEG SIGN key is depressed to change the sign o~ any terminated or u~terminated number in the x-register.
If the CHG SIGN key is depressed as the first key o~ a numeric data entry, it changes the sign of the number then in the x-register ~whatever the sig~ may be) and, once that number is replaced b~ the ~irst digit o~ the ne~ data entry, it pre~ces the new data entry with a negati~e sign.
This is illustrated by the ~ollowing example:

.~

1~58'76V

KEYS DEPRESSI;DCONTENTS OF x-REGISTER
-123.45 6 -6.
7 -67.
The CHG SIGN key is also depressed immediately followin~ the ENTER EXP key (or the last-entered digit of the exponent) to enter negative exponents into the x-` register For example, the number 8.3 x 10 2 x 104 x 10 may be entered by sequentially depressing the keys 8, 3, ENTER EXP, CHG SIGN, ~, ENTER EXP, 4, ENTER EXP, CHG
SIGN, 1, and 2 keys and the number 1 x 10 16 may be ` entered by depressing the ENTER EXP, 1, 6, and CHG SIGN
keys.
The tt key. is depressed to enter the value of (i.e. 3.14159265360) into the x-register.
Clear keys (CLEAR x, CLEM) The CLEAR x key clears (i.e. sets to zero) the x-register. It does not affect any other registersO
The CLEAR key clears the x-, y-, and z~ (working) registers, clears the a- and b- (data storage) registers, and clears (or resets) the Ilag, which can be set by the SET FLAG key as hereinafter e~plained. It does not affect any other registersO
When the calculator is switched on, all of the working, program, and data storage registers of the RWM are automatically cleared. Any terminated numbers subsequently stored in them will automatically be cleared and replaced by any new data entry.

i ~`

.. .. . .
.

Working Register Control Keys (t, l, ROLL ~, x~y) The working register control keys are used to re-position the contents of the x-, y-, and z-registers. They do not affect any other registers.
When the ~ key is depressed, the contents of the y-register shift to the z-register and the contents of the ~ x-register appear in both the x- and y-registers. The `~ contents of the z-register are lost.
When the ~ key is depressed, the contents of the y-register shift to the x-register and the contents of the r z-register appear in both the y- and z-registers The contents of the x-register are lost.
When the ROLL ~ key is depressed, the contents of the x-register shift to the y-register, the contents of the y-register shift to the z-register, and the contents of the z-register shift to the x-register. No information is lost.
` The x~y key is depressed to exchange the contents of the x- and y-registers. The contents of the z-register are unaffected by this operation.
Arithmetic Keys ~+, -. x` :) _ _ _ _ _ These four keys are used to perform working re-gister arithmetic operations in which the contents of the x- and y-registers are employed as operands. The results of these arithmetic operations are stored in the y-register and the contents of the x-register remain unchanged by the arithmetic operations performed. These four ke~s do not ~ affect any other registers.
J The + key is depressed to add the number in the ` x-register to the number in the y-register, the sum appearing in the y-register.

~: , - .

1058~760 The - key is depressed to subtract the number in the x-register from the number in the y-register, the dif-ference appearing in the y-register.
The x key is depressed to multiply the number in the y-register by the number in the x-register, the pro-duct appearing in the y-register.
The ~ key is depressed to divide the number in the y-register by the number in the x-register, the quotient appearing in the y-register.

, .
The use of these keys and the working register control keys is illustrated by the following method of ::!
computing (3 x(48)x~2)8 69) = 1.1 :

' CONTENTS OF CONTENTS OF CONTENTS OF
KEYS DEPRESSED x-REGISTER y-REGISTER z-REGISTER

CLEAR o o O

~ 3 3 0 ; 4 4 3 o ROLL ~ 0 4 12 ` x~y 4 8 12 ` 9 9 8 12 ~ 9 -1 12 ~ -1 12 12 + -1 11 12 ROLL~ 12 -1 11 ` 8 8 -1 11 x~y -1 8 11 , .

lOS~76Q
(Computing continued) ~ - 6 10 11 `' ~ 10 11 11 `', . 10 1. 1 11 The answer, appearing in the y-register, is underlined.
Unary Function Keys ( ~ x2 l/x, int x CHG SIGN) These five keys are used to perform unary functions in which the contents of the x-register are employed as the argument. The results of the unary functions performed are placed in the x-register. These five keys do not affect any other registers.
The ~ key is depressed to calculate the square root of the number in the x-register. If the number is negative, the square root of its absolute value is cal-culated and the STATUS indicator light 19 turned on. The STATUS indicator light remains on until the next key is depressed.
The x2 key is depressed to calculate the square o~
the number in the x-register. If the number is greater than ~ 10 9, the number 9.99999999999 x 1098 is placed in the x-register and the STATUS indicator light 19 turned onO The STATUS indicator light remains on until the next key is depressed.
.
The l/x key is depressed to calculate the reciprocal .
`~ of the number in the x-register. For example, 1/9.8 may ; be calculated by sequentially depressing the 9, ., 8, and ` l/x keys.
The int x key is depressed to truncate the fractional ' - .

1~58760 .
part of the number in the x-register. It does not affect the sign o~ the integer part of the number. For example, if the number -5.9 is contained in the x-register when the int x key is depressed, the number -5.0 will remain.
;~ The CHG SIGN key has already been described above in connection with the numeric data entry keys.
~ Data-Storage and Register-Transfer Keys (a, b, x)(), y~(), x-(), i y~(~ INDIRECT) :, ~
These keys are variously used to perform direct data storage and recall, direct storage-register arithmetic, in-direct data storage and recall, and indirect storage-register arithmetic operations. As illustrated below, the a and b ` keys are depressed following any of the remaining five keys of this group to specify the a- and b-registers, respectively.
The a and b keys may also be used to directly recall the contents of the a- and b-registers, respectively, to the x-register without changing the contents of the a- and b-registers themselves. Either of these functions of the a and b keys may be performed in response to a single key-stroke thereof. For example, the contents of the b-register may be directly recalled to the x-register by simply de-pressing the b key alone. As noted above the contents of ; the b-register itself will remain unchanged by this recall `.i operation.
.~
"! The x~(), y~(), x-(), andy~l~keys are used to control the transfer of numeric data from the x- and y-registers to the a- and b-registers and 49 additional storage registers available to the user (at user addresses 000-048) in the data storage section of the RWM and from these storage registers to the x- and y-registers. If the 60 optional storage re-gisters included in the data storage section of the RWM

lOS8760 (at user addresses 049-108) are made available to the user, these same four keys may also be used to control the trans-fer of numeric data from the x- and y-registers to these optional storage registers and from them to the x- and y-registers.
The specific storage register to or from which numeric data is transferred by these four keys is specified by the key or keys depressed immediately following them.
Accordingly, the a key is used to specify the a-register, the b key to specify the b-register, and the decimal digit keys 0-9 to selectively specify any of the available storage registers at user addresses 000-108 of the data storage section of the RWM. For simplicity of description, the available storage registers at user addresses 000-108 will hereinafter be referred to by their addresses (i.e.
the storage register at any available address nnn will be referred to as register nnn). If a non-existant or non-available storage register is designated, the STATUS in-dicator light is turned on, no data transfer or arithmetic operation is performed, and the operation o~ the calculator halts. (If such a register is designated while the cal-culator is automatically executing a stored program, the program-counter specifies the program step immediately following the improper operation.) The x-)() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the x-register in the a-register, the b-register, or register nnn respectively. In any case, the contents of the x-register remain unchanged by this opera-tion. For example, ~ may be stored directly in the b register by sequentially depressing the ~, x~(), and b keys. Similarly, ~ may be stored directly in register 027, by sequentially depressing the ~, x~(), 0, 2, and 7 keys.
In each of these examples, ~ will also remain in the x-register.
The y~() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the y-register in the a-register, the b-register, or register nnn,respectively. In any case, the contents of the y-register remain unchanged by this opera-tion. For example, a number contained in the y-register may be stored directly in register 000, without changing the contents of the y-register, by sequentially depressing the y~(), 0, 0, and 0 keys.
The x-() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to directly re-call the contents of the a-register, the b-register, or register nnn, respectively, to the x-register. In any ,:
case, the contents of the recalled register remain unchanged by this operation. For example, the contents of register 012 may be recalled to the x-register, without changing ~-~ the contents of register 012, by sequentially depressing the x-(), 0, 1, and 2 keys. Recall from the a- or b-register to the x-register may be accomplished in the same manner as described above, by simply depressing the a or b key aloneO
The Ytl) key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to exchange the con-: tents of the y-register with the contents of the a-register, the b-register, or register nnn, respectivelyO For example, a number in the y-register may be exchanged with a number l~S876~

in register 048 by depressing the yfo, O, 4, and 8 keys.
The direct storage and recall operations per~ormed by the x~(), y~(), x (), and y~() keys may be conveniently summarized by employing the following notation:

~IIA~lj In this notation each pair of braces implies that any one ; 10 of the enclosed group of key operations or storage registers may be selected. The order of the successive pairs of braces from left to right specifies the key-sequence re-j quired to perform the selected key operation with the ~ selected storage register. Thus, any of the key operations < enclosed in the left-hand pair of braces may be employed ~, with any of the storage registers enclosed in the right-hand pair of braces by first depressing the key performing the selected key operation and then depressing the key or keys designating the selected storage register. The usefull-ness of these direct storage and recall operations is il-lustrated by the ~ollowing method of multiplying a series `~ of num~ers nl, n2, etc. by a constant K, where nl = 3 ~ n2 ~ 11.2, etc. and K = 1.684:
i KEYS CONTENTS OF CONTENTS OF CONTENTS OF
: DEPRESSED x-REGISTER y-REGISTER a-REGISTER
_,_ CLEAR o o O
1, O, 6, 8, 4, 1.684 0 0 y~, a 1.684 0 1.684 3 3 1,684 ; 30 ~ 3 3 1,684 ~05876~

` (Illustration continued) a 1.684 3 1.684 X 1.684 5.0520 1.684 1, 1, ., 2 11.2 500520 1.684 11.2 11.2 1.684 . a 1.684 11.2 1.684 X 1.684 18.8608 1.684 . ..
The answers, appearing in the y-register, are underlinedO
The x~(), y~(), x~(), and y~) keys may also be em-ployed with the ~, -, x, and . arithmetic keys to perform ` direct register-arithmetic operations in which the con-~s tents of the x-register or the y-register are employed as .. l one operand and the contents of the a-register, the b-register, or register nnn are employed as the other operand.
s. These direct register-arithmetic operations may be sum-marized as follows by using the above-described notation:

~ b ~
Thus, the x~() key may be employed to directly per-form any of the arithmetic operations enclosed by the second : pair of braces upon the contents of the x-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the selected storage register without recalling the contents of the selected storage register and without changing the contents of the x-register. For example, the contents of the x-register may be subtracted from the contents of the b-register by sequentially depressing the x-)(), -, and b keys.

1~51!3760 The difference is stored in the b-register, and the contents of the x-register remain unchanged by the operation. Simi-larly, the contents of register 042 may be divided by the contents of the x-register by sequentially depressing the x~(), ~ 0, 4, and 2 keys. The quotient is stored in re-gister 042, and the contents of the x-register itself re-main unchanged by the operation.
The y~() key may be similarly employed to directly perform any of the arithmetic operations enclosed by the .:
second pair of braces upon the contents of the y-register and any of the storage registers enclosed by the third pair . .
j of braces and store the result in the selected storage re-` gister without recalling the contents of the selected storage register and without changing the contents of the y-register. For example, the contents of the y-register `~ may be added to the contents of the a-register by sequentially depressing the y~(), +, and a keys. The sum is stored in the a-register, and the contents of the y-register remain unchanged by the operation. Similarly, the contents of register 038 may be multiplied by the contents of the y-register by sequentially depressing the y~(), x, 0, 3, and 8 keys. The product is stored in register 038S and the contents of the y-register remain unchanged by the opera-tion.
The x ~) key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of - braces upon the contents of the x-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the x-register without changing the contents of the selected storage register. For :
e~ample, the contents of the a-register may be added to ; the contents of the x-register by sequentially depressing the x~(), +, and a keysO The sum is stored in the x-register, and the contents of the a-register remain un-changed by the operation Similarly, the contents of the x-register may be multiplied by the contents of register `~ 022 by sequentially depressing the x (), x, 0, 2, and 2 keys. The product is stored in the x-register, and the contents of register 022 remain unchanged by the operation.
The y~l) key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the y-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the y-register without changing the contents of the selected storage re-gister (i.e. the y~l~ may be used as though it were a y () key in performing register-arithmetic operations).
` For example, the contents of the b-register may `~` be subtracted from the contents of the y-register by sequentially depressing the y~l~, -, and b keys. The dif-ference is stored in the y-register, and the contents of the b-register remain unchanged by the operation. Similarly, the contents of the y-register may be divided by the contents of regiters 039, by sequentially depressing the y~l~, ~, 0, 3, and 3 keys. The quotient is stored in the y-register, and the contents of register 039 remains unchanged by the ~; operation.
The INDIRECT key is used with the above-described data-storage and register-transfer keys to perform indirect data-storage and recall and indirect register-arithmetic :

, ' .

operations, in which the contents of a directly-addressed register (e,g the a-register, the b-register or any of the registers nnn) are employed as the address of an indirectly-addressed storage register (e.g. any of the other storage registers nnn) to be used in these opera-tions. When indirectly addressing any of the storage re-. gisters 000 through 048 or 108, care must be taken to in-sure that the directly-addressed register contains the proper address nnn of the indirectly addressed-register nnn. The indirect address used is the absolute value of the integer part of the contents of the directly addressed register. Thus, 1.732 will be treated as the address of register 001, -6.99 as the address of register 006, 0.999 as the address of register 000, and 106.75 as the address of register 106. Since the storage registers may only contain numeric data, the a- and b-registers may not be used as the indirectly-addressed registers in these opera-- tions.
The indirect data storage and recall operations may be summarized as follows by again using the above-described notation without braces for the INDIRECT key:

I~Y~
; ~ ~ INDIRECT ~ b ~ y~lJ ~nnnJ

Thus, the x~() and y~() keys may be employed with the INDIRECT
key to indirectly store the contents of the x- and y-registers, respectively in any storage register nnn designated by the contents of any of the other data storage registers. More-over, this may be accomplished without changing the contents , l~S~760 of the x- and y-registers or of the directly addressed storage register. For example, the contents o~ the x-register may be indirectly stored in the storage register designated by the contents of the a-register by sequentially depressing the x~(), INDIRECT, and a keys. The contents of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the y-register may be indi~ectly stored in the storage register designated by the contents of register 022 by sequentially depressing y)(), INDIRECT, 0, 2, and 2 keys. The contents of the y-register and register 022 remain unchanged by this operation.
The x~() key may be similarly employed with the INDIRECT key to indirectly recall to the x-register the contents of any storage register nnn designated by the conteLts of any of the other storage registers. This is accomplished without changing the contents of either the directly-or indirectly-addressed storage register. For example, the contents of the register nnn designated by the contents of the b-register may be indirectly recalled to the x-register by sequentially depressing the x~(), INDIRECT, and b keys. The contents of the b-register and of the indirectly-addressed register remain unchanged by this operation.
The y~) key may be employed with the INDIRECT key to indirectly exchange the contents of the y-register with the contents of any storage register nnn designated by the contents of any of the other storage registers. This is accomplished without changing the contents of the directly-addressed storage register For example, the contents of the y-register may be indirectly exchanged with the contents , . .~
., -90-.: .
.

~ 3760 , of the register designated by register 041 by sequentially depressing the y~,), INDIRECT, O, 4, and 1 keys. The con-` tents of register 041 remain unchanged by this operation.
The indirect register-arithmetic operations may be summarized as follows:

~ ; ~ INDI~ECT ~ 1 b In connection with the indirect register arithmetic opera-" tions it should be noted that the INDIRECT key may also be depressed immediately after the selected arithmetic key. Thus, the indirect register-arithmetic operations may also be summarized as follows:

) ~ j INDI~C~ ~ ~

Thus, any of the x~), y)(), x-(), and y~l) keys ~0 may be employed with the INDIRECT key and any of the arith-metic keys to indirectly perform register-arithmetic opera-tions employing the contents of either the x- or the y-register as one operand and the contents of any of the storage registers nnn designated by the contents of any of the other storage registers as the other operand. In : the case of the x)() and y~() keys, the results of these operations are stored in the indirectly addressed storage register nnn, and the contents of the x- and y-registers and the directly-addressed registers are not changed.
Similarly, in the case of the x () and y~) keys, the results `: --91--.

105~760 of these operations are stored in the x- and y-registers, respectively, and the contents of the directly and in-directly addressed registers are not changed.
` For example, the contents of the x-register may be added to the contents of the register nnn designated by the contents of the a-register by sequentially depressing the x~(), INDIRECT, +, and a keys~ The sum is stored in the indirectly-addressed register nnn, and the contents ; lO of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the storage register nnn designated by the contents of register 014 may be multiplied by the contents of the y-register by sequentially depressing the y-)(), x, INDIRECT, 0, 1, and 4 keys. The product is stored in the indirectly-addressed storage register nnn, and the contents of the y-register and register 014 remain unchanged by the operationO Simi-larly, the contents of the register nnn designated by the contents of the b-register may be subtracted from the con-tents of the x-register by sequentially depressing the x (), INDIRECT, -, and b keys. The difference is stored in the x-register, and the contents of the b-register and the ind~rectly-addressed register remain unchanged by the opera-tion. As a last example, the contents of the y-register may be divided by the contents of the register nnn designated by the contents of register 008 by sequentially depressing the y,l), INDIRECT, -, 0, 0, and 8 keys. The quotient is ;s stored in the y-register, and the contents of register 008 and the indirectly-addressed register nnn remain unchanged by this operation.

"~

. .

105~7~;0 Multiple-level indirect addressing may be performed to any desired level in the above described indirect data storage and recall and indirect register arithmetic opera-. .
tions by sequentially depressing the INDIRECT key once foreach desired level. Multiple-level indirect data storage and recall may be summarized as follows:
~x)()~ ~ a 1 ~ INDIRECT .... INDIRECT ~ b ~y"~ J
Thus, for example, the contents of the x-register may be indirectly stored in the contents of register 017 designated by the contents of register 003 in turn designated by the contents of the a-register by sequentially depressing the x~(), INDIRECT, INDIRECT, and a keys. The contents of the x-register, the a-register, and register 003 remain un-changed by this operation. Similarly, the contents of re-gister 046 designated by the contents of register 031 in turn designated by the contents of register 000 in turn designated by the contents of register 025 may be exchanged with the contents of the y-register by sequentially depressing the y~t~, INDIRECT, INDIRECT, INDIRECT, 0, 2, and 5 keys.
The contents of registers 025, 000 and 031, remain un-i~ changed by this operation.
Multiple level indirect register-arithmetic may be similarly summarized as follows:

( ~ INDIRECT .. INDIRECT ( ) [ b y~

:..

,,.

`:
~` 10513760 OR

~ DIR~CT ... INDIRECT ~ bJ

Thus, assuming, for example, that the 60 optional storage registers 049-lQ8 are available to the user, the contents of the y-register may be subtracted from the contents of register 108 designated by the contents of register 082, in turn designated by the contents of register 049 by sequentially depressing the y~(), INDIR~CT, INDIRECT, -, O, 4, and 9 keys. The difference is stored in register 108 and the contents of the y-register, register 049, and regis~er 082 remain unchanged by this operation. Simi-larly, the contents of the x-register may be divided by the contents of register 106 designated by the contents of register 056 in turn designated by the contents of the b-register by sequentially depressing the x (), ~, INDIRECT, INDIRECT, INDIRECT, and b keys. The results are stored in ' 20 the x-register, and the contents of the b-register and registers 003, 056, and 106 remain unchanged by this opera-tion.
Numeric Address Termination As described above, each of the available numerically ., ` addressed storage registers 000 through 048 or 108 employed in the foregoing data-storage and register-transfer opera-~ tions is properly addressed by selectively depressing the - decimal digit keys to specify its three-digit address. Upon entry of the third digit, the numeric address is automati-cally terminated. Any immediately following digit entries , ; -94-~ lOS8760 , .
are therefore not intrepreted as part of the numeric ad-dress, but rather as the beginning of a new data entry.
Thus, for example, if the x~(), 1, O, 3, 2, and 5 keys are sequentially depressed, the contents of the x-register are stored in register 103, and the number 25 is entered into the x-register Similarly, if the y>(), +, O, 0, 2, 1, and + keys are sequentially depressed, the contents o~
the y-register are added to the contents of register 002, and the number 1 is entered into the x-register and there-upon added to the contents of the y-register.
A numeric address may also be terminated, without entering leading zeros of the address, by depressing any non-numeric key except the STEP PRGM key or, if the cal-culator is in the manual operating or first key-log print~ng mode, the CONTINUE key. However, most of the terminating key entries that may be used will also be . executed. For example, if the x~(), 2, and + keys are sequentially depressed, the contents of the x-register are stored in storage register 002 and also added to the con-tents of the y-register. Similarly, if the y)(), 1, 3, 8, and a keys are sequentially depressed, the contents of the y-register are added to the contents of register 03~, and :`
the contents of the a-register are recalled to the x-register.
When the calculator is in the manual operating or ~irst key-log printing mode, the STOP key may be used to terminate a numeric address if a no-operation address-terminating key entry is desired. For example, by simply depressing the x~(), 3, and STOP keys the contents of the ~-register may be stored in register 003 without performing any other operation. Similarly, when formulating or - ~5876~
entering a program by which the calculator is to be con-trolled in the automatic operating mode, a CONTINUE pro-gram step may be employed to terminate a numeric address if a no-operation address-terminati~g program step is desired For example, i~ t~e program steps y)(), x, 2, 9, CONTINUE, and 3 are sequentially encountered when the calculator is in the automatic operating mode, the contents of register 29 are multiplied by the contents o~ the y-register, and the product is stored in register 29. No operation is performed by the CONTINUE program step, and the next program step 3 is stored in the x-register as ~"
the beginning o~ a new data entry.
Since every numeric storage register e~cept optional registerslOO-108 may be uniquely speci~ied by less than three digits, these abbreviated address-termination feat~res permit significant reductions in the number o~
~ey-operations and program steps required to perform many calculations. Moreover, these same address termination features may be used in connection with the four-digit numeric addresses of the program storage section o~ the RWM to achieve still ~urther reductions in the number o~
key-operations and program-steps required to perform many calculations.
Program-Co~trol ~eys (GO TO, IF x<y, IF x-y, I~ x~y, IF FLAG, ` SET FLAG, LABEL, RETURN ) .. . .

All of the previously-described keys except the FLOAT, FI~), RUN, PRG~, KEY LOG, LIST, ~OAD, and RECORD
keys may be employed both for controllin~ the operation o~
the calculator during the manual operat~ng and ~irst key-log printing modes and for entering program steps into the calculator during the program entering and second key-log printing modes. When the calculator is in the manual operating mode, the user may continuously observe the output display of the contents of the x-, y-, and z-registers and, in accordance with his observations, make his own decisions about what to do next at any stage of the cal-culation. However, this is not possible when the calculator is executing a stored program at high speed in the auto-matic operating mode. The above eight program-control keys have therefore been provided to permit the calculator itself to test calculated quantities and make decisions based on those tests during the automatic execution of an internally-stored program. These eight keys may be used ; to permit unconditional branching (or transfers), condi-tional branching (or transfers), symbolic or labelled branching, storage of "yes-no" information in a flag and conditional branching based on that t'yes-no" information i at a later stage in the execution of a program, and un-conditional or conditional branches to pre-defined program routines with return to the main program sequence upon com-` pletion.
A Branching instructions in a program cause the user program counter to specify an address other than the next sequential address in the program storage section of the RWM~ whereupon execution of the program continues sequen-tially from the new address. If a branch is conditional, the calculator makes a decision, based upon a specified condition, whether or not to branch. Xowever, if the branch is unconditional, the calculator has no option, and ~058'760 must branch to the address specified in the program (e.g.
` by a GO T0 program step followed by a numeric address nnnn).
The GO TO key is depressed followed by decimal digit keys specifying a selected four-digit address nnnn in the program storage section of the RWM to set the user program counter to the selected address nnnn. When this sequence of keycodes is encountered as a sequence of pro-gram steps, an unconditional branch is made to the address indicated and the program step stored at that address is executed. Execution of the program then automatically con-tinues to run from that address.
For simplicity of description the terms "keys" and ~ "program steps" will hereinafter be used synonomously since ;~ the remaining keys of this group are used almost exclusively to enter keycodes into the calculator as program steps during the program entering mode of the calculator. All of ' the program steps so entered are automatically executed ~x during the automatic operating mode of the calculator~
The four IF keys are used for conditional branching.
( 20 The IF x<y, IF x=y, and IF x>y keys compare the numeric Il values contained in the x- and y-registers to determine if ! the number in x is less than the number in y, equal to the ~`~i number in y, or greater than the number in y respectively.
The IF FLAG key tests the condition ("yes-no") of the flag, which is controlled by the SET FLAG key hereinafter ex-plained. There can be only two possible results to each test made by each of these four keys. The condition tested is either "met" (YES) or ~not met" ~N0).
When the condition tested is met (YES), the next 3~ program step following the "IF" is automatically executed.

~: , ~ , . .

105~3760 However, when the condition tested is not met (N0), the calculator automatically skips (ignores) the next four program steps and continues execution at the ~ifth program step following the 'tIFn.
If the program steps immediately following the 'tIF"
constitute a numeric address nnnn and the condition tested - is met (YES), an automatic branch is made to that address nnnn. The program step stored at address nnnn is thereupon executed, and automatic execution of the program continued ; 10 from there. If the program steps immediately following the "IF" constitute operations (e.g. +, t, etc.) then no `. branch occurs and the operations are executed.
When an IF program step (other than IF FLAG) is encountered, the two numbers in the x- and y-registers are automatically rounded before the test is made. In each register, the tenth digit of the number is rounded according to the value of the guard digits; the guard digits are then set e~ual to zero. Thus the numbers to be tested actually have the same values as would appear in a floating point display with all ten significant digits displayed. After `~ the test has been made, the numbers in the x- and y-registers retain their rounded values. This means that the actual ~" values of the number in the x- and y-registers may be dif-ferent after the test than before. If the resulting slight ` loss in accuracy is undesireable, the numbers in the x- and y-registers can be stored in the data-storage section of the RWM before the "IF" test is made and can be recalled and substituted for the rounded numbers after the "IF" test is completed.
The use of the IF x>y and IF x<y keys is illustrated ~' _99_ ' ~3S~760 . .
by employing the following sequence of program steps be-ginning with an IF x>y program step and including a three-step conditional routine for taking the absolute value of the contents of the y-register:
IF x>y r X~Y
conditional I l 4-step conditional routine for ¦Y¦ ~CHG SIGN ~ sequence x~y CONTINUEJ
'" 10 If the contents of the x-register are greater in value than the contents of the y-register (i.e. condition met), then ~.~ every program step in this sequence is executed and the ab-;, solute value of the contents of the y-register is calculatedO
As described above CONTINUE is a no-operatlon program step.
,, .
~ It is used in this and the following examples to fill in `~ the fourth program step to be skipped if the test condition is not met. If the contents of the x-register are equal to or greater in value than the contents of the y-register (i.e.
the condition is not met), then the four program steps im-` mediately following the IF x>y program step are skipped and execution continues beginning with the t program step. In this case the absolute valùe of the contents of the y-register is not calculated.
The use of the IF x=y key is illustrated by employing the following sequence of program steps:
IF x=y 3 ~ 4-step conditional sequence CONTINUE
CONTINUEJ

`:
, l~S8760 If the contents of the x-register equal the contents of the y-register in value (i.e. condition met), then every program step in this sequence is executed. This results in an auto-matic branch to execute the program step stored at user address 0023. However, i~ the contents of the x-register do not equal the contents of the y-register in value (i.e.
condition not met), the four program steps immediat;ely fol-lowing the IF x=y program step are skipped and execution con-` tinues beginning with the + program step.
A 10 The use of the IF FLAG key is illustrated by the - following sequence of program steps:
IF FLAG

" ~ 4-step conditional sequence ~ CONTINUE
`:~ CONTINUE
:~
~ SET FLAG
. ~, ~ If the flag controlled by the SET FLAG key has been set :,i ~- (i e condition met), then every program step in this se-quence is executed. This results in an automatic branch to execute the program step stored at user address 0041. How-ever, if the flag controlled by the SET FLAG key has not been set (i.e. condition not met), then the four program steps immediately following the IF FLAG program step are skipped and execution continues beginning at the SET FLAG
program step by setting $he flag.
The SET FLAG key establishes the condition to be tested by the IF FLAG key. The "YES" condition is established when a SET FLAG keycode is encountered either as a program ~0 step or as a keyboard entry The "NO" condition is established : . -101-'` ' ' , .

by clearing the flag. This occurs automatically whenever the calculator is switched on or whenever a CLEAR or IF FLAG key-code is encountered either as a program step or as a keyboard entry. If the flag condition must be retained for use later, the program must include a SET FLAG program step in the se-;::
quence of program steps execu$ed ~ollowing the flag-clearing ` program step. The flag enables the user to select the con-;`~ ditions which will determine whether a conditional bra~ch :.
(or operation) is to be made.
The LABEL key allows relocatable symbolic addresses , to be used within a program. A LABEL key immediately fol-lowed by any other programmable key (e.g. LABEL, ~) except the END key serves as a symbolic address that may be in-i serted in a program immediately before any program step a `i:
user may wish to relocate independently o~ its absolute (numeric) address. This symbolic address is relocated by a search command comprising a GO T0 key immediately followed by the symbolic address itsel~ (e.g. ~0 T0, LABEL, ~). In response to this search command, the user program counter is reset to the first user available address 0000 in the program storage section of the R~M and is sequentially incremented in a search operation until the symbolic address (e.g. LABEL, ~) is ~ound. The user program counter then specifies the next address which is the program step designated by the symbol~c address.
; lf the search comma~d ca~e from the keyboard~ the . , calculator waits ~or the next key to be depressed. ~owever, i~ the search command came from the program, then execution automatically continues at the program step designated by the symbolic address. The keys o~ the symbolic address itself `:

.' , .

105~3760 ;
serve as no-operation codes and are ignored during execution o~ the program. This may be illustrated by the following sequence of program steps.
PROGRAM
; ADDRESS STEP
r 0098 ~~~-0101 ~
0102 etc.

,,,~ 10 0362 ___ ' 0364 s 0365 ` 0366 etc.
The search for the symbolic address "LABEL, ." is initiated s immediately after address 0101 is designated by the user pro-gram counter and starts at address 0000. When the symbolic ad-dress is found, program execution continues with the t program step at address 0365. The - program,steps 0101 and 0364, serving as paxt of the symbolic address are not executed.
A specific symbolic address cannot be used to specify more than one location at any one time. If it is, only the ; first (lowest order numeric address) specified will be valid (i.e. the point of transfer). Any number of di~ferent labels can be used at one time, limited to the number of keys available to follow the LABEL key.
If transfer to an undefined symbolic address occurs, `~ 30 the calculator will search all of program memory, and if the .

~ -103-7f~0 : ' ~
symbolic address is not ~ound, will stop with the STATUS
indlcator light on. The program-counter will speci$y thë
next ~ollowing program steps.
Branching to a symbolic addrsss o~fers considerable advantages over branching to an absolute address. Programs with symbolic addresses can be stored anywhere in the pro-gram storage section o~ the RW31 and can be easily moved and . . , ` relocated because there are no absolute addresses to be changed.
Also, any time a program is to be corrected (i.e. program steps changed, added or deleted), any absolute addresses must be chec~ed in case they themselves must now be changed as a ; result o~ the corrections. This may entail substantial book~eeping by the user. If symbolic addresses are used instead of absolute addresses, the corrections will not a~-~ect the eymbolic addresses.
The main disadvantage of using symbolic addresses is that a search takes considerably more time tdepending upon the location of the label in memory) than does a branch to an absolute address. Usually, this will have no significance because, in this case, "time" constitutes only a ~ew thousandths o~ a second. ~ven if time is a significant factor, the user may st~ll take advantage o~ symbolic addresses by writing his original program with symbolic addresses and once the program .j .
has been completely debugged, changing the symbolic addresses to the appropriate absolute addresses~
The ~ET~E~ key is used to transfer to ti.e. call) a subroutine (subprogram) an~ return from the subroutine to the point in thè calling program where the transfer was ini-t~ated. Subroutines may be nested up to a depth of ~ive. An attempt to nest to a depth o~ more than ~iYe is an error, .. ~ .. . .

" lOS87~0 "
stopping execution of the program and turning on the STATUS
indicator light. Both the automatic initialization occuring at turn-on and the END key (given either as a program step or a keyboard entry) automatically reset the nesting to a depth of zero so that all five depths are then available~
A GO TO key followed by a RSTuRN key and either an absolute ., numeric or symbolic labelled address may be used in the ` calling program to (unconditionally) call a subroutine. The - address used specifies the starting address of the subroutine.
If a symbolic address is used, the first two program steps of the subroutine must also be the same symbolic address. An IF key followed by GO TO and RETUBuRN ke~ and either an absolute numeric or symbolic labelled starting address may also be used in the calling program to conditionally call a subroutine. Execu-tion of the steps of the subroutine starts automatically as soon as the subroutine is called. A RESTURN key must be in-cluded as the last step to be executed in the subroutine. The RETURN causes a branch to the "return-address" in the calling program. The return address is always the address immediately following the last step used to call the subroutine. Exe-cution of the calling program then continues automatically, starting at the return address.
Any number o~ subroutines may be called individually during a program. However, it is also possible to use more than one subroutine at one time. One subroutine can call a second subroutine which, in turn, can call a third subroutine, and so on. This multiple-calling is known as "nesting". The calculator can remember (store~ from one to five return-addresses at a time so that the subroutines may be nested up to a depth of five. Returns are made on a "last-in, first-out"

- l~S8760 basis, the return always being made to the last return-address stored. As soon as the return is made, that return-address is forgotten (erased from storage) so that the pre-vious address now becomes the ~last~' one, Thus the returning order is always the opposite of the calling order, A program written as a subroutine may also be used as a "stand-alone~ program, This is accomplis~ed by depressing ` the END key to erase any return-addresses currently stored in the calculator and by not using the RSUBURN key when addressing the memory before the program is run, : Special Function Keys (F~T, ~p~, PAPER) .. .
The FMT (format) key is used to initiate special operations not otherwise defined and implemented by the other basic keys of the calculator, It is always used with other keys and, in e~fect, serves to re-define these other keys to implement the desired special operations, Several of these special operations associated with the FMT key are de~ined as part of the basic calculator, Others have been de~ined as part of associated plug-in ROM modules and are available only when the associated ROM modules are plugged into the calculator, :':
The command-sequences FMT, t and FMT, l are used to .~
operate the g-Y plotter peripheral unit. They are part of the basic calculator. The X-Y plotter-input commands are PEN t, PE~ l, and x and y coordinates to which the pen-carriage is to be moved. The x and y coordinates are specified by decimal numbers in the range 0000 to 99990 The corresponding actual pen range of physical movement is determined by adj~stments ` on the plotter itself. The FMT, t command-sequence causes the pen to be raised and the contents of the x- and y-registers to be fed to the plotter as the x and y coordinates to which ~587~0 the pen is to be moved. The FMT, ~ command-sequence lowers the pen and transmits the x-y coordinates. Note that for both commands the pen is raised or lowered first and the pen car-riage is then moved. The x-y coordinates in the x- and y-registers must be pre-scaled by the user in the range 0000 to 9999. I~ these limits are violated, the following events occur:
1. If the contents of the x- and/or y-registers are less than 0000 (i.e. negative), 0000 is sent to the plotter, the pen is raised, moved, and loweredO
2. If the contents of the x- and/or y-registers are greater than 9999, 9999 is sent to the plotter, the pen is raised, moved, and lowered.
The result is to plot a series of dots along the boundary of the plot. The raising and lowering of the pen is a visual and audible warning to the user that he is plotting out-of-bounds.
The basic calculator includes provision for recording , .
a user-program in the program storage section of the RWM as a secure program. This provision is completely distinct from a protected recording obtained by physically notching the magnetic card. A secure program is, by definition a program which can be executed only. It cannot be listed, recorded, looked-at in the program mode, edited, or changed in any way. It is a program which can only be executed in the automatic operating mode at high speed by using the CONTINUE key (or step-by-step using the STEP PRGM key hereinafter explained).
Any program entered by the user from the keyboard input unit into the program storage section of the RWM, or any non-secure program loaded from a magnetic card, can be l~S876~1 recorded as a secure program. This is accomplished in the same manner as described above in connection with the RECORD
key except that the keys FMT and RECORD are sequentially de-pressed in the named order to initiate the recording operation.
The program thereupon recorded on the magnetic card or cards is a secure program. The original program also remains in the program storage section of the RWM as a non-secure pro-gram, and can be recorded again, either as a secure or non-secure program. It should be noted that once recording of a secure program has begun, it must be completed by continuing to insert cards until recording is terminated by an END pro-gram step. If the recording process is interrupted by de-pression of the STOP key, the recording will be terminated but the original program stored in the program storage sec-tion of the RWM then becomes a secure program and can only be executed - no further recordings can be madq.
If a program stored in the program storage section of - the RWM is a secure program ~either by loading a program re-corded as a secure program or by the STOP default outlined above) the following conditions prevail:
1. If the PRGM key is depressed, the entire program memory is cleared.
2. If LIST or RECORD are depressed, they are ignored, so that no listing or recording of the program can be made. These actions do not destroy the program - they are just ignored.
3. Since the program is destroyed by switching to the PRGM mode, the program cannot be changed or edited in any way.
3~ Loading of a secure program is no different than lOS8760 loading a non-secure program - the same procedure holds.
Several secure programs may be chain-loaded. If a non-secure program is loaded into the calculator when a secure program is already stored therein, the program storage section of the RWM is cleared of the secure program in all areas not loaded by the non-secure program so that no trace of the secure pro-gram remains after loading the non-secure program Thus, a non-secure program may not be chain-loaded after a secure pro-gram. However, the reverse can be done _ a secure program can .!
be chain-loaded to a non-secure program but the composite - program is then secure.
The command sequence FMT, GO TO is used to implement automatic or program-controlled loading of magnetic program cards. The effect of FMT GO TO is the same as the following sequence: GO TO, O, LOAD, GO TO, O, and CONTINUEJ This may :l be used to load a program from the keyboard, with automatic ;;! initiation of execution, or it may be used in a program to . ~ .
"link" programs. If the magnetic card reading and recording unit is not loaded with a magnetic card, the INSERT C M D in-dicator light will come on indicating to the user that a mag-netic card should be inserted. The LOAD routine operates in the same manner as described above in connection with the LOAD
key and is terminated by an END program step on the magnetic card.
The command sequence FMT, x~ causes the contents of the available numeric-addressed data-registers in the data storage section of the RWM to be recorded on a magnetic card The INSERT CARD indicator light comes on, and the recording continues, pass-after-pass, card-after-card until all registers are recorded, at which time the magnetic card reading and . --109--, `

~C~5876~

recording unit stops and the INSERT CARD indicator light goes out. If the FMT, x~ command sequence was executed from a stored-program, the program will return to execution at the keycode immediately following the x~ command Recording may be terminated after any card by depressing the STOP key if the FMT x~ command sequence came from a stored program, execu-tion may then be resumed by depressing the CONTINUE key . ~
The command sequence FMT x~ causes the loading of the available numeric-addressed data registers in the data storage section of the RWM from one or more magnetic data cards.
These registers are loaded card-after-card until all the registers are loaded. The INSERT C M D light remains on, and ` the card unit continues to run until all are loaded. The loading may be terminated by a STOP key. If the FMT, x~ ¢om-., ~-~ mand sequence is executed from a stored program, execution re- sumes after a completed data load.
The æF~E key causes the contents of the x-register ~i to be printed in the same format as it is displayed (i. e.
s FIX (), n, or FLOAT). If additional ~ commands follow im-` 20 mediately, they will cause the printer to space (print a blank ` line). If the ~F~E command follows immediately after a numeric entry to x (from the keyboard or from a sequence of digit-keys in a program) the numeric printout is followed by an * (asterisk) indicating that this was a data entry and not a computed result.
The PAPER key is depressed to space the strip of thermal-sensitive paper used by the output printer unit. It continues to drive the paper upward until it is released.
Program Checking and Editing Keys (~g~ TEF) The STEP PRGM key is not programmable and is used, from ~58760 the keyboard only, to single-step programs. When the cal-culator is in the manual operating mode the STEP PRGM key single-steps program execution. Each time STEP PRGM is de-pressed the program counter is incremented by one so that one program step is executed. When the calculator is in the program mode the STEP PRGM key enables the program steps stored in the program storage section of the R~M to be viewed. Each time the STEP PRGM key is depressed, the program counter is incremented by one, so that the address and program step displayed in the y-register shifts to the z-register, those in the ~-register shift to the y-register and the next higher address and program step appears in the x-register.
The BACK STEP key is not programmable and is used to decrement the user program counter by one each time it is pressed. This backs up the output display (iOe. does just the opposite of the STEP PRGM key). It should only be used in the . .
program mode. I~ the STEP PRGM and BACK STEP keys are de-pressed alternately, thè same program step will be executed repeatedly. This key is extremely use~ul in editing and checking programs and when used with the PRGM STEP key per-mits the user to advance either forward or backward through a stored program one step at a time.
Definable and Redefinable Keys The half keys A-O comprising the group of definable keys 91 enable the calculator to be tailored to the special needs of the user. Operation of these keys is defined by the various plug-in ROM modules 92 that may be used with the cal-culator. Without these ROM modules the definable keys 91 serve no function and accidently depressing them, or encounter-ing them in the execution of a stored program, will result in a completely non-destructive no-operation.
!

, '`,' -, ~05876~
.
I The plug-in ROM modules 92 include the alpha ROM
module mentioned above, a de~inable ~unctions ROM module, a mathematics ROM module, a statistics ROM module, and a typewriter ROM module. Both the alpha RO~ module and the typewriter RO~ module rede~ine nearly all o~ the keys o~
the keyboard as well as defining the definable keys 91 the=selves. The de~lnable functions RO~ module, the mathe-matics ROM module, and the statistics ROM module each uniquely de~ine the de~inable keys alone and may each be used at the same time as the alpha ROM module or the typewriter ROM
module.
A dif~erent overlay 192 is associated with each o~
the definable ~unctions, mathematics, and statistics ROM
modules and is employed wi~h the de~inable keys 91 to identify the ~unctions performed therby when its associated ROM module . ! ' ~` is plugged into the calculator. Each of these overlays 192-comprises a thin metal template that ~its over the definable keys 91 and latches into a recess around them. The graphics on these templates visually complete the key shapes and in-2Q dicate the key ~unction. A small tab positioned jU9t above the nameplate releases each template, which then pops up e~ough to grasp. Three holes 196 near the top edge o~ each template allow direct viewing o~ three light-emitting diode indicator lights used to indicate various operating c03di-tions assaciated w~th the routines implemented by the ROM
module. When the overlay and its associated RO~ module are not i~ use they may be secured together by a pair o~ tabs 198 provided o~ the ROM module.
~ description o~ the additional key operations that may be provided by the plug-in RO~ modules will now be given.

~058760 , Alpha ROM Module The Alpha ROM module redefines the keyboard input unit :.
as indicated by the letters printed on the tops of the definable keys 91 and the letters and symbols printed on the front sides of most of the other keys to provide an "alpha keyboard" (see Figure 8) containing 54 character-entry keys, 5 operational keys, and 16 "non-essential" keys (these non-essential keys are either inoperative or duplicate other keys during the alpha mode). During the alpha mode, the key-log feature is deactivated (thus, any keys pressed are not logged).
The 54 character-entry keys include all of the :
English alphabetic characters A-Z, all of the decimal numbers 0-9, and all of the following symbols ~, ~ / (printed by the . key), x, -, +, ~, ~, " ., =, $, ?, (, ), %, ", and #.
Depressing any of these keys during the alpha mode, will cause the alphameric character or symbol indicated thereby to be printed out in line-printer fashion. The output printer unit operates as a line printer in that each character is not im-- mediately printed out, but rather an entire line (16 characters) is first stored and then printed out. The print-out occurs as the 16th character is entered.
The 5 operational keys include the FMT key, the STOP
key, a SPACE key (normally the CONTINUE key), a C~ETuRRN key (normally the CLEAR key), and a PAPER key.
During the alpha mode, the following operational keys are depressed to perform various printing operations. De-pressing the FMT key twice redefines the keyboard to the alpha mode, after which character keys may be depressed. After the last character is entered, depressing the F~T key causes a line print, a line feed, and returns the keyboard to normal .
.~

:-105~'7f~0operation. (The output display is blanked during the alpha mode, although the contents of the x-, y-, and z-registers remain unchanged.) For example, the alphabet may be printed by sequentially depressing the RUN, STOP, FMT, FMT, A through j æ, and F~T keys.
Depressing the SPACE key inserts a blank space in the printed line (similar in operation to the space bar on the typewriter).
Depressing the CELTuRN key causes a line print and advances the prInter to the next line (i.e. like a typewriter carriage-return and line feed operation). The alpha mode ~; rema~ns set after this instruction. Successive CL~AR instruc-tions will cause the printer to advance, without printing, one line for each instruction.
Depressing the STOP key terminates the alpha mode without a lt~e print or line ~eed. Any characters entered but .
~ot printed will be erased when STOP is pressed. This in-struction is not programmable and should not be used while progr = ing alpha messages.
The PAPER key is a manual paper advance control. This operation is not progr = able.
The 16 "non-essential" keys include the 1, x~y, t, ~F~' ST~B~ END~ SAT~K~ PREGP~ FLOAT, FIg (), RUN, PRG~, EEY
LOG, LIST, LOAD, and RECORD keys. These keys are not essential for alpha printing operations The non-essential keys ~hich are programmable duplicate the SPAC~ key, while most of the non-progr = able keys are "locked-out" (i.e. not operational) during alpha printing operations. Pressing BACE STEP or STE~
PRGM will cause I or 0, respectively, to be printed.

. .

. . .

05876~
Definable Functions ROM Module When the definable ~unctions ROM module is plugged into the c~lculator, the user may employ the definable keys 91 to perform the redefined functions identi~ied by the associated overlay sho~n in Figure 9. These functions in-clude:
a. Defining special subroutines that can be called by a single key;
. b. Protecting such subroutines against accidental . 10 erasure;
c. Deleting one, or more, of such subroutines when ^ desired; and d. Deleting, inserting, or searching for keycode-~in any stored program.
a. Defining a Function A user definable function can be any sequence of pro-gram steps, beginning with the keys D~FINE F(i), where F(i) represents one o~ the keys Fl thru F9. The execution of such sequence of program ste~s must be terminated with the F-RET
key i~ the same manner as the SUB~RET key in the case of sub-routines.
Exa~ple:
The following is a function which puts ~ in x, y, and z.
Program Step _ ~ey 0000 DEFI~E
OOI Fl .. 0~03 t .~

., .

./ -115-'':'' :
~ .

`" ~051~76~

The above function is identified by the key Fl. To execute this function simply press the Fl key in RUN mode or insert Fl in a program at the place you want it executed.
Example:
The following is a call on Fl from another program (the program here happens to be another function F2).
Program Step Key DEFINE

Fl Notice that we have assigned the same program step numbers to both the functions Fl and F2. Every function definition is assumed to start at program step 0000. All GO TO commands when present in a function are coded accordingly. This al-lows the user to define functions and delete them in a way independent of where they actually reside in the calculator memory. The key DEFIÆ in both of the above functions serves to mark the start of the definition of a function in the cal-culator memory. This key is treated as an error if it is pressed during RUN mode. The key DEFINE is also treated as an error if the user attempts to execute it in a program.
Example:
;

Program Step Key --11~--~ lOS~7~0 The DEFINE at program step 0003 will be treated as an error when encountered during the execution o~ F3. The user here forgot to terminate the execution of F3 with F-R~To This error will cause the calculator to stop execution and turn on the STATUS light.
b. Protecting User Defined Functions The protection feature allows the user to designate areas of memory to be a part of the calculator's executive system.
i. Protecting A Single Function Assume that you have just entered the definition of the function Fl in memory (the same Fl discussed earlier). After entering the last keystroke in the definition, namely F-RET, the program counter (y ` display) will point to program step 0006. Location 0005 which contains F-RET will be displayed in the z-register. Switch to the RUN mode. Press PROTECT.
The light on the top of the PROTECT key (option 2 light) .......... 0....... will come on. The de-finition of Fl is now protected up to and including the F-R~T key. If you switch back to PROGRAM mode, whatever was in program step 0006 before will appear ` now to be at program step 00000 All the program -~ steps used in defining Fl became "invisible". For all purposes these program steps are now a part of the calculator system. You can still execute Fl by pressing the corresponding key in RUN mode, or by ~; calling on it from another stored program or function.
:, ii. Protecting Several User Defined Functions Assume now that both the functions Fl and F2, de-scribed earlier, are to be protected. After protecting ' ~OS876() : Fl switch to the PROGRAM mode and enter the de-finition of F2~ namely:
Program Step Key A~ter entering the definition of F2 switch to the RUN mode. Press DELETE PROTECTo The protect light indicator (option 2) will go off. Press PROTECT.
Both the definitions of Fl and F2 are protected.
iii. E~fect o~ Protection on User Memory . When protecting a certain number of keystrokes the calculator subtracts that number from the total number of program steps available in user memory~
The user can compute the number of program steps available at any time as ~ollows. In RUN mode, press END, DELETE, PROTECT, switch to the PROGM M
mode and read the program step number in the y .~
~ display, assume this number is p~ The number of ; program steps available to the user are given by the simple ~ormula:
Available Program Steps = n - p The variable n in the above formula is 500, 1012 or 2036 according to the amount of user memory pur-. chased.
After finding the value of p, as illustrated above, you can switch back to the R~N mode and press PROTECT
again to re-establish the protectionO

.

` " ~05~76~) c. Deleting User Defined Functions To delete a given ~unction simply press the DELETE key ~ollowed by the n~me o~ the function to be deleted. The DELETE key only applies to the unprotected area o~ user me-mory. This prevents accidental erasure o~ protected ~unc-tions. Pressing the DELETE key causes the Insert/Delete ; light to come on (option 1) indicating that a memory modi-~ication operation is to be per~ormed. If aft-er pressing the DELETE key you ~ind that you did not want to delete a4ter all, you can press the CLEAR key to abort the delete option. Pressing the CLEAR key at this time will cause the Insert/Delete light to go o~. If the ~unction to be de-leted does not e~ist t~e error light will come on and the delete operation will be aborted. The DELETE key must be pressed while the calculator is in RUN mode. The DELETE
key may be followed by a ~unction name (Fl thru F9), CLEAR, or a digit. Other keys following the DELETE key will turn ~q; on the error light and abort the delete operatio~ en-^~ countered during the execution o~ a stored program the DELETE
key will cause the calculator to stop e~ecution and turn on ; the error indicator.
DELETING TEE LAST F~NCTION IN ME~ORY
. . . .
The delete operation is designed to delete a portion o~
~, user memory which starts with the DEFINE o~ the function to be deleted and endlng with the keystroke prior to the DEFINE
o~ the negt ~unction in memory, or E~D. To illustrate, con-sider the ~ollowing memory map~ -Program Step ~ey , .

0001 ~1 (Memory Map Continued) :;

` 0007 0009 IF X~Y

, 0012 CONT

0017 ...
. When pressing DELETE Fl the calculator will delete the :~ memory portion delimited by the two arrows in the memory map.
. 20 After deletion the DEFINE at program step 0004 will move to program step 0000. The following keystrokes will move ac-~ cordingly. Since the last function in a user memory is not :~ likely to be followed by another DEFINE it is advisable to `~` terminate that function with the keystroke END as shown in the memory map (program step 0016). If the last function in ~ memory is not terminated with END then by deleting that func-: tion the user will also delete that portion of memory which follows that function and terminates with an END. When de-leting the last function in memory, the delete operation does . 30 not delete the END key. Thus deleting F2 from the memory map ' -`; lOS~376~

shown earlier will result in the following memory map.
Program Step Key 0001 Fl ' 0002 CLR
; 0003 F-RET

The keystroke END becomes now the terminator to the de~ini-tion o~ Fl.
` 10 d. General Editing Capabilities In addition to deleting functions the user of the de-finable function block is offered the capability of deleting, inserting, and searching for individual keystrokes in memory.
This feature is discussed next.
i. Deleting Individual Keystrokes ~,~ If the DELETE key is followed by a 4 digit address*
the calculator will delete the keystroke contained in that address and move all the following key-strokes accordingly.
Example:
Consider the memory map:
Program Step Key `` 0000 CLR

' 0002 0 0006 .0O
*See next paragraph on Automatic Address Termination for further details on address length.

1 [3587~0 To delete the keystroke at program step 0002 press the D~L~TE key in RUN mode, (Insert/Delete light will come on), ~ollowed by the keys 0 0 0 2. The resulting me-mory map will be:
Program Step Eey ' 0000 CLR

., 000~ ~

~t~0006 ...
~- Notice that the keys'roke previously at 0003 is now at program step 0002. All the keystrokes ~ollo~ing the deleted key up to the last keystroke in memory ha~e bee~ moved accordingly.
TO~AT~ ADDRESS TE~MINATION AND ABORTING A DELETE:
, In the above example we used a 4 digit address to speci~y the keystroke to be deleted. The user can ùse a 3, 2, or one , 20 dlgit address i~ such an address is terminated by a no~-numeric key other than CLEAR. The ~ollowing delete commands are e~ui-valent to that given in the last example:
D ,~TE 2 STOP -.
`i DELETE 02 S~OP
DELETE 002 ' STOP
To abort a delete command be~ore it is executed press the C~ R key. The Insert/Delete light (optio~ 1) will go o~ and .. .. . . .. . . . ..
the delete command will be cancelled. The CLEAR key can be pressed immediately a~ter the DELETE key or during the entry o~ the address digits. Notice that the 4th digit in a~ address .

105~760 terminates that address. This digit signals to the calculator that the delete operation is to be performed. A CLEAR key following the 4th digit of an address will have no effect on a delete operation. After performing a delete operation the calculator switches off the Insert/Delete light. If the de-lete address is bigger than 2035 the status light will come on and the delete operation will be aborted. This number re-presents the maximum available program steps in the cal-culator.
ii. Inserting Individual Keystrokes The definable function block also offers the user the capability of inserting key codes at any arbit-rary program stepO
;~ Example:
Consider the following memory map:
Program Step Key . ~

0004 ~OO
To insert a keystroke before the key at program step 0002, press INSERT in RUN MODE, tthe Insert/
Delete light will come on), followed by 0 0 0 2.
Switch to PROGRAM mode. The y display will point to program step 00020 At this location you will find that a CONTINUE (Code 47) has been inserted.
The keystroke originally at 0002 has now been moved to step 0003. All the keystrokes which follow this keystroke have been moved accordingly.

-123_ 105876~
, .
~ To put a new keystroke at oao2, simply press - the new key while you are still in PROGRAM mode.
The key pressed will replace the CONTINUE in-serted earlier by the calculator. Without re-placing the CONTINUE at step 0002 the new memory map is as shown below:
; Program Step Key ; 0001 GO TO

. 0003 9 >~ 0005 The address in an INSERT command may . . . . . . O
be automatically terminated in the same manner described earlier in connection with DELETE. The insert operation can also be aborted in the same 3 fashion~
Notice that the insert operation effects the con-tent of all the program steps following the one designated in that operation.
iii. Searching for a Given Keystroke in Memory:
The ability to search for a given keystroke in me-mory is provided by the FIND key. By pressing the FIND key, in RUN mode, ~ollowed by any other key on the keyboard the user commands the calculator to search for that key in memory starting at the cur-rent program counter value. If the key asked for is not found, the status light will come on. ~ow-3C ever if the key is found: the calculator will :~.
. .

.`'' ' ~ ' .

105~376~
automatically switch to PROGRAM mode, and the Z
register will contain the program step at which the key was found~
Example:

, Consider protecting a function definition area in ; memory. This area is terminated with the key ENDo ,;~,h, Reset the program counter to 0000 by pressing GO

TO O or END, in RUN mode. Now press FIND END, the z-register will now contain the terminating END

in the function area. Press RUN PROTECT. The :', function area is now protected up to and including that terminating END.
.:~
`~ PROGRAMMING HINTS:
:.
The definable functions can be nested 5 levels deep, irrespective of regular subroutine nestingO A higher nesting value will cause the calculator to stop execution and turn on the status light.
The light on top of the F-RET key (option 3) when lit in-dicates that the user is executing a sequence of keystrokes in ; 20 a function definition. If you press STOP while this light is on you may stop the calculator in the middle of a function.
To reinitialize program execution press DELETE, F-RET in RUN
.
mode, the F-~ET light will go off and the program counter ad-justed to the value it had when the function area of memory was calledO
Calling on a non-existant function from a stored program will cause the calculator to stop execution and turn on the status light. The program counter at this time will point to the program step which contains the name of the function called.

. . .

:
.. . .

lOS8760 Mathematics ROM Module . .
~ hen the mathematics ROM module is plugged into the calculator at the le~t-hand receptacle 94, the user may em-ploy the de~inable keys 91 to perform the additional ~unc-tions indicated by the mathematics overlay shown in Figure 10. All o~ these additional functions are programmable. Any mathematically illegal functions performed either ~rom the keyboard input unit or a stored program will tur~ o~ the STATUS light.
10The units to be used in problems involving trigono-. ., metric functions or vector arithmetic are selected according to the procedure listed in Table A The units speci~ied by .i .
`~ the appropriate indicator light above the de~inable key bloc~.
Table A. Speci~ying Units To Specify Press: Indication-DEGREES TABLE N 1 Deg Rad Grad RADIANS TABLE N 2 Deg Rad Grad GRADS TABLE N 3 Deg Rad Grad It should be noted that the setting o~ degrees, radians, and grads (360 degrees ~ 400 grads) is programmable.
Trigonometric ~unctions o~ angles ~rom 0 up to 5760 can be calculated at full accuracy; however, inverse trigono-metric ~unctio~s are calculated only ~or the principal values oi the-functions:
SiD. ~ X; -gO < ~ < + so i 4 ~ cos~l x; 0 < ~ < + 180 4 ; tan~l x; -90 < ~ < + 90 For instance: cos 150 ~ cos 210 ~ cos 510 ~ tetc.) ~ -.866 .. But: cos ~ .866 - 150 The sin x key is depressed to calculate the SLne of the contents of the x-register and insert the result in the ~-register 1~5~7~V
The cos x key is depressed to calculate the Cosine of the contents of the x-register and insert the result in the x-register.
The tan x key is depressed to calculate the Tangent o~ the contents of the x-register and insert the result in ` the x-register.
The arc key is depressed followed by a trigonometric key to calculate the inverse trigonometric function of the contents of the x-register and insert the result ~n the x-register.
For example, the sin 1 0.5 may be calculated by sequentially depressing the TABLE N, 1, ., 5, arc, and sin 2 keys. Depression of the TABLE N and 1 keys selected the u~its (degrees) per Table A above.
The $ollowing logaritkmic and exp~nential functions may all be performed by employing one or two keystroke opera-tions.
The TABLE N and 4 keys are sequentially depressed in the order named to calculate th~ logarithm (to base 10) of the contents of the x-register and display the result ln the x-register.
The T~BLE N and 5 keys are sequentially depressed in the order named to raise 10 to the power indicated by the contents of the x-register and display the result in the x-register (i.e. lOX). ~or e~ample, the n~mber 0.69897 may be raised to the power indicated by the contents of the x-register by sequentially ~epressing the ~, 6, 9, 8, 9, 7, TABL~ ~ a~d

5 keys. ~;
The ln x key is depressed to calculate the logarithm (to base e, i.e. natural logarithm) of the contents of the ~ ' .

:

, l~S87t;0 x-register and displny the result in the x-register (i.e.
ln x). For example, the 5~ may be calculated by sequen-tially depressing the 2, 3, ln g, t, S, , ~, and ex keys.
The ex key is depressed to raise e (i.e. 2.718....) to the power indicated by the contents of the x-register and display the result in the x-register (i.e. eX).
The xY key is depressed to raise the contents o~
the x-register to the power indicated by the contents o~ the y~register. The result is displayed in the ~-register, and . .
10 the contents o~ the y-register remain unchanged.
The followi~g keys provide capability ~or performing complex and vector arithmetic with a single keystroke opera-tion.
The TO POLAR key is depressed to co~vert rectangular coordinates (consisting of æ and y components in the æ- and y-registers, respectively) to polar coordinates (~ ~ tan 1 y, R a ~)~ ~hen converting ~rom rectangular (cartesia~) to polar coordinates, the calculated angle 4 will be within the range of -180~ 4 <180. The ~inal display is:
te~porary z ------accumulator y tAngle 4) ., .
keyboard æ (Rad~us R) For example, the coordinates 4, 3 (~, y) may be converted to polar form by sequentially depressing the TABLE ~, 1 (these keys select the units, i.e. degrees), 3, t, 4, and T0 POLAR
keys.
The TO RECTANGULAR key is depressed to convert polar coordinates, when the radius (R) and the angle (~) are i~ the x- and y-registers, respectively, to rPctangular coordinates (y 3 R æin ~, x = R Cos ~).

-12g-~05876~

The final display is:
temporary z ------accumulator y (y component) keyboard x (x component) For example, the polar coordinates R = 8, ~ = 120 (or -240) may be converted to rectangular form by sequentially de-pressing the TABLE N, 1, 1, 2~ O, t, 8, and TO RECT~N~ULAR keys.
The final display is:
temporary z accumulator y 6.928 keyboard x -4.000 The ACCUMULATE ~, ACCUMULATE -, and RECALL keys are storage and recall keys associated with the a- and b~data storage registers. These keys provide complete capabilities for vector addition and subtraction.
The ACCVMULATE + key is depressed to simultaneously add the contents of the x- and a-registers together and the ~i contents of the y- and b-registers together. The sums are entered in the a- and b-registers, respectively, while the `~ 20 ~- and y-registers remain unchanged.
The ACCUMULATE - key is depressed to simultaneously subtract the contents of the x-register from the contents of . ::
` the a-register and the contents of the y-register from the contents of the b-register. The remainders are entered into the a- and b-registers, respectively, while the contents of the x- and y-registers remain unchanged.
The TABLE N key permits access to 10 more ROM func-tions than there are definable keys. A list of these func-tions is given in Table B below. The TABLE N key may be fol-lowed by any key. If this key is different from a numeric -129_ 1C~5~7t~0 .
or FMT, no operation is performed.
Table B
TABLE N FUNCTION
:. . ~
, 1 SET DEGREESI
¦ SETS ARGUMENT UNITS FOR
2 SET RADIANS ~
TRIGONOMETRIC FUNCTIONS

4 LoglOx

6 DEGR, MIN, SEC ~ DECI~AL DEGREES

7 DECI~AL DEGREES ) DEGR, ~IN, SEC

8 ~-

9 ROUWD
F~T AUTOMATIC PLOTTER SCALING
The ~irst fi~e functions oi the TABLE N key ha~e al-ready been e~plained above. Howe~er, this key ~ay also be used to perform any o~ the next ~ive ~unctions (namely, angle conversion, calculatio~ ~', rounding a number to a speci~ied power o~ ten, and plotter scaling) not previously described above.
`~ 20 The TAB~E N and 6 Xeys are seguentially depressed in ;~ the order named to convert an angle expressed in degrees, minutes and seconds to decimal degrees. The angle must be entered into the calculator as follows:
: ~ISPLAY
temporary z - (Degrees) ` accumulator y - (Minutes) keyboard ~ - (Seconds) ' The result in dècimal degrees, appears in the x-register, while the y- and z-registers are cleared. This is illustrated as ~ollows:

.

r temporary z -0 . .
accumulator y - 0 keyboard x - DECIMAL DEGREES
The TABLE N and 7 keys are sequentially depressed in the order named to convert an angle expressed in decimal degrees to degrees, minutes and seconds. The angle to be con-verted must be entered into the x-register, and the resultant angle appears as in the previous display. ~owever, the con-tents of the y- and z-registers need not be zero for the in-struction TABLE N, 7.
The TABLE N and 8 keys are sequentially depressed inthe order named to replace the contents of the x-register ~r with X! (where x 0 < ¦x¦ < 69) The TABLE N and 9 keys are sequentially depressed in the order named to round the contents of the y-register to the power of ten indicated by the integer value of the con-tents of the x-register. The rounded number appears in the x-register, while the y-register remains unchanged. For .,:
example, the number 5610.0 may be rounded to 102 (or nearest 100), by sequentially depressing the 5, 6, 1, 0, and t ~ol-` lowed by the 2, TABLE N, and 9 keys.
DISPLAY
accumulator y 5610.000 keyboard x 5600.000 (y rounded) Similarly, the contents o~ the y-register may be rounded to another power (104) by sequentially depressing the 4, TABLE
N, and 9 keys.
DISPLAY
accumulator y 5610.000 keyboard x10000.000 (y rounded) 10587~) A fractional number may be rounded by inserting a negative number into the x-register. For example, the number 0.005 may be rounded to the 10 or nearest 1/100 by sequentially depressing the ., 0, 0, 5, t, CHG SIGN, 2, TABLE N, and 9 keys.
DISPLAY
accumulator y 0.005 keyboard x 0.010 (y rounded) ~ A problem usually encountered when writing a calculator/
: plotter program is that of scaling the available problem variables to coordinates which the plotter can use. The plotter scaling feature to be described, simplifies this typical plotting problem. The TABLE N, FMT, and t or l keys are sequentially de-pressed in the order named to replace the plotter problem variables, which are entered in corresponding x- and y-registers, . with scaled coordinates~ The user variable maxima and minima for this scaling operation are stored in user data storage registers 001-~04. The foregoing sequence of keys controls the plotter (using the scaled variables) in the same manner as FMT, t, or ~ described above.
The DEFINABLE f ( ) key is used to label and "call" an often used (or favorite) function which is programmed as a subroutine in the calculator. The definable function may be executed at any time from the keyboard by depressing the DEFINABLE key, or it may be "called" in a program by inserting the DEFINABLE (key) instruction. The definable function is programmed similar to a "LABEL" subroutine, while the function is executed as a normal subroutine; except it may be "called"
with only one keystroke or program step.
When the DEFINABLE f ( ) ~ey is depressed the program counter searches for a subroutine labeled DEFINE f ( ), . , .

: I .

lOS876~) executes, and returns. This key can be used both in key-board and program control. A user written subroutine to be called by the DEFINABLE f ( ) key can be stored anywhere in the program memory, its first program steps must be LABEL, DEFINABLE f ( ); its last step must be SUB/RETURN. There are no restrictions on the operations this subroutine may performO It is illustrated by the following example:
LABEL
DEFINABLE f ( ) t ~: eX

x.,y CHG SIGN
,~ eX

. " +
~ 2 ..
.
s SUB
: RETURN
Whenever the key DEFINABLE f ( ) is called either in RUN or ~ 20 PROGRAM mode, the hyperbolic cosine of the number in the ...~
x-register is computed and placed in the y-register by this subroutineO
The TABLE N and ChEAR x keys are depressed to clear all numerical storage registers without affecting the a- and b-registers or the x-, y- and z-registers.
A programmed subroutine may be repeated m number of times by inserting the following keys at the end of the sub-routine: TABLE N, SUB RETURN, and n, where n may be ~ny key from O to 9 indicating a data storage register that contains m, and m is equal to the absolute integer value of the con*ents 1~5~376 :
of the n-registerO After the subroutine has been repeated n times, the program exits the subroutine and resumes normal program operation at the program step following the sub-~r.' routine "calling instructions~. The iterative subroutine feature may be added to a "LABEL" subroutine, but when the LABEL subroutine is "called" (during a program) the call instructions must contain 6 program steps. The following partial program shows how to call the LABEL ~ iterative sub-. ~
routine.

Iterative "LABEL~' Subroutine STEP KEY ~E COMMENT

0400 - _ _ _ _ , ; 0401CONTINUE 47' Subroutine ' 1r: CALLS
0403 GO TO 44l 0404~ETuBN I Instructions ., 0405LABEL 31 (6 keys) 0406 ~ 56J
Return from i 0407 ! 35 Subroutine i .

10587~V

Statlstics ROM Module The primary function of the statistics ROM module is to carry out the summations of variables, cross-products, and squares needed as funda-mental quantities in a variety of statistical ana1yses. These summations ;~ are generated in the general data storage user registers, and the user must be careful to avoid any operations which might destroy or alter the contents of these registers. The number of registers used is dependent on the number of variables treated - as defined by the user.
' The registers used are:
:.
. n ~-~
. 2 x2 ~1 . 2 x >2 ~1 - variable; x y >3 ~:xy :~ 4 2 y2~5 ~ 2 - variable; x, y s 2 z-~6 2xz - ~ 7 - 2yz ~ 8 ~ z2~.9 ~3 - variable; x, y, z - 2 a~10 2xa~11 2ya.~12 2za,~13 2 a6~14 ~ 4 - variable; x, y, z, a 2 b~15 ~xb~16 2yb~17 2zb~18 2ab~19 2 b2 :-~20 ~5 - variables; x, y, z, a, b : These are graphically summarized in an easy-to-recall form in this table:

1 _ 1 xl 1 3 l 6Z I 10l 15l _ X, ~ D~

1~ 58 ~'~ O
.
In additionto the user-reg~ters O. - 20 ut~ized as sh~wn above, regîsters 21 ~27 are usedfor co~ection of max~num/m~L~n values, for the "seed" ofthe pseudo-random number generator. This iS shown below:
, xm~l~21 Zm ~ 26 FUN - ~27 A~y registers notused in a spec~ic sequence are : ava~able. For exannple, ~ 2 - variable operations are setup, only reg~ers 0-- -~5 are ~nuse, and 6 ~ ~20 arefreefor other purposes.
When the statist~cs ROM module is plugged into the calculator, the user may employ the definable keys gl to : perfonm the additional functions indicated by the statistics overlay shown in Figure 11. All of these additional functions are programmable and will hereinafter be described key-by-key.

`. ' ' ', .

~S~7~) . ~ .

The VARIABLES K key is used to define the number of variables to be treated, 1 to 5. It must be followed immed-iately by a digit key, 1 to 5. If any other key is depressed . after this key, the STATUS light will be turned on, and the calculator will halt in the display mode. The VARIABLE key and the erroneous key following it are ignored - there is no other action.
` If a correct digit key follows, one or more of the indicator lights will come on, to signal the number of variables selected. The pattern i9:
. . .
1 - variable 1 - light 2 - variable 2 - light 3 - variable 3 - li~ht 4 - variable 1 and 3 - lights 5 - variable 2 and 3 - lights The definition of the number of variables affects subsequent use of the ~ key, MAX/MIN key, and the INITIALIZE and CORRECT keys used in conjunction with it. The number of variables remains unchanged until the VARIABLES key is used to change it, which may be done at any time.

This key is used to accumulate the data summations of variables, cross-products, and squares as outlined previously. The number of summations is determined by the VARIABLES key described above.
That is, the contents of the registers utilizedare:
`~ 1- variable x 2 - variable x, y 3 - variable x, y, z 4 - variable x, y, z, a 5 - variable x, y, z, a, b If the summation key (~ ) is depressed without a previous definition of the number of variables (VARIABLES key followed by digit 1~5), the mlmber of variables is set at 3. It will remain at this setting unless changed by use of ~AP~ABLES
The E key generates the summations, and leaves the contents of x, y, z, a, and b unchanged.
The INITIALIZE and COP~RECT ke s work in conjunction with the snnlmation key. They must precede the ~ key.
When the sequence lNIrIALIZE - ~ is used, all registers (defined by the number of variables set) involved in the summations are cleared to zero. This sequence should always be used before the start of a series of summations on a set of data - otherwise any previous contents of the .

~ l~S87~) .: .
, registers are included in the summations.
If, after depressing the ~ key, it is discovered that the contents of x, y, z, a, or b were erroneous, the user may remove the erroneous data from the summation by depressing CORRECT - ~ keys in that sequence. This will remove all variables, cross-products, and squares of that data from the surnmation. The user may then correct the data and reenter it by depressing the ~ key. Since x, y, z, a, and b are unchanged by the use of ~ (or CORRECT - E ) this is most conveniently done when the erroneous data is still intact - i. e., immediately after ~ . However, if the erroneous data is not discovered until later the user must reenter the erroneou_data in x through b (only x and y if ~ - variable, etc. ), use CORRECT - ~ , and then correct the erroneous data and enter it with the ~ key.

The user must be careful not to do any operations during a summation-sequence on data which will alter the con-tents of any user-registers in~olved in the summation.
However, the contents of any of the summation-registers may be recalled and used at any time, so long as they are not altered.
Once a data-sequence has been entered by use of the ~ key, the summations are available for any desired statistical analysis. For user convenience, four commonly used statistical processes are implemented, to be performed by a single keystroke. The function of these four keys will follow.

The MEAN key computes (from the collected summatians) the arithmetic mean of up to three variables; x, y, and z. If 4 or 5 variables are set, the MEAN key operates on only 3, and does not form the other two means (on a and b).
For various variable settings, the follo~ving computations are made, and appear in the x, y, z registers:
` 1 - variable z 0.0 i Y 0-0 . x x = ~x = (1) n (0) where (1) means "contents of register - 1".
; 2 - variable z 0.0 y y = ~ Y = (3) n (0) x x .

; 3 - variable z z = ~ z = (6) n (O) x x These computations are carriedout and the results appear in x, y, z as shown, without changing the contents of any of the summation registers.

The VARIANCE key computes (from the collected summations) the variance of up to three variables, x, y, and z. If 4 or 5 varlables are set, the VARIANCE key operates on only 3, and does not form the variance of a or b.
The following computations are pe~ormed:
2 _ ( nx) (2) -~
` n- 1 (O) -1 2_ ( ~ y)2 (5)_ (3)2 n = (O) n- 1 (O)- 1 2 ( ~ z)2 (6)2 n = (O) rl- l (0)- 1 .

The results appear in the x, y, z registers in the pattern.
1 - variable 2 - variable 3 -2variable z - 0-0 0-0 ~ z ` Y~ 0.0 ~y ~,2 x ~ 2 ~ x ~x The contents of all summation-registers used in these computations remain unchanged.

"

~ . .

~5876V

; The REGRESSION key performs linear regression (least-squares curve fitting) using the accumulated summations. The computations and .. results are controlled by the variable-setting, as outlined below:
Variable - 1: The regression of a single variable on itself i9 not performed. If REGRESSION is depressed with VARIABLES - 1 set, the STATUS light is turned on, and the calculator halts in the dis~lay mode There will be no other action - the contents of x, y, z, and a~l summation -registers will be uncha~ged.
Variable - 2: The regression of the dependent variable on one independent variable is performed for the equation:
y =aO +alX
The results are placed in x, y, z in the pattern:
z 0.0 y - --aO
x- al The contents of all summation-registers used in the computation remain unchanged.
-Variable - 3: The regression of the dependent variable on two ind~endent is performed for the equation:
, '~ z = aO + alx + a2y The results are placed in x, y, z in the pattern:
:~ Z aO
,~ y- ~ - a2 x al The contents of all summation-registers used in the computation remain unchanged.
Variable 4 - and Variable - 5: This situation is treated as Variable - 3. Four - and 5 - variable regression may be l~erformed by -S user-programming. All summations required are generated by the key when variables are set at 4 or 5.
:. r2 The r2 key generates the correlation coefficient (a measure of s ., :

.'~'' .
,~

16~5876~

goodness-of-fit) for the linear regressions performed by the REGRESSION
key. The computations performed are controlled by the variable setting.
Variable - 1: No computations are performed - the key is ignored.
Variable - 2: The correlation coefficient of the linear regression for:
y = aO + alX
`~ is computed.
The computations performed are best described by introduction of a subsidiary quantity:
~ Xi~ XiXi - ( ~ Xi)( ~ Xj) The correlation-coefficient for variable - 2 is then defined to be:
r2 = (~ xy) :, ~ xx.~yy This result is placed in register x, and y and z are cleared.
Variable - 3: The correlation-coefficient of the linear regression for:

., Z = aO + alx + a2y is computed. This is:
2 al~Xz+a2~yz ~; ~ zz . .
The result is placed in register x, and y and z are cleared.

., The MAX/MIN key is used to collect the maximum and minimum values of the variables x, v, and z. Since these values are stored in registers 21 through 26, tfiey do not affect the summation register~
( ~ key). Thus, MAX/l~ information may be collected on the same data on which summation information is being collected.
The MAX/M~ storage registers 21 through 26 are initialized by the key-sequence INIl'IALIZE - MAX/~N. This results in loading the registers with:

. .

. .

, . . .

.

(~l), (23), (~5) (x, Y, Z)min = 10 (~2), (24), (26) (x, Y, Z)max = -10 All six registers are initialized without regard to the variable-number setting.
When MAX/MIN is depressed, the contents of x (1-variable), x and y (2-variable) or x, y, and ~ (3, 4, or 5-variable) are compared to the stored contents of the max/min registers. If the new value is less than the contents of the associated "min" register, the new value is substituted -if not, the register is left unchanged. The maximums are handled correspond~ngly. Thus, at any time the max/min registers contain the max/min of the input data since the last initialization. This data is not displayed - the user must recall it, as needed, from the appropriate register.
The CORRECT key c7.oes not work in association with the MAX/MIN
key, since any previous values changed are lost irretrievably by the MAX/MIN operation.
t The t key collects summations necessary to compute a t-statistic on data in x and y, and computes and displays the statistic. The overall action is quite different from the ~ key, which collects summations only, and leaves the original data unchanged. In contrast, the t key collects needed summations, computes and presents the t-statistic, and destroys the data just entered.
Further, the t-summations are stored in registers 0, 1, and 2 which are the same registers used by the ~ key. Therefore, use of the ~ and t key cannot be intermixed.
; ~
~ The summations accumulated are:
. ~ .
n ~0 (x _ y)2 - ~ D~ ~2 These are accumulated with each depression of the t key. The three registers may be cleared for starting a new data-sequence by the key-sequence INITIALIZE - t.
If an error i~ made in data entry and the erroneous data is included in the summations by depression of the t key, ~ is convenient to have a means for removing the erroneous data. H~ever, the data has been destroyed in order to present the t-statistic which is computed after each key depression. Whell the user disco~ers the d~ta error, he may reenter the erroneous data in x and y. Then, depression of CORRECT - t will remove the data from the summation. He may then reenter the correct data ~nd include it by depressing the t key.

l~lS~376iO

The computations performed from the summations are:
D = 2D = ~ (x y) D
, ~
~D 1¦ (X y)2 ( ~ (X - y n(n- 1) D is placed ~n the z - register, n in y, and t in x.

X

The X key accumulates the summations and then computes and presents the chi-squared statistic at each depression of the key. It's general operation is the same as the t key in that:

1. 2 Summations are accumulated in O and 1 so that use of X and ~ cannot be mixed.

2. The presentation of results after each key depression : destroys the data entry in x and y. Correction for erroneous . data can be accomplished ~y reentering the bad data and then . depressing CORRECT - X~.

3 The regi~ters used (0 and 1) are cleared by depressing The summations accumulated are:

. .
.. n ~0 1~- ~1 ~n the normal context for use of chi-square the "obser~ed" value is in x, the "expected" value in y.
., The RANDOM key causes the computation of a sequence of pseudo-random numbers, uniformly distributed in the interval O_RN21. The method used is congruential products. It is neces-sary for the user to provide a "seed" for the sequence before using the RANDOM key. A given seed will produce the same se-quence of pseudo-random numbers each time it is used.
The seed should be stored by the user into register 27.
After each depression of RANDOM, the newly-generated pseudo-random will be stored in register 27 as a new seed, and the number will also be presented in the x - register. They y and z registers remain unchanged.

~ lOS87tiV

The initial seed provided by the user should be selected with certain rules in mind in order to obtain acceptable pseudo-random number properties. They are:
1. Enter a decimal fraction consisting of 12 digits (i.e., enter a complete number including guard-digits, even though they cannot be seen).
; 2. The number should be odd.
3. The number should not be evenly divisible by 5.
The LOGlox, LOGex, and eX keys provide the specified mathematical function on the argument in x, and the result is leit in the x-register. No other registeri are changed.

:~j ,.: .
~: .
, . . .
.~`
:, ~OS8760 Ty ~ Module .~
When the typewriter ROM module is plugged into the calculator, ~he keyboard input unit is redefined as shown in Figure 12 so tha~ the entire keyboard of a properly interfaced typewriter such as the Facit ~odel 3841 (hereinafter referred to as the Model 61) may be completely controlled by the calculator. The Model 61 is capable of performing three basic operations:
1. Type data contained in the calculator's X-register.
2. Type alphameric messages and control typewriter functions.
3. List programs contained in the calculator memory.
These operations are accomplished by calculator instructions given either from the keyboard or as program steps in a proper sequence. In this section, these instruction sequences will be described. Numerous examples are provided so that the user will be able to manually key the instruction s sequences and observe the results. In normal operation, the instruction se~uences would be placed in a program.
. ~
Table C provides, in brief form, the instruction sequences used to operate the Model 61. The table is not provided to teach typewriter operation; rather, it is provided for quick reference once the instruction sequences are under-stood All of the Model 61 instruction sequences presented in this section can be reduced into component parts consisting of one or more calculator instructions. For example, all of the ~odel 61 instruction sequences contain the two calculator instructions FMT and 2.
The instructions FMT and 2 service the special purpose of redefining the following calculator instructions so that they will be u~derst~od only by the typewriter. The two instructions, when thought of as a component part of an instruction sequence, can be considered as "the type-writer address" Although these two instructions will be shown as part of each of the following instruction sequences, their meaning will not be xplained gain.

:~ ' ' , .
''.' ' ' TABLE C

~! COMMAND SET
Instruction Sequence:
Typing a Number ~ Types the number in the x-register ¦ in a notation and location speci~ied by 1. FMT 2 PRINT ¦ the last w.d. instruction.
2. FMT 2 w.d. w specifies field width (location).

3. FMT 2 w.d. The number will be right justified in the PRINT
field. At turn-on, the calculator assumes a w of 20.
d specifies the number of digits to the right of the decimal point or specifies floating point.
Alphanumeric Typing FMT 2 FMT Message FMT
~ Allows the user to type labels and headings. Also ;; allows control of all keyboard functions except margin setting. Messages may include print instructions. Calculator keyboard has two modes, shifted and unshi~ted (see keyboard diagram on the back page).
Listing A Program FMT 2 List Lists the con$ents of the calcula~tor's memory be-ginning with the present location of the program counter and continuing until an end statement is encountered in the memory or stop on the calculator keyboard is pressed. The listing includes address location, key code, and key mnemonic.
All commands are available on program or manual request.

-.
.. . . .
.

1~5876~) The instruction sequence FMT, 2, w.d, PRINT allows the user to type the data contained in the calculator's X-register. In this sequence, the notation (fixed or floating point) of the typed data can be specified. In addition, the location where the data will be typed on the typewriter platen may also be specified. This instruction sequence consists of the following component parts:
FMT 2 - Typewriter address.
w.d. - Specifies the location and notation of the typed data.
PRINT - Causes the data point to be typed.
The instruction sequence is initiated with the typewriter address and is terminated by the PRINT instruction. The component parts of the instruction sequence have the following meaning for the typewriter.
w.d. - This component of the instruction sequence allows the location and notation of the typed data to be specified.
The w part of the component specifies the location; the d part specifies the notation. The decimal point in the com-ponent delimits the two parts. Although a w cannot be given without also giving a d, they are best explained separately.
w specifies the field width (w) in which the data is to be typed. The left side of the field is defined by the location of the typewriter carriage when the data is typed. The right side of the field is defined by the value of w. For example, if the typewriter carriage were sitting ten spaces from the left margin setting and w was specified as twenty, then after the data has been typed the carriage will be located thirty spaces from the left margin setting.
Any data typed in a field, will automatically be typed in the right most spaces (right justified) of the field. The following drawing illustrates the number 123.45 right justified in a field of ten.
. ~ Ll~
-. w = 10 The field must be large enough to contain the typed data, including the decimal point and any signs that may be present :

, :
,. . .

lOS87~0 in the data point. If, for example, the data point were the digit one, a w of one would be large enough to contain the data point; however, if the data point were a negative one, a field width of two would be required.
If the field is not large enough to contain the data point, the data will not be typed; instead, the entire field would be filled with asterisks to notify you that the data point could not be fitted into the specified field width.
W may be specified as any number between one and sixty-three (inclusive). Since the data point is always right justified in the field, you will use w to place the data point at the desired loca ion on the typewriter platen.
Do not, however, set w so large that the data, when typed, exceeds the right margin setting. If the right margin is exceeded, the program will be stopped at the memory location following the PRINT instruction (explained later) that exceeded the right margin setting and the STATUS lamp will be lit.
When a w instruction is given, the value is automatically stored in the calculator. A w instruction, once given, need not be given again in a program and may be used any number of times when succeeding FMT, 2, PRINT (explained later) instruction sequences.
The value selected for w is lost when the calculator is switched OFF. When the calculator is switched ON
a w of twenty is automatically stored.
, .~
The d part of the w~d component allows the user to control the mode of the calculator display from a program and, therefore, the notation (fixed or floating point) of the typed data.
In this instruction sequence, when the data in the calculator's X-register is typed, it will be typed as it is displayed in the X-register. In order to provide the capability of specifying the notation (fixed or floating point) of the typed data, this instruction sequence is capable of con-trolling the format of the calculator display. This is provided by the d part of the w~d component.

- lOS~7~0 .
,~ , The following table shows the relationship between d and ` the notation of the typed data.
d _ TyPed Notation ; ~ decimal part and decimal point are suppressed 1 one digit to the right of the decimal point is typed.
2 two digits to the right of the decimal point are typed.
.,~ .

. ~ .
9 nine digits to the right of the decimal point are typed.
decimal point) the data will be typed in floating point notation.
` A data point in the calculator's x-register will always contain a decimal point; however, if the data point is displayed with no digits to the right of the decimal point (e.g., 10.3, the data, when typed, will be typed without the decimal point.
.,:
The d part of the w.d component is most easily thought of as a programmable FIX ( ) - FLOAT instruction. It has the same effect as those keys on the calculator display. Also, all of the rules of operation con~erning overflow and under-flow applicable to the FIX ( ) and FLOAT keys apply equally to d.
In the case of overflow, if the calculator display contains nine digits to the right of the decimal point and a data point containing two digits to the left of the decimal point is entered in the x-register, the register will overflow and display the data point in floating point notation.
Exactly the same situation can occur with d. If you specify a d of nine and the data point in the x-re~ister overflows, then the data point will be typed in floating point notation.
There is a potential problem in the interaction between w and d that the operator should be aware of. For example, assume that w has been set for two and d has been specified as zero. If the data point in the x-register over-flows and an attempt is made to type the data point, the field width of two will not be large enough to contain the data point in floating notation and two asterisks will be typed.

j 1058,~60 .., Whereas an overflow condition which exceeds the field width will cause asterisks to be typed, an underflow condition will not. In an underflow condition, the data point in the x-register has become so small that the d specification does not allow the data point to be dis-played with enough accuracy. Like the overflow condition, the data point is, in essence, not typed. For example, assume the ~alue of the data point in the x-register were 1.23 x 10 1 and d were specified as zero. When the data point is typed it will be typed as zero.
The operator should be aware of the range in which the typed data will lie and set the w.d specification so that neither underflow or overflow occur. If the range is likely to be very great, the field width and d should be set so that the data point is typed in floating point notation (16 . . ).
Because d is essentially stored by changing the format of the calculator display, the value for d remains unchanged until the display format is changed. This can be done by giving another d instruction or by manually pressing the FLOAT or FIX ( ) keys. If, for example, you specify a d of two, stop the program and press FLOAT, then, when the data is typed it will be typed in floating point notation.
The PRINT component of this instruction sequence causes the typewriter to type the data contained in the calculator's x-register. The data will be typed in the location and notation specified by the last w.d component given.
When a FMT, 2, w.d, PRINT instruction sequence has been executed, the instruction sequence will automatically be terminated and the typewriter address reset. This means that if you wished to type the same data twice, the entire instruction sequence (less w.d, explained later) must be given again.
In order to provide maximum programming flexibility, certain component parts of the FMT, 2, w.d, PRINT instruction sequence may, optionally, be omitted from the instruction sequence. The following variations of the sequence are allowable:
FMT, 2, w.d, PRINT - Type the data in the x-register in a specified location and notation.
FMT, 2, w.d - Establish a field width (w) and notation (d) which will be used later in the program by one or more FMT, 2, PRINT
instruction sequences.
FMT, 2, PRINT - Type the data in the x-register in a location and notation stored earlier in the program.

r :' . .

1~3S&7f~

.
The FMT, 2, w.d instruction sequence allows you to save program steps by specifying w and d only once in a program and reusing them any number of times with succeeding FMT, 2, PRINT instruction sequences.
The PRINT instruction in these sequences will automatic-ally terminate the instruction sequence and reset the typewriter address. In the case of the FMT, 2, w.d instruction sequence, the instruction sequence is not terminated; however, the next calculator instruction, in addition to performing its normal function will terminate , the sequence.
The use of the FMT, 2, w.d, PRINT instruction sequence is illustrated by the following example:
A piece of paper 8-1/2" or wider is placed in the typewriter and the margin stops, paper guide and carriage set as shown below:
Left Margin Right Margin Stop ~ ____tStop i 1 2 3 6 7 . O O O O . . . O O
Paper Guide 1 2 3 4 Paper Bail's o a o o o . . . Graduated ` Typing Scale -' O O O O O . . .
Card Holder The number one thousand is keyed into the calculator's ~x-register, and floating point display is selected.
,~DISPLAY: 1.000000000 03 ~ X
.
PRESS: FMT, 2 1 3 2 DISPLAY: 1000.00 ---~X
The w (13) was stored and the d (2) changed the display.
The instruction sequence is not terminated, however, and a PRINT instruction may be added:
.
PRESS: PRINT
:..' TYPE-OUT:
, w = 13, d = 2 " 1000.00 ,~~~~~~~~~`ï~ - 1` 2 3 4 0 0 3 0 0 0 . . .
f~
`:

~. .

~ 5~760 The red pointer mark on the CARD HOLDER points to thirteen on the PAPER BAIL'S graduated typing scale, not fourteen as one might expect. That is hecause the scale starts at zero, not one.
The PRINT instruction has terminated the instruction sequence. To type the data again will require another instructioh sequence:
PRESS: FMT, 2, PRINT
, TYPE-OUT:
~ w = 13, d = 2 "` 1000.001000.00 0 0 0 6 0 0 . . .
. ~
The FMT, 2, PRINT instruction sequence has used the w and d stored in the preceding FMT, 2, w.d instruction sequence.
The type-out is right-justified on the twenty-sixth space as the left side of the field is defined by the location of the carriage when the data is typed.
It should be noted that a FMT, 2, w.d PRINT
instruction sequence does not contain the capability of a carriage return/line feed instruction. This capability does exist, however, as explained below.
A FMT, 2, W. d instruction sequence is terminated by the next calculator instruction given. In addition to terminating the FMT, 2, w.d instruction sequence, the instruction will be performed in its normal manner.
`'` PRESS: FMT, 2 j 1 3 . , ~:i DISPLAY: 1.000000000 03 - X, Y
This instruction sequence has specified floating point notation; however, this display can be manually over-ridden with the FIX ( ~ - FLOAT keys:
PRESS: FIX ( ) 2 DISPLAY: 1000.00 - X

, .

~0587f~0 :
PRESS: FMT, 2, and PRINT
TYPE-OUT: w = 13, d = 2 ,. .~ ., ^ ~ . , 1000.00 1000.00 1000.00 ' 1 2 3 34 :`.................... O O O O ,~0 . . .
.. ~1 .J~ Data in the calculatox's x-register can be typed without a decimal point. This is done by specifying a d of zero:
`. PRESS : FMT , 2, 4 , ., 0 , and PRINT
~ TYPE-OUT: w = 4, d = 0 ,' :'" 1000.00 1000.00 1000.00100 ' O O O O O ~
~, The data point just typed was typed in a field width of four, just large enough to contain the data. Spaces - between this data type-out and the one previously typed ` could have been provided by specifying a larger field width, w.
~r Asterisks will be typed across a field that is not large enough to contain the data.
PRESS : FMT , 2 , 3 , ., 0 , and PRINT
,1 TYPE--OUT : w = 3, d = 0 ,, -- 1000.00 1000.00 1000.001000***' ,.

;~ 0 0 0 0 0 6 0 . -'.'"

~, :
.

` lOS87~0 .
The FMT, 2, FMT, MESSAGE, FMT instruction sequence allows labels and headings to be typed for data. With this instruction sequence, the user can control both characters on each typewriter key and control all typewriter functions directly from the calculator, either by stored program step or manually, from the calculator keyboard.
The instruction sequence consists of the following component parts:
FMT 2 - Typewriter address FMT - Established the TYPING
r~SSAGES instruction sequence.
MESSAGE - Your label or heading FMT - Terminates the instruction sequence.
Other calculator instructions which terminate this instruc-tion sequence are:
LOAD STOP * PRGM FLOAT
RUN KEYLOG RECORD END *
. .
ATEpK FIX ( ) PRGM LIST

* Programmable instructions.
i In the MESSAGE component of this instruction sequence, one '~ programmable calculator instruction will control one typewriter key. Which character on the typewriter key will be typed or which typewriter function will be performed, will depend on the mode of the calculator keyboard when the instruction is given. In the MESSAGE component of this ;~ sequence, the calculator can be in one of two modes, unshifted or shifted.
f When the instructions FMT, 2, FMT are given, the , calculator keyboard will automatically be in the uNshifted mode. In this mode of operation, the calculator instructions and the typewriter character typed or function performed have the correspondence shown by the characters and symbols included within the keys of Figure 12.
'~`
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.
1(3 587~V
.
The unshif-ted ca7culator ke~bnard can cnntrol the typ~writer's ~-numbers and capital alphabet. In addition, the functions TAB
CLEAR, TAB, CR/LF (Carriage return/Line feed), SPACE, BLACK
RIBBON may also be performed. The FMT instruction and the blank keys shown in the diagram will terminate the instruction sequence. Three instructions (PRINT, TAB and SHIFT) avail-able on the unshifted calculator keyboard require special mention.
:~:
A PRINT instruction placed in a MESSAGE will cause the data in the calculator's x-register to be typed. The data will be typed in the location and notation specified by the last w.d given. A w.d may not be placed in a MESSAGE; however, they are stored when they are given and automatically recalled and used with a PRINT instruction placed in a MESSAGE.
.
~ A TYPING MESSAGES instruction sequence will not affect the ;~ contents Gf the calculator's display registers. Therefore, data can be placed in the x-register and typed with a PRINT
,- instruction placed in this instruction sequence.
`: Giving a TAB instruction will cause the typewriter carriage ;i to move either to the next tab set or to the right margin ` setting. If the carriage is less than two spaces from a tab setting and a TAB instruction is given, then that tab -' setting will be ignored by the typewriter and the carriage will move to the next tab setting or right margin setting.
The SHIFT instruction allows one to change the mode of the ~ calculator's keyboard. If the calculator keyboard were un-.~i shifted and a SHIFT instruction was given, then the calcula-~I tor keyboard would be in the shifted mode. In the shifted : mode of operation, the calculator instructions and the ` typewriter character typed or the function performed have the correspondence shown by the characters and symbols printed below the keys of Figure 12.

105871ij0 The shifted calculator keyboard can control the typewriter's small l~tter alphabet and the sylllbols abpve the numbers and : .n add1tion, the functions TAB CLEAR ALL (CLEAR ALL TABS), TAB SET, CR/LF, SPACE, BACK SPACE. The FMT instruction and the blank keys shown in the diagram will terminate the in-struction sequence. The operation of the PRINT and SHIFT
instructions on the shifted calculator keyboard are the same as on the unshifted keyboard. The two instructions that require special mention on the shifted calculator key-board are the CR/LF instruction and the RED RIBBON instruction.
The CR/LF instruction will cause the typewriter to perform a carriage return and line feed. In addition, this instruction will cause the calculator keyboard to become unshifted.
A RED RIBBON instruction will cause the typewriter to type in red. Once red ribbon is selected, only two things can reset the red ribbon, they are, giving a BLACK RIBBON instruction (available on the calculator's unshifted keyboard) or switching the calculator interface OFF. Terminating the TYPING MESSAGES
instruction sequence will not reset a RED RIBBON instruction~
THE MESSAGE component of a TYPING MESSAGES instructlon sequence may be any number of program steps (limited only by the size of the calculator memory). However, a typewritten line must not ~` be allowed to exceed the right margin setting. If the right margin setting is exceeded, the program will stop at the second . memory location following the instruction that exceeded the right margin setting and the STATUS lamp will light.
' (It should be noted that if the right ; margin setting is exceeded in a typing data instruction sequence, the program will stop at the memory location imme-diately following the PRINT instruction that exceeded the right margin setting.) . . , :~

lOS87t;0 Because of the two things an operator must keep track of, an example of TYPING MESSAGES is potentially confusing. For example, if the instruction "A" were placed in a MESSAGE, the operator could not easily predict whether the character typed would be "A" or "a", further, the color would be unknown.
Which character and which color would, of course, depend on whether the calculator keyboard were shifted or unshifted and the status of the ribbon color. The following format makes keeping track of these two things easier and, therefore, helps clarify the examples.

t :, !
s~eP _ BR r _ PROG. INST. KEY COD~ X Z
_~ L ~: ~
_~ ~

' ~, The format is essentially the standard programming pad format with five additional columns: B, R, S, U and PROG INST.
Mark the B and R column so that you will know the status of the ribbon color, red or black. In the S and U columns, you can mark the mode of the calculator keyboard when the instruction is given - S for shifted, U for unshifted. In the PROG INST column you can record the typewriter instruc-tion that, considering the mode of the calculator keyboard, corresponds to the instruction in the KEY column. In the following examples, the PROG INST column will not be used except fos typewriter instruction sequences.

.~
'' lOSt37f~
To type messages the typewriter's LEFT MARGIN STOP and PAPER
GUIDE are set to zero. The typewriter carriage is positioned against the LEFT MARGIN STOP. A piece of paper 8-1/2" or wider is placed in the typewriter and the RIGHT MARGIN STOP
set to seventy. The number 123.45 is keyed into the calcu-lator's x-register and a display mode of FIX ( ), 3 selected.
In this example, the MESSAGE "The value is" wiI1 be typed followed by the data just entered into the calculator's x-register. This is accomplished by keying in the following instructions:
., STEP _ 3R iU _ PROG. IN5T. KEY CODE X Y
0000 FMT FMT 42 123.450 --2 __ _ ---2 ~ 02 ~ ~
.: 4 _ _ _ _ 2 2 02 123.45 5 ~----~FM2T F MT 42 :~ 7 F MT F MT 42 ,.
.,. 8 _ _ B L K R I B S/ R 7 7 ~ 9 CR/LF CLR 20 ..
r 0010 _ T XTO 23 ¦
1 _ _ $H I FT UP 27 ..

2 _ _ 5:ACE CNT 60 , v INT 64 _ . ~ 6 _ . a A 62 0020 9 _ sP~Ce 1 /X 17 .
~,, --1 _ 65 ..
.1 2 _ s YTO 40 . 3 . PRINT PNT 45 ..
_ FMT FMT 42 TYPE-OUT: The value is 123.45 Steps 0000-0004 The ~ m w.d instruction sequence established a field of seven with two digits to the right of the decLmal point.
The data point (123.45) requires a field width of six;
setting the width to seven will ensure that there will be a space between the data and the last character typed.

~ 1058760 Steps 0008-0009 The BLK RIBBON instruction in step 0008 will ensure that the MESSAGE in this example is typed in black. Prior to that time the status of the ribbon color was unknown; therefore, neither the B or R column was filled in.
The CR/LF instruction in step 0009 will ensure the MESSAGE
is typed against the LEFT MARGIN STOP.
:
.`
The next example performs the same type of operation with the instruction sequences used in a slightly different manner.
In this example the TYPING MESSAGES instruction sequence will be used to type the message "123.45 squared =" in black and then set the red ribbon. Next a TYPING DATA instruction sequence is used to set a field width of ten with four digits to the right of the decimal point, and type the data contained in the x-register.
If the number 123.45 is not still in the x-register from the last example, it is entered into the x-register and the fol-lowing calculator keys are depressed in the order given:
"`
., ., STEP 8RSUPROG. INST. KEY CODE ..
2 0000 _ _ _ UP27 123.45 123 is 1 _ _ _ X 36123.4515239 9025 2 DN 2515239.9025 ., 3 _ _ FMT FMT 42 ..
4 2 2 02 .. ..
S _ _ FMT Fl/IT 42 .. ..
6 _ _ CR/LF CLR 20 . ..
87 _ _ 2 1 01 . . _. _ 00109 _ _--5- -~ =

3 _ SPACE CNT 47 ... _ 4 SH I FT UP 27 .. ..
S _ s YTO 40 _ 7 _ u 1 IX 14 8 _ a A 62 .. .
9 r a 13 .. ..
0020 _ e E 60 .............
l d D 63 ,. ., 2 _ _SP~CE CNT 47 4 _RED RIBS/R 77 FMT FMT 42 .. ..
6 _ _ FMT FMT 42 .
7 _ _ 2 2 02- ..
3 _ 1 1 01 :" 0030 _ = 21 " . . _ 1 _ _ 4 4 04 ,............. ,.
2 _ P~ I NT PNT 45 . _ _ .. . =

. .
, :' :
,. , ~; . .-~ j , l~S~7~
.

In the last example, a BLK RIBBON instruction was given. Since then, the ribbon color has not been changed. Therefore, in step 0003, the B column can be filled in even though a BLK RIBBON instruction was not given.
At step 0024 a RED RIBBON instruction is given so that the data in the x-register will be typed in red. Remember, the red ribbon can be reset to black ribbon by two things only, giving a BLK RIBBON instruction or turning the typewriter interface OFF.
TYPE-OUT: 123.45 Squared = 15239.9025 It may be noticed that there is no space in the type-out between the "="
and the data. That can be corrected in two ways:
1. Setting the w specification to eleven.
2. Inserting a SPACE instruction immediately following the "=" instruction.
The instruction sequence FMT, 2, LIST allows the user to list a program contained in the calculator memory. The listing will be typed in a column format with each line consisting of the memory location, the mnemonic of the instruction stored in the location and the key code of the instruction.
The listing will begin at the location of the program counter when this instruction sequence is given and will continue until either an END in-struction is given or STOP on the calculator keyboard is pressed.
(It should be noted that if the ribbon color status is red, the listing will be typed in red ) This may be illustrated by entering a typewriter exerciser program into the memory of the calculator and then:
PRESS: END FMT 2 LIST
TYPE-OUT:

0001-- *---36 0028-~FL---54 0031-~LR---20 . . .

" 1058760 KEY CODES AND MNEMONICS
A11 of the keys of the keyboard input unit and their associated octal keycodes and mnemonics are listed in Table D below. Every key has only one keycode and only one mnemonic (if it has a mnemonic), regardless of how many different functions it may be used to perform. The keycodes for the FLOAT, FIX ( ), RUN, PRGM, KEY LOG, LIST, LOAD, RECORD, BACK STEP, and STEP PRGM keys are applied to the CPU in seven-bit binary form. Since these keycodes are used only to control the mode of the calculator, are not programmable, and are never printed out by the output printer unit, they have no associated mnemonic. All of the remaining keycodes are applied to the CPU in six-bit binary form, are pro-grammable, and have a mnemonic that may be printed out by the output printer unit.

..
`'' ! ' .
`' .
~ ' .

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~ -161-..

1~5876 i TABLE D
r B Y KEY
. KEY CODE MNEMONIC KEY CODE MNEMONIC
; 0 oo 0 GO TO 44 GTO
1 01 1 æ~F~ 45 PNT

' 3 03 3CONTINUE 47 CNT
4 04 4IF x-y 50 X-Y
; 5 05 5LABEL 51 LBL
6 06 6IF x<y 52 X<Y
7 07 7IF x>y 53 X>Y

. x 12 XSQ ~ 56 a 13 a PAUSE 57 PSE
. b 14 b E 60 E

: F 16 F A 62 A
l/x 17 l/X ~ 63 D
. CLE M 20 CLR int x 64 INT
, 21 . I 65 ROLL t 22 RUP B 66 B
x~() 23 XTO x~() 67 XFR
:~ y~() 24 YE ~ 70 M

~ ENTER EXP 26 EEX L 72 L
.' - t 27 UP N 73 N
. x~y 30 XEY H 74 H

~` CHG SIGN 32 CHS ~ 76 ~-:.~ + 33 + EEI~E~ 77 S/R
` - 34 - RECORD 102 . 35 DIV LOAD 103 . X 36 x LIST 104 CLE M x 37 CLX BEY LOG 105 Y3() 40 YTO PRGM 106 F~T 42 FMT FIX () 110 IF FLAG 43 IFG FhO~T 110 i ' -1~2-. , .~- , . .

~7~0 PROC~SSING KEYCODES
The manner in which ~eycodes entered into the CPU ~rom the keyboard input unit or from the program storage section o~ the memory unit are processed is shown and described in the keycode processing ~low chart o~ Figure 13. Once the calculator is turned on, it operates in the display routine until a key is depressed. I~ a FLOAT, FIX (), RUN, PRG~, KEY
LOG, LIST, LOAD, RECORD, BACK STEP, or STEP PRG~ key (each having a seven-bit keycode) is depressed, the calculator operates in a director routine to determine which of these keys w~s depressed and thereupon selects the routine for per-~orming the function required by that key. Upon completion o~ the selected routine, the calculator re~erts to operation in the display routine.
If any other key (each having a si~-bit keycode), ex-cept the CONTINUE key, i~ depressed and the PRGM key has not ~een depressed or has been ~ollowed by the R~N key, the cal-culator operates in the interpreter routine to determine - ~hich si~-bit keycode it has received and to select the ap-propriate routine for per~ormi~g the ~unction requixed by that six-bit keycode. Upon co~pletion o~ the selected routine the calculator reYerts to operation in the display routine.
I~ the CONTINUE key is depressed and t~e PRG~ key has ` not been depressed or has been followed by the R~ key,.the .
calculator operates in a ~etch routine to sequentially ~etch keycodes~ as designated by the user program counter, from the pxogr~m storage section o~ the RW~. Each ~etched keycode is interpreted and-the routine for performing the function re-; quired thereby selected in the same manner as if the ~etched ~eycode had been recei~ed ~rom the key~oard input unit.
: r 'I .
~ -163-,~
;

~owever, upon completion of the selected routine the calculator reverts to the ~etch routine unless the ~etched keycode was a STOP, END, or PAUSE (i~ the execution o~ the PAUSE is im-~ediately ~ollowed by depression o~ a key), in which cases the calculator reverts to operation in the display routine.
I~ any key havin~ a six-bit keycode is depressed and the PRG~ key has been depressed and has not been followed by the RUN key, the calculator operates in a store routine to store the six-bit keycode received from the keybo~rd input unit as a program step in the progra~ storage section o~
the R~M. Upon completion o~ this storage operation the cal-culator reverts to operation in the display routine I~ the EEY LOG key has been depressed and has not been ~ollowed by the RUN key or the PRG~ key, the calculator also prints out each six-bit keycode received ~rom the keyboard .input unit in any o~ the above-mentioned cases.
The display routine, the director routine, the inter-preter routine, the routines ~or per~orming the various ~unctions required by the six-bit and seven-bit keycodes, and other routines used by the calculator are shown and de-scr~bed in Figures 14-135.

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~ -164-. .
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lOS~7~;0 BASIC INSTRUCTION SET
Every routine and subroutine of the calculator comprises a sequence of one or more of 71 basic sixteen-bit instructions listed below. These 71 instructions are all implemented serially by the micro-processor in a time period which varies according to the specific instruction, to whether or not it is indirect, and to whether or not the skip condition has been met.
Upon completion of the execution o~ each instruction, the program counter (P register) has been incremented by one except for instructions JMP, JSM, and the skip instructions in which the skip condition has been met. The M-register is left with contents identical to the P-register. The contents of the addressed memory location and the A and B registers are left unchanged unless specified otherwise.
Memory Reference Group The 14 memory reference instructions refer to a specific address in memory determined by the address-field <m>, by the ZERO/CURRENT
page bit, and by the DIRECT/INDIRECT bit. Page addressing and indirect addressing are both described in detail in the reference manuals for the Hewlett-Packard Model 2116 computer (hereinafter referred to as the ~P 2116).
The address field <m> is a 10 bit field consisting of bits O
through 9; The ZERO/CU~RENT page bit is bit 10 and the DIRECT/INDIRECT bit is bit 15, except for reference to the A
or B register in which case bit 8 becomes the DIRECT/I~DIRECT
bit. An indirect reference is denoted by a <,I> following the address <m>.
REGISTER REFERENCE OF A OR B REGISTE~: If the location <A> or ~B> is used in place of <m> for any memory reference instruc~ion, the instruction will treat the contents o~ A or B exactly as it would the contents of location <m~. See the note ~elow on the special restriction for direct register reference of A or B.
ADA m,I Add to A. The contents of the addressed memory location m are added (binary add) to contents o~ the A register, and the sum remains in the A register. If carry occurs from bit 15, the E register is loaded with OOOl, otherwise E is left unchanged.
ADB m,I Add to B. Otherwise idelltical to ADA.

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:

lOSt3760 Memory Reference Group (continued) CPA m,I Compare to A and skip if unequal. The contents of the addressed memory location are compared with the contents of the A register. If the two 16-bit words are different, the next instruction is skipped; that is, the P and M
registers are advanced by two instead of one. Otherwise, the next instruction will be executed in normal sequence.
:
CPB m,I Compare to B and skip is unequal. Otherwise identical to CPA.
~ LDA m,I Load into A. The A register is loaded with the ; contents of the addressed memory location.
LDB m,I Load into B. The B register is loaded with the contents of the addressed memory location.
STA m,I Store A. The contents of the A register are stored into the addressed memory location. The previous contents of the addressed memory location are lost.
STB m,I Store B. Otherwise identical to STA.
IOR m,I "Inclusive OR" to A. The contents of the addressed ;~ location are combined with the contents of the A register as an "INCLUSIVE OR" logic operation.
ISZ m,I Increment and Skip if Zero. The ISZ instruction adds ONE to the contents of the addressed memory location. If the result of this operation is ZERO, the next instruction is skipped; that is, the P and ~ registers are advanced by TWO instead of ONE. The incremental value is written back into the addressed memory location. Use of ISZ with the A or B register is limited to indirect reference; see foot-note on restrictions.
.
AND m,I Logical "AND" to A. The contents of the addressed location are combined with the contents of the A register as an ~'AND" logic operation.
., DSZ m,I Decrement and Skip if Zero. The DSZ instruction ; subtracts ONE from the contents of the addressed memory location. If the result of this operation is zero, the next instruction is skipped. The decremented value is written back into the addressed memory location. Use of DSZ with the A or B register is limited to indirect reference; see footnote on restrictions.
:
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. ~ ~
., :.' lOS876V

, JSM m,I Jump to Subroutine. The JSM instruction permits jumping to a subroutine in either ROM or R/W memory. The contents of the P register is stored at the address contained in location 1777 (stack pointer). The contents of the stack pointer is incremented by one, and both M
and P are loaded with the referenced memory location.
JMP m,I Jump. This instruction transfers control to the contents of the addressed location. That is, the referenced memory location is loaded into both M and P registers, effecting a jump to that location.

Shift-Rotate Group The eight shift-rotate instructions all contain a 4 bit variable shift field <n> which permits a shift of one through 16 bits;
that is, 1 < n < 16. If <n> is omitted, the shift will be ~ treated as a one bit shift. The shift code appearing in bits i~ 8,7,6,5 is the binary code for n-l, except for SAL and SBL, in which cases the complementary code for n-l is used.

AAR n Arithmetic right shift of A. The A register is shifted right n places with the sign bit (bit 15) filling all ; vacated bit positions. That iSJ the n+l most significant bits become equal to the sign bit.
, ABR n Arithmetic right shift of B. Otherwise identical to AAR.
,~!i, SAR n Shift A right. The A register is shifted right n places with all vacated bit positions cleared. That is, the n most signiflcant bits become equal to zero.
SBR n Shift B right. Otherwise identical to SAR.
SAL n Shift A left. The A register is shifted left n places with the n least significant bits equal to zero.
SBL n Shift B left. Otherwise identical to SAL.
RAR n Rotate A right. The A register is rotated right n places, with bit O rotated around to bit 15.
; RBR n Rotate B right. Otherwise identical to RAR.

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10587~

Alter-Skip Group The sixteen alter-skip instructions all contain a 5-bit variable skip field <n> which, upon meeting the skip condition, permits a relative branch to any one of 32 locations. Bits 9,8,7,6,5 are coded for positive or negative relative branching in which the number <n> is the number to be added to the current address, (skip in forward direction), and the number <-n> is the number to be subtracted from the current address, (skip in negative direction). If <n~ is omitted, it will be inter-preted as a ONE.
<n>=O CODE=OOOOO REPEAT SAME INSTRUCTION
<n>=l CODE=OOOOl DO NEXT INSTRUCTION
<n>=2 CODE=OOO10 SKIP ONE INSTRUCTION
<n>=15 CODE=Ollll ADD 15 TO ADDRESS
<n>=-l CODE=lllll DO PREVIOUS INSTRUCTION
<n>=-16 CODE=10000 SUBTRACT 16 FROM ADDRESS
<n>=nothing CODE=OOOOl DO NEXT INSTRUCTION
The alter bits consist of bits 10 and bits 4. The letter <~
following the instruction places a ONE in bit 10 which causes the tested bit to be set after the test. Similarly the letter <~j will place a ONE in bit 4 to clear the test bit. If both a set and clear bit are given, the set will ta~e precedence.
Alter bits do not apply to SZA, SZB, SIA, and SIB.
SZA n Skip if A zero. If all 16 bits of the A register are zero, skip to location defined by n.
SZB n Skip if B zero. Otherwise identical to SZA.
RZA n Skip if A not zero. This is a "Reverse Sense" skip of SZA.
RZB n Skip if B not zero. Otherwise identical to RZA.
SIA n Skip if A zero; then increment A. The A register is tested for zero, then incremented by one. If all 16 bits of A were zero before incrementing, skip to location defined by n.
SIB n Skip if B zero; then increment B. Otherwise identical to SIA.
RIA n Skip if A not zero; then increment A. This is a "Reverse Sense" skip of SIA.
:.
RIB n Skip if B not zero; then increment B. Otherwise identical to RIA.
SLA n,S/C Skip if Least Significant bit of A is zero. If the least significant bit (bit O) of the A register is zero, : skip to location defined by n. If either S or C is present, the test bit is altered accordingly after test.

` ~OS8760 ., , Alter-Skip Group (continued) SLB n,S/C Skip if Least Significant bit of B is zero. Other-- wise identical to SLA.
SAM n,S/C Skip if A is Minus. If the sign bit (bit 15) o~ the i A register is a ONE, skip to location defined by n. I~
either S or C is present, bit 15 is altered after the test.
SBM n,S/C Skip if B is Minus. Otherwise identical to SAM.
SAP n,S/C Skip if A is Positive. If the sign bit (bit 15) of the A register is a ZERO, skip to location defined by n.
either S or C is present, bit 15 is altered after the test.
` SBP n,S/C Skip if B is Positive. Otherwise identical to SAP.
SES n,S/C Skip if Least Significant bit o~ E is Set. If bit O of the E register is a ONE, skip to location defined by n. If either S or C is present, the entire E register is ; set or cleared respectively.
SEC n,S/C Skip if Least Significant bit of E is Clear. If ` bit O of the E register is a ZERO, skip to location deined by n. If either 5 or C is present, the entire E register is set or cleared respectively.
Complement-Execute-DMA Group.
These seven instructions include complement operations and several special-purpose instructions chosen to speed up printing ~, and extended memory operations.
CMA Complement A. The A register is replaced by its One's ~ complement.
- CMB Complement B. The B register is replaced by its One's complement.
TCA Two's Complement A. The A register is replaced by its One's Complement and incremented by one.
, TCB Two's complement B. The B register is replaced by its One's Complement and incremented by one.
EXA Execute A. The contents of the A register are treated as the current instruction, and executed in the normal manner.
The A register is le~t unchanged unless the instruction code causes A to be altered.
EXB Execute B. Otherwise identical to EXA.
DMA Direct Memory Access. The DMA control in Extended Memory is enabled by setting the indirect bit in M and giving a WTM
instruction. The next ~OM clock transfers A~M and the ~ollowing two cycles transfer B~M. ROM clock then remains inhibited until released by DMA control.

~OS876~) Note: Special Restriction for Direct Register Reference of A or B
For the five register reference instructions which involve a write operation during execution, a register reference to A or B must be restricted to an INDIRECT reference. These instructions are STA, STB, ISZ, DSZ, and JSM. A DIRECT register reference to A or B with these instructions may result in program modification.
(This is different from the hp 2116 in which a memory reference to the A or B register is treated as a reference to locations 0 or 1 respectively.) A reference to location 0 or 1 will actually refer to locations 0 or 1 in Read Only Memory.

Input/Output Group (IOG) The eleven IOG instructions, when given with a select code, are used for the purpose of checking flags, setting or clearing flag and control flip-flops, and transferring data between the A/B
registers and the I/O register.
STF <SC> Set the flag. Set the flag flip-flop of the channel indicated by select code <SC>.
,, CLF <SC> Clear the flag flip-flop of the channel indicated by } select code <SC>.
~ SFC <SC> Skip if flag clear. If the flag flip-flop is clear ;~ in the channel indicated by <SC>, skip the next instruction.
~ SFS <SC> H/C S~ip if flag set. If the flag flip-flop is set ;~ in the channel indicated by <SC>, skip the next instruction. H/C indicates if the flag flip-flop ~, should be held or cleared after executing SFS.
~ CLC <SC> H/C Clear control. Clear the control flip-flop in the `' channel indicated by <SC>. H/C indicates if the flag flip-flop should be held or cleared after executing CLC.
STC <SC> H/C Set Control. Set the control flip-flop in the channel indicated by <SC>. H/C indicates if the flag flip-flop should be held or cleared after ~ executing STC.
;~ OT* <SC> H/C Out~ut A or B. Sixteen bits from the A/B register are output to the I/O register. H~C allows holding or clearing the flag flop after execution of OT*, ` The different select codes allow different functions to take place after loading the I/O register.
.. . . .. . .. .. ..
SC=00 ~ata from the A or B register is output eight bits at a time for each OT*
instruction given. The A or B register is rotated right eight bits.

,................................ - 17C--.

':, l~S876~) Input-Output Group (IOG), continued :
SC=Ol The I/O register is loaded with 16 bits from the A/B registers.
SC=02 Data from the A/B register is output one bit at a time for each OT* instruction for the purpose of giving data to the Magnetic Card Reader. The I/O register is unchanged.
~i SC=04 The I/O register is loaded with 16 bits , from the A/B register and the control flip flop for the printer is then set.
,~
SC=08 The I/O register is loaded with 16 bits ; from the A/B register and the control flip ^ flop for the display is then set.
;
,~ SC=16 The I/O register is loaded with 16 bits from the A/B register and then data in th~
I/O register is transferred to the switch ;ii latches.
.
LI* <01> H/C Load into A or B. Load 16 bits of data into the ~iA ` A/B register from the I/O register.~ H/C allows ; holding or clearing the flag flop after Ll* has ``' been executed.
~LI* ~00> The least significant 8 bits of the I/O register `~ are loaded into the most significant locations in ~j the A or B register.
~, _ MI* <01> H/C Merge into A or B. Merge 16 bits of data into the A/B register from the I/O register by "inclusive or". H/C allows holding or clearing the flag flop " after Ml* has been executed.
MI* <00> The least significant 8 bits of the I/O register are combined by inclusive OR with the least significant 8 bits of the A or B register, and rotated to the most significant bit locations of the A or B register.

: .

: -171-~ .

., .

1~587~

MAC Instruction Group A total of 16 MAC instructions are available for operation (a) with the whole floating-point data (like transfer, shifts, etc), or (b) with two ~loating-point data words to speed up digit and word loops in arithmetic routines, , NOTE: <Ao 3> means: contents of A-register bit O to 3 AR 1 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1744 to 1747 (octal) ;, AR 2 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1754 to 1757 (octal~
D. means: mantissas i-th decimal digit;
, most significant digit is Dl `. least significant digit is D12 decimal point is located between Dl and D2 .~, Every operation with mantissa means BCD-coded decimal operation.
~ RET Return i~ 16-bit-number`stored at highest occupied address in stack~ is transferred to P- and M-registers. Stack pointer $ (=next free address in stack) is decremented by one.
<A>, <B>, <E> unchanged.
'1 MOV Move overflow The contents of E-register is transferred to Ao 3. Rest of A-register and E-register are filled by zeros.
cB> unchanged.
, ~
CLR Clear a floating-point data register in R/W memory on ` ` location <A>
ZERO~<A>, <A>+l, <A>+2, <A>+3 ; ~A>,>B>,<E> unchanged XFR Floating-poin$ data transfer in R/W memory from location <A> to location <B>.
Routine starts with exponent word transfer.
Da$a on location cA> is unchanged.
<E> unchanged.

:

:, , .. .

. .

1~5~7tj~

MRX ARl mantissa is shifted to right n-times. Exponent word remains unchanged.
<Bo 3> = n (binary coded) 1st shift: <Ao_3>~Dl; Di~Di+l; D12 is jth shift ~ ~ Dl; Di~Di+l; D12 i nth shift: ~ ~ Dl; Di~Di+l; D12 ~ Ao-3 $ ~} ~ E, A4_15 each shift: <Bo_3> ~ 1 ~ Bo_3 <B4_15> unchanged MRY AR2 mantissa is shifted to right n-times.
Otherwise identical to MRX
MLS AR2 mantissa is shifted to left once.
Exponent word remains unchanged.

D12; Di ~ Di~l; Dl Ao_3 <B> unchanged DRS ARl mantissa is shifted to right once Exponent word remains unchanged Dl; Di ~ Di+l; D12 Ao_3 ZERO ~ E and A4_15 <B> unchanged DLS ARl mantissa is shifted to left once. Exponent word remains unchanged.
<Ao 3> ~ D12; Di ~ Di_l; Dl 0_3 ~ ~ E, A4_15 ; <B> unchanged FXA Fixed-point addition Mantissas in pseudo-registers AR2 and ARl are added together and result is placed into AR2. Both exponent words remain unchanged. When overflow occurs "OOOl"
is set into E-reg., in opposite case <E> will be zero.
, <AR2> + <ARl> ~ DC ~ AR2 DC = ~ if <E> was OOOO before routine execution DC = 1 if <E> was 1111 before routine execution <B>, <ARl> unchanged .
.

.

10~876~) FMP Fast multiply ; Mantissas in pseudo-registers AR2 and ARl are added together <Bo 3>-times and result is placed into AR2.
Total decimal overflow is placed to Ao 3. Both ex-ponent words remain unchanged.
; <AR2> + <ARl> * <Bo_3 >+DC ~ AR2 i DC = O if <E> was OOOO before routine execution DC = 1 if <E> was 1111 before routine execution ZERO ~ E~ A4_15 <AR1> unchanged ` FDV Fast divide Mantissas in pseudo-registers AR2 and ARl are added together so many times until first decimal overflow occurs. Result is placed into AR2. Both exponent words remain unchanged. Each addition without over-flow causes +l increment of <B>.
1st addition: <AR2> + <ARl> + DC ~ AR2 DC = O if <E> was OOOO before routine execution DC = 1 if ~E> was 1111 before routine execution next additions: <AR2> + <ARl> ~ AR2 ZERO ~ E
h <ARl> unchanged CMX 10's complement of ARl mantissa is placed back to ARl, -~ and ZERO is set into E-register. Exponent word remains unchanged <B> unchanged CMY lO's complement of AR2 mantissa.
Otherwise identical to CMY
MDI Mantissa decimal increment.
Mantissa on location <A> is incremented by decimal ONE
on D12 level, result is placed back into the same . location, and zero is set into E-reg.
" Exponent word is unchanged.
When overflow occurs, result mantissa will be 1,000 OOOO OOOO (dec) and OOOl (bin) will be set into E-reg.
<B> unchanged.
NRM Normalization Mantissa in pseudo-register AR2 is rotated to the left to get Dl f O. Number of these 4-bit left shifts is stored in Bo_3 in binary form t<B4_15>=O) when<BO_3>= 0,1,2,. . . , 11 (dec) ~ <E> = OOOO
When<BO 3>= 12 (dec) ~mantissa is zero, and <E>=OOOl E~ponent word remains unchanged <A> unchanged.

., -1~4-lC~S~76V

~ The binary codes of all of the above instructions are listed in the following `~ coding table, where * implies the A or B register, D/I means direct/indirect, A/B means A register/B register, Z/C ~eans zero page (base page) current page, ; H/S means hold test bit/set test bit, and H/C means hold test bit/clear test` bit. D/I, A/B, Z/C, H/S, and H/C are all coded as 0/1.
CODING TABLE

., ;~MEMORY -O---- AD* D/I O O O A/B Z/C I MEMORY ADDRESS
.REFERENCE -1---- CP* D/I O O 1 A/B Z/C
; GROUP -2---- LD* D/I O 1 0 A/B Z/C
-3---- ST* D/I O 1 1 A/B Z/C

_4- -- ISZ D/I 1 0 0 1 Z/C

.' ..
SHIFT- 07---0 A*R O 1 1 1 A/B-- + SHIFT- O O O O
. ROTATE CODE
GROUP 07---2 S*R O 1 1 1 A/B-- - O O 1 0 : 07---4 S*L O 1 1 1 A/B-- 0 1 07---6 R*R O 1 1 1 A/B-- _ 0 1 1 ALTER- 07---0 SZ* O 1 1 1 A/B O SKIP~0 1 0 0 0 SGROUP 07---0 RZ* O 1 1 1 A/B 1 CODEO 1 0 0 0 07---0 SI* O 1 1 1 A/B O 1 1 0 0 0 . 07---0 RI* O 1 1 1 A/B 1 1 1 0 0 0 : 07---1 SL* O 1 1 1 A/B H/ l H/C 1 0 0 1 07---2 S*M O 1 1 1 A/B H/S H/C 1 0 1 0 07-~-3 S*P O 1 1 1 A/B H/ l H/C 1 0 1 1 : 07---5 SEC O 1 1 1 A/B H/~ H/C 1 1 0 1 . REGISTER 07--17 ADA O 1 1 1 A/B-- D/I O O O 0 1 1 1 1 : REFERENCE 07--37 ADB O 1 1 1 A/B-- D/I O O 0 1 1 1 1 1 .~ GROUP 07--57 CPA O 1 1 1 A/B-- D/I O O 1 0 1 1 1 1 .~ 07--77 CPB O 1 1 1 A/B-- D/I O O 1 1 1 1 1 1 . 07--17 LDA O 1 1 1 A/B-- D/I O 1 O 0 1 1 1 1 .;. 07--37 LDB O 1 1 1 A/B-- D/I O 1 O 1 1 1 1 1 ` 07-557 STA O 1 1 1 A/B-- 1 0 1 1 0 1 1 1 1 ~ 07_577STB O 1 1 1 A/B-- 1 0 1 1 1 1 1 1 1 :. 07--17 IOR O 1 1 1 A/B-- D/I 1 0 O O 1 1 1 1 07_-57 AND O 1 1 1 A/B-- 1 0 1 O 1 1 1 1 1 ~` 07--37 JMP O 1 1 1 A/B-- D/I 1 1 O 1 1 1 1 1 CONTINUED

~, .~
, 1~5~7~0 CODING TABLE - CONTINUED
.' ' COMP07-016 EX* O 1 1 1 A/B - - O 0 1 1 1 0 ; EXECUTE070036 DMA 0 1 1 1 O - _ 0 1 1 1 1 0. DMA 07-056 CM* O 1 1 1 A/B - - 1 0 1 1 1 0 07-076 TC* O 1 1 1 A/B - - _ _ 1 1 1 1 1 0 ... _ _ . INPUT1727-- STF 1 1 1 1 _ 1 01 1 1 1 + SELECT
.. OUTPUT1737-- CLF 1 1 1 1 - 1 11 1 1 1 CODE

.` 17-5-- SFS 1 1 1 1 - 1H/C1 0 1 0 . 17-6-- STC 1 1 1 1 - 1H/C1 1 0 0 17-1-- OT* 1 1 1 1 A/B 1H/CO 0 1 .~ 17-2-- LI* 1 1 1 1 A/B 1H/C0 1 0 17-0-- MI* 1 1 1 1 A/B 1H/CO O O 1 .
.~ . . _ _ ~ MAC170402 RET 1 1 1 1 O O O1 0 0 O O O 0 1 0 :~ GROUP170002 MOV 1 1 1 1 O O OO O O O O O 0 1 0 ~ 175400 DLS 1 1 1 1 1 0 11 0 0 O O O O O O
i 170560 FXA 1 1 1 1 O G O1 0 1 1 1 0 O O O

~ 170420 FDV 1 1 1 1 O O O1 0 0 O 1 0 O O O
.~ 174400 CMX 1 1 1 1 1 0 01 0 0 O O O O O O
~i.; 170400 CMY 1 1 1 1 O O O1 0 0 O O O O O O
.~ 170540 MDI 1 1 1 1 O O O1 0 1 1 0 0 O O O
.~ 171450 NRM 1 1 1 1 O 0 11 0 0 1 0 1 O O O
., ....
~' ~

. .

. -176-105~760 - MICROPROCESSOR
All of the above-listed routines and subroutines oi basic instructions are implemented by the basic computing system shown in Figure~ 3A-s~ Central control of this sy~tem is achieved by microprocessor 120. As shown in the block dia-gram o~ Figure 136 and in the detailed schematic dlagram o~
Figures 137A-D, the microprocessor comprises a bipolar ROM 200 including seven ROM chips organized into 256 words oi 28 bitc. ~ight J-~ ~lip-~lops contai~ the ROM address; (i.e.
a 4-bit primary address and a 4-bit secondary address). A
single chip 16-bit data selector permits any one o~ 16 di~-~ .
~ere~t qualifier lines to be ~ested with a 4-bit quali~ier code. This 4-bit quali~ier code ROM chip serves a dual ~unc-tion in that it provides a complementing code to the 4 pri-mary address ~lip-~lops as well as selecti~g the proper qualifier to be tested. I~ branching i~ any RO~ state is desired, the microinstruction BRC must also be given. BRC
occurring with a QN (quali~ier not met) signal ~rom the data ~ .
`~ selector will cause the least signi~icant bit o~ the address :,, `` 20 code to be inhibited to the secondary address ~lip-flop, thus `` causing the address to "bra~ch" according to the state of the qual~ier.
~n additional feature o~ this ROM orga~ization is the IQN microlnstruction (inhibit i~ quali~ier not met). ~hen the IQN is given and the qualifier selected by the quali~ier code is not met, the signal CCO (cloc~ code zero) goes low.
This inhibits all shi~t clock ~ulses ~rom the clock decoder which in ef~ec~ ~reve~ts execution o~ microinstructions in that ROM state~
To minimize the ROM word length, two ~-to-8-line lOS8~760 decoders are used to expand 3 R-code outputs and 3 X-code outputs into a total of 14 microinstructions. Also the SCO
and SCI outputs from ROM #5 are decoded in the Memory. The ALU code outputs ACO, ACl, and AC2 are treated as address inputs to the ALU ROM and therefore need no decoding.
The microprocessor is responsible for the following:
1. Issuing a four-bit clock code to the clock decoder during each ROM state.
2. Issuing microinstructions to the memory, in-j 10 cluding the read and write microinstructions.
3 Issuing microinstructions to the shift registers for gating serial data into or out of the proper registers.
4. Issuing a four-bit ALU code to the Arith Logic Unit to select the proper binary or BCD arithmetic functionu 5. Performing logical decisions (branching) based on the states of 16 qualifier inputs to the micro-processor.
6. Issuing next address information to the ROM ad-dress flip-flops in the microprocessor.
7. Transferring control to the input/output controller via the I/O strobe for execution of input or output instructions.
The full set of 28 ROM outputs with their associated microinstructions, the list of 16 qualifiers and assigned codes, and the microprocessor mnemonics are contained in the s iollowing tables:
:`
3~

105~3760 MICRO-INSTRUCTION SET TABLE
POSITIVENEGATIVE TRUE
~TRUE~~ OUTPUT ~
CONTROL ROMDECODED M-INSTRUCTION FUNCTION
FIELD OUTPUT OUTPUT
, .
GENERAL1. IQN INHIBIT SHIFT CLOCK IF QUALIFIER NOT MET.
2. BRC BRANCH: INHIBITS SOO IF QUALIFIER NOT MET.
3. ~T~ T BUS ~ T REG
4. TTM T BUS M REG
5. XRTDECODED IN MEMORY A/B REG ~ R BUS
SCl SCO
S-CODE6. SCl ZTS O O ZERO ) S BUS
7. SCO MTS O 1 M REG ) S BUS
TTS 1 O T REG ~ S BUS
UTS 1 1 ONE ) S BUS
DECODED IN MICROPROCESSOR
RC2 RCl RCO
R-CODE 8. RC2 UTR O O O ONE ~ R BUS
;` 9. RCl PTR O O 1 P REG ~ R BUS
10. RCO TRE O 1 O T REG E REG ~ R BUS
WTM-ZTR O 1 1 STORE CONTENTS T REG ) MEMORY
TQG-ZTR 1 O O T BUS ~ Q REG (BIT 6) QTR 1 O 1 Q REG ~ R BUS
RDM-ZTR 1 1 O READ MEMORY 'M> ~ T REG
ZTR 1 1 1 ZERO ~ R BUS
DECODED IN MICROPROCESSOR
XC2 XCl XCO
X-CODE11. XC2 TTQ O O O T BUS ~ Q REG
12. XCl QAB O O 1 Q REG (BIT 11)~ AB FLIP-FLOP
13. XCO BCD O 1 O BCD ARITHMETIC MODE OF ALU
TBE O 1 1 T BUS ~ E REG ~ R BUS
; CAB 1 O O COMPLEMENT THE AB FLIP-FLOP
TTP 1 O 1 T BUS ~ P REG
TTX 1 1 O T BUS ~ A/B REG

DECODED IN ALU
` AC2 ACl ACO
ALU14. AC2 XOR O O O EXCLUSIVE OR....... R+S ~ T BUS
15. ACl AND O O 1 LOGICAL AND........ R-S ~ T BUS
16. ACO IOR O 1 O INCLUSIYE OR....... R+S ~ T BUS
ZTT O 1 1 ZERO ~ T BUS
~:` ZTT-CBC 1 O O ZERO ~ T BUS, CLEAR BINARY CARRY
IOR-CBC 1 O 1 INCLUSIVE OR, CLEAR BINARY CARRY
IOR-SBC 1 1 O INCLUSIVE OR, SET BINARY CARRY

.

~ 105~3760 ` MICRO-INSTRUCTION SET TABLE (CONTD.) ~ ... __ -CONTR¢L ROM FUNCTION
; FIELD OUTPUT
CLOCK 17. CCl THIS 4-BIT CODE INITIALIZES A PRESETTABLE
18. CC2 DOWN COUNTER TO GENERATE ANY NUMBER
19. CC4 OF SHIFT CLOCKS FROM 1 THROUGH 16.
20. CC8 SHIFT IS INHIBITED BY IQN IF QUALIFIER NOT MET.

QUALIFIER 21. QC3 THIS 4-BIT CODE PERFORMS TWO FUNCTIONS:
22. QC2 (1.) ADDRESSING THE DATA SELECTOR TO SELECT
23. QCl ONE OF SIXTEEN QUALIFIER INPUTS.
2q. QCO (2.) PROVIDES COMPLEMENT CODE TO PRIMARY FLIP-FLOPS

SECONDARY 25. S03 THIS 4-BIT CODE PROVIDES COMPLEMENT
ADDRESS 26. S02 CODE TO THE SECONDARY FLIP-FLOPS.
27. SOl IF BRC IS GIVEN AND QUALIFIER IS NOT
28. SOO _ MET, THE SOO BIT IS INHIBITED
.~
. SPECIAL MICRO-INSTRUCTIONS:
"
~ ,_ TQR = UTR XTR..... TRANSFERS ¦ Q14 Qll ~ P04 Q-REGISTER TO PRIMARY ADDRESS J Q12 ~ P05 AS SHOWN ~ Q13 ~ P06 - ~ Q14 ~ Po7 -~ IOS = PTR XTR....... INITIATES:
' a) TRANSFER OF CONTROL TO I/O IF Q10 = 1 ' b) SETS "SINGLE SERVICE" FF IN I/O VIA ~ IF Q10 - O
SPECIAL OPERATIONS:
BCD SUM ~ A<0-3> - BCD ~ff~ ROM CLOCK
CLEAR DECIMAL CARRY = QAB . ROM CLOCK
- ~ SET DECIMAL CARRY = UTR BCD ROM CLOCK
~' DECIMAL ADD = BCD 2TT ........ T<0-3> ~ A<0-3> ~ Q<0-3>
IO'S COMPLEMENT W/ DECIMAL ADD = BCD ~ ADD......
...... T<0-3> ~ A<0-3> ~ Q<0-3>

`.

~0S87610 QUALIFIER SET TABLE

QUALIFIER CODE
QC2 QCl QCO MNEMONIC FUNCTION
OOOO QOO SHIFT/SKIP ONE BIT
OOOl QOl SHIFT/SKIP TWO BITS

OOll Q03 SHIFT/SKIP EIGHT BITS

O101 Q05 SET BIT IN A/S GROUP; FDV QUALIFIER
OllO Q06 T-BUS QUALIFIER VIA TQ6 Olll QBC BINARY CARRY FROM ALU
1000 QPO P REGISTER, BIT O, FOR BCD COUNTING
1001 Q15 INDIRECT ADDRESS, CLEAR BIT IN A/S GROUP

1011 Q10 CURRENT PAGE QUALIFIER, FXA QUALIFIER

1111 *QRD ROM DISABLE (NORMALLY ZERO) ~. ' POP WILL PRESET ROM ADDRESS FLIP-FLOPS AT TURN-ON
*QRD MAY BE USED WITH IQN TO INSURE ZERO SHIFT EXCEPT WHEN IN I/O LOOP.
`:
`~` MICROPROCESSOR MNEMONICS
Clock Signals MCK Memory Cl ock SCK Shift Cl ock XTC External Clock RCF ROM Clock for Flip Flops RCA ROM Clock for Address Flip Flops IIC Inhibit Internal Clock INH Inhibit Clock IPS Inhibit ROM Clock (Also primary and secondary Flip Flop) ~; -391-~058760 MICROPROCESSOR MNEMONICS (Continued) . . .
: CC8 . CC4 CC2 Clock Code: Binary Code that programs CCl the number of shift clocks ` CC0 Inhibits Shift Clocks Address Mnemonics :
pop Power on Preset IQN Inhibit if Qualifier not met BRC Branch Q-Register TQR Transfer Qll, Q12, Q13, Q14 to primary addr. Flip Flops TTQ T-Bus to Q-Register QTR Q-Register to R-Bus Q5 Bits 10 - 0 of Q-Register Ql Data Qualifiers QP0 Bit 0 of P-Register QRD Qualifier ROM Disable (I/O interupt) QNR Qualifier No Request (Keyboard Interupt) QDC Decimal Carry QBC Binary Carry Memory SC0 S-Bus Code SCI
m T-Bus to T-Register TTM T-Bus to M-Register RDM Read Memory WTM Write Memory 10587~60 MICROPROCESSOR MNEMONICS (Continued) A, B, P, E-Registers QAB Q-Register to AB Flip Flop AB = ~ A-Register Operation = 0 B-Register Operation TTX (ROM) T-Bus to A or B Register (Originates at ROM Decoder) XTR A or B Register to R-Bus TTP T-Bus to P-Register PTR P-Registers to R-Bus TBE T-Bus to E-Register to R-Bus ,.
TRE T-Register to E-Register UTR Units to R-Bus : AC2--) . ACl ~ Arithmetic Codes for Arithmetic AC~ Logic Unit ~b Decimal Arithmetic SDR Disables ROMs For Single Step Test Operation :;
Each of the ROM chips of Figures 136-137 is organized into 256 words of 4 bits each constructed in accordance with the following table, . where each "L" represents a low (or "O") state and each "H" represents a high or ("1") state:

:
, :~ 1058760 0012 2053,09,1,4,01024 0014 02,11,71 0~15 414 ~023 056-063 LLLH LLLH HHLL LHLH LLLH HHLH HLHH LHLL

0~27 088-095 LLHH LLLL HHHH LHHH LLLL LLHH LLLL LHLL

0~32 128-135 HLHL LHLL HHLL LHLH LHHH HLHH LLLL LLLL

~037 168-175 LHHL HLLL LHLL HLHL LLLL LLLH LHLL HLLL

~043 216-223 HHHH HHLH LLLL LLLL LLLL LHLL LLLH HLLH
~044 224-231 HLLH HLLH LLLL LLLL HHLH HLLL LHHL HHHL

.:: .

0049 20s4,09,1,4,01P24 0051 02,11,71 P056 024-p31 LLLL LLLL HLHL LLHL LLLL LLLH LHLL LHHH SN237P4 p058 040-047 LLLL LLLL HHLH HHLL HHLH HHLL HLLH HLHL SN23704 0059 048-055 HHHH LLHH LLLL HLLL LLLL HLHH HHLL LHLL SN237~4 0p65 096-103 HHHL HLHH HLLL HLHL HHHH HHLL HHHL LLHL SN23704 P066 lP4-111 LLLL LLLL LHLL LLHL HLLL LLLL HLHL LLHH SN23704 0068 12p-127 LLHL HHHH HLLL HLHH LHLL HLLH HLLH HHHL SN23704 p071 144-151 HLHL HLHL HLLL HLLH HLHH LHLL HHLL HHLL SN23704 0p73 160-167 LLLH HHHL HHHL LLHH HHHL HLHH HHHH HHHL SN23704 0p79 2P8-215 LHHH HLLL HLLL LLLH HLHL LLLH LHLL LHHL SN237P4 0p8P 216-223 LLHL HLHL HLHL LLHL HLLL LLLL LLLL HLHL SN23704 0p81 224-231 HLLL HLLH LHHL HHLL HLLL LHLL LHLL LHHH SN23704 0p83 24p-247 HHLL LHLL LLHH HLLL HLLL HLHH LHLL LHLL SN23704 .~
0086 2055,09,1,01024 ~087 ROM5 0~88 02,11,71 01p5 120-127 HLHH LLLL LLHH HLHH LLHH HHLH LLLL HHHH
~106 128-135 HHHH LHLH HHHH LLLL LLLH LLHH LLLL LLLL

pll4 192-199 HHHH HLHH HHHH HHHH LHLH HLHH LHLH LHLH
0115 200-2a7 LLLL HHHL HHHH LLLH HHHH LLLL HLHH HHHH

Pll9 232-239 HHHH LLLL HLHH HHHH LLLL LLLL HHHL HHHL

., :
:

0123 2~56,09,2,4,01024 0125 02,11,71 0131 032-p39 LLLL LHHH LHHH LHHH LHLH LHHH LHHL HHHH SN237P6 pl33 048-P55 LLLH LHLH LHHH LHLL LHHH LLLH LLHH LLHH SN23706 pl35 P64-071 LLHH LHHL LHHH LHHH LHHL LHLH HLHH LLLH SN237P6 pl37 08P-087 LHHH LHHH LLHH HHHL LHHH LHHL LHLH LHHH SN237P6 pl49 176-183 LHHH LHHH LHLH LHLH LHLH LLHH LHHL LHHH SN23706 pl54 216-223 HLHH LHHH LHHH LHHH LLHH LHHH LHLH LLHH SN237P6 pl57 240-247 LHLL LHHH LHLH LLLH LHLL LHLH LLHH LLLH SN237P6 ~^' -:

. .

-0160 2057,09,1,4,P1024 0162 02,11,71 0166 016-023 LHLL LHLL LHHH LHHH LHHH LHHH LLHH LHHH SN237a7 pl73 072-079 LLLH LHHH LHHH LHHH LHLL LHHH LHHH LHHH SN23707 pl76 096-103 LHHH HHHL HLHH HHHH HHHH HHHH HHLL LHHH SN23707 pl77 104-111 LLLH LHHH LLLL LHHH LLHH LHHH HLLL LHHH SN23707 0185 168-175 LLLH LHHH LHLL HHHH LLLL LHLL LHLL LHLL SN237a7 0190 208-215 LHHH HHHH HLHH LHLL HHHH LLHL LHHH LHHH SN237a7 01g5 248-255 LHHH HHHH LLHH LHHH HHHH HLLH LHHH LHHH SN23707 :`
`:

0197 2058,09,1,4,~1024 ~198 0199 02,11,71 02p0 733 p2P6 040-P47 LHHL LHHL LHHL LHHL HLHL HHHH HHHL HHHL

p210 072-079 HHHL HHHL LHHH HHHL LLLH LHHH HHHH HHHH

0213 p90-103 HHHL LHLL HHHL HHHL LHHL HHHL HHHL LLHL

p230 232-239 LHHL HHHL HHHH LLLL HHHH HHHL LLLH HHHH
p231 240-247 HLHL HHHL LHLH LLHL HHHL HLHL HHHL HHHH
p232 248-255 HHHL HHHL LHLL HLHL HHHL HHHL LHHL LHHL

lOS8760 0234 2059,09,1,4,01024 0236 02,11,71 p237 586 0238 000~007 HHLH HHLL HHLL LHLH HHLL HHHH HHLH HHLH
0239 0~8-015 HHLL HHHH LHLH HHLL HLHH HHLL HHLL LHLL

a257 152-159 HHLL HHLL HHLL HHLL HLLH HHLL HHLL LHHH

~259 168-175 HHHH LHLL HHHH HHLL LHLH HLLL LHHL HHLL
p260 176-183 HLLH LHLL HHLH HHLH LHHH LHHH HHLL HHLL
p261 184-191 HHLL HHLL LHLL HHHL LHHH HHLL HHLL LHHH

p265 216-223 HHLL HHLL HHLL HHHH LHHH LHLL LHLL HHLL

p267 232-239 HHHH HHLL HHLL LLHH HHLL HHLL HHLL LHLL
fl268 240-247 HHHH HHLL LHHH HHLL LHHH HHHH LHHH LHLL

.

.
., Each o~ the 71 basic instructions employed by the calculator is implemented by one or more o~ the above-described microinstructions and associated control signals issued by the microprocessor. The manner in which this is accomplished is shown and described in detail in the ~low charts of Figures 138A-H. Each rectangular box o~ these ilow charts represents a state of ROM 200 of the microprocessor and includes the mnemonic of the microinstructions and con-trol signals stored in that RO~ state. The number at the upper right-hand corner o~ each of these rectangular boxes represents the number of shift clock pulses required by the microinstructiQns of tha~ RO~ state. A simpli~ied overview o~ these detailed flow charts is shown in Figure 7.
PROGRA~AB~E CLOCE
Given a computing system organized to process binary data serially and under co~trol of microinstructions stored in ROM 200 as shown in Figures 3A-B and 136, the Lmplementation o~ a general purpose ~nstruction set requires that some num~er of bits be shifted into or out of the storage registers.
Depending on the operation be~ng performed, the number o~ bits may vary ~rom zero to n, where n is the number of bits in a si~gle machine word.
I~ each clock period o~ the RO~ clock corresponds to a o~e bit shift, a count loop must be employed to provide the desired number of shifts~ A rather large number of such count loops would e~ist in order to implement an entire instruction set. An alterna*ive method is to provide additional hardware which permits assig~ment o~ the desired number o~ shifts in a single state o~ ROM 200. Such an arrangement requ~res a varia~le cycle time ~or each state of RO~ 200, but results .

.

~058760 in a very substantive saving in total number of ROM states To implement a variable number of shift clocks in a single state of the microprocessor, two separate clocks are required. The shift clock is applied to the data storage registers in the memory, the shift register block~ the arith-metic logic unit and the input/output block. The ROM clock is applied to the ROM address flip-flops in the microprocessor, and occurs once for each state in the microprogram. The number of shift clock pulses that occur in any given ROM state is determined by a 4-bit clock code sent to the clock decoder from the microprocessor.
If no shift clocks are desired, a separate signal from the microprocessor inhibits the shift clock output, ~i independent of the clock code issued in that state. In this way, any number of shifts between and including zero and 16 may be implemented with a 4-bit clock code and an inhibit x signal.
This inhibit signal offers an additional powerful feature when gated by the qualifier test logic in the micro-?.
processor as shown in Figure 136. The qualifier test logic includes a 4-bit qualifier code from ROM 3 that selects one of 16 qualifier inputs to the data selector. The data selector output QN (qualifier not met) will be high if the selected qualifier input was low. By using the QN signal to gate the inhibit microinstruction, IQN, the shift clock will be inhibited only when the qualifier is not met. Thus all microinstructions requiring shift clocks that are issued in a given ROM state may be either executed or inhibited, depending on the logical state of the qualifier under test.
The ROM clock is applied to the eight J-K flip-flops 105 !3760 which address the 256 word microprocessor ROM. Durin~ any given state, the complementing (J-X) inputs to the 4 pri-mary address flip-flops are set up by the qualifier code or q-register code. The 4 secondary address flip-~lop inputs are determined by the ROM 4 outputs, the BRC microinstruction, and the data selector output QN. Where ROhl clock goes low, the negative edge-trigger~d flip-flops will cause transi-tio~ of the ROM address to the next ROM state.
As shown in the block diagram of Figure 139 and the detailed schematic diagram of Figures 140A-C, a crystal con-trolled system clock output is inverted to generate memory clock, MC~. This signal is again inverted to clock a D
flip-flop ha~ing an output ~control clock), which will go low if the end-of-count signal (borrow) ~rom the down counter has occurred at the D input. The ROM clock will also go low at this time, initiating a new RO~ state in the microprocessor.
Control clock will norm~lly remain low ~or one system clock period, and in turn generates a load signal which is delayed a hal~ period from control clock by means of a second D flip-~` 20 ~lop. The 4-bit clock code ~rom the microprocessor is pre-~ set into the counter while the load signal is low.
-~ ~s the load signal goes high, ROM clock also goes high, completing the fixed interval portion of RO~ clock and shift clock as shown in ~igure 141. A series of clock pulses are now gatad onto shift clock, SCK, until the preset counter has counted down to zero, causing control cloc~ to again go low, completing the ROM cycle~
The inhibit slgnal, ~R~-, from memory may lengthen the normal fi~ed i~erval of ROM clock by cleari~g the D flip-flop a~d holding control clock low. This may occur during i .

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1058~60 memory refresh or e~ternal test operations. In this situation, the counter remains preset and the correct number of shifts will be generated when the inhibit goes away.
SHIFT REGIST~R UNIT
As shown in the detailed schematic diagrams of Figures 137A-D and 142A-D, A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130 comprise bipolar status registers, the contents of which are recir-culated when data is output to the R-bus or the S-bus.
Full control of these registers in use and type o~ opera-: tions per~ormed is maintained by the microinstructions from the from the microprocessor. The number of bits to be shifted in a~y one ROM state of the microprocessor is determined by the number of shift clocks from the clock de-coder. This shi~t clock appe rs at the shiit clock i~put of , each shift register that is enabled by the microprocessor during that RO~ cycle.
ARlT~ETIC LOGIC UNIT
The de~elopment of comple~ read-only memory arrays on a single chip ha~e made possible a hard~are implementa-tio~ of central processing units (CPUs) and arithmetic logic units (AL~s) with far ~ewer components than were previously possible. In this application, two bipolar read-only memory ` chips are combined with carry ~lip-flops and adapted to perform one-bit binary logic and arithmetic operations as ~ell as four-bit binary coded decimal (BCD~ arithmetic opera-tious. The two bipolar read-only memory chips may comprise, for example, Hewlett-Packard 16-pin dual-in-line packaged bipolar RO~s organized into 256 words by 4-bits and of the same .. . . .
type as shown and described in U.S. Patent 3, 721, 964 issued March 20, 1973.

. , 105~760 .
The binary/BCD Arithmetic Logic Unit consists of fiYe integrated circuits connected as shown in the block diagram of Figure 143 and the detailed schematic diagram of Figures 142A-D. Specifically, the packages consist of two 1024-bit RO~s, a du~l D-type flip-flop and two quad two-input NAND gates. The function code input '~CD" selects between the binary mode and BCD mode o~ operation.
In the binary mode, the function code inputs ACO, ACl, and AC2 select the desired logical function or arith-metic operation as gi~e~ in Figure 144. The binary input data enters ROM #l on the carry, S-bus and R-bus input lines, and the binary result appears on the T-~us and binary carry output lines. RO~ ~2 is not used in the binary mode.
the BCD mode of operation, the two function code lines ~ ACO and ACl are disabled from the Micro-processor and these twoJ lines carry the T02 and T03 bits of BCD data from the T-Register.
x The ALU function code l~ne AC2 is used to select the desired BCD operation. If AC2 is lo~, the four-bit output ~OJ~ 2,~3 `~ will be the BCD sum of the t~o BCD data inputs. I~ AC2 is high and decimal c~rry has been set, the ~our-bit output ~0~ 2~3 ` will be the BCD Tens Complement of the BCD data ~rom the '~! T-Register. ID the BCD mode, the binary carry output will be ` disabled and the decimal carry output will be enabled to ROM ~1.
Although only one-fourth of the a~ailable registers in RO~ #l are required for tho eight binary operations, the concept oi' adding a second 1024-bit ~OM to peri'orm the BCD
operations grew from several basic concepts:
1) The least significant BCD su~t bit, Eo~ is always identical to the binary sum bit; therefore, only three add~tional outputs, 1, ~ , and ~3 need be generated~ For BCD complement operations, the decimal carry flip-flop defines whetll~r or not the least significant bit should be complemented.
:
--~0 5--,.~

, .
. . .

2) In forming tl~c "ninc's complenlellt~ oi the T-ne~ister BCD data in ROhT #l, it can be scen that ior 8~2l co(le the second least si6nific~nt bit 1'01 is the same beforc and after Lormin~ the complcment. Thus only two bits, T02 ~nd T03 need be complemcnted ~ prior to input illto ROM #2. The ten's complement ; with add is then found by presctting decimal carry and performing a BCD sum of the three most ;` significant digits in ROM ~2.

3) With only eight ROM inputs available, some sharing of inputs is required for ROM #1 During binary '! operations, all four function codcs and only one bit of T-Register data is required. During BCD
operations9 all four bits of T-Register data and only two function codes are required. Use of two NAND
gates in wire-OR connection with the open collector function codes AC0 and ACl permits sharing of the two lnputs.
This arrangement left one input still available to ROM #2.
5~ By programming this input to always make output DCI true,. the micro-instruction UTR can sexve two purposes--placing units on the R-bus and also set decimal carry if BCD is true. When BCD is false, cloc~ is inhibited to decimal carry. This feature permits saving decimal carry information during all binary operations. Similarly, binary carry is saved during the f~ur binary operations AND, IOR, XOR, and ZTT by connecting AC2 such that when AC2 is false the shift clock is inhibited to the binary carry flip-flop.

In summary, the mode select input "BCD" performs the following functions:
1) Addresses the proper 128 word set of word lines in ~OM #1.
2~ Enables the T02 and T03 data lines to ROM ~l only in BCD mode.
3) Enables clock to decimal carry flip-flop only in BCD mode.
4) Selects binary carry or decimal carry into ROM s71 as appropriate.
5) Transfers outputs ~0~5~ 2~ to A-Registcr only in BCD mode. 3 ., -~06-.

,, --lOS~1760 i The remaining three ALU function codes select the proper set of wor'd lines ln R~ ~1 to pertGrm ~he eign~ binary'functions 'listed in Figure 144. In addition, the AC2 input performs the following functions.
1) Enables clock to binary carry flip-flop only during the four carry-related binary functions and the BCD comp/add function.
2) In the BCD mode, AC2 causes BCD data bit TOO, TO2 and TO3 ~' to convert to nine's complement form.
The ALU has a total of 15 inputs which include 8 data inputs, 2 clock inputs and 5 microinstructions. Four data output lines are required, and two additional output lines from carry flip-flops are available as qual-ifier inputs to the microprocessor. The ALU and shift register mnemonics are listed in the following table:
-~ SHIFT REGISTE2S ~ ALU BO~RD MNEMONICS
`'3~ TRE T-Register to E-Register to R-Bus TO0 Bit 0 of T-Register TBE T-Bus to E-Register to R-Bus TTX - TEST T-Bus to A/B-Register from Tester TTX - I/O T-Bus to A/B-Register from I/O (Board #12) TTX - ROM T-Bus to A/B Register from ~-Processor (Board #13) TTX Logical "OR" of Three TTX Signals AB Status of AB-Flip-Flop AB = O A-Reg. Operation ' AB = 1 B-Reg. Operation XTR A/B Register to R-Bus UTR Logical "1" to R-Bus ; TQR Q-Register to Primary Address Flip-Flops AB Complement of AB
' TTP T-Bus to P-Register - SCK Shift Clock QP0 Qualifier, Bit 0 of P-Register ' PTR P-Register to R-Bus .. - :

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i..
` SHIFT REGISTERS & ALU BOARD MNEMONICS (Continued) Q00 Q-Register Bit ~
~. QTR Q-Register to R-Bus :~ RCK ROM Clock , ;
:`~. QAB Q-Register to Ab-Flip-Flop, also ................................................................. clears decimal carry.
SCB Set Binary Carry .` QDC Qualifier, Decimal Carry BCD Decimal Arithmetic ::`
:~ AC2 ALU Operation Code .'. QBC Qualifier, Binary Carry ~" S-BUS Data Bus , ACl ALU Operation Code . AC0 ALU Operation Code ~` T02 Bit 2 of T-Register T03 Bit 3 of T-Register SDR Signal to Disable ROMs TOl Bit 1 of T-Register '` T-BUS Data Bus ALU Arithmetic Logic Unit ( ) Indicates Negat~ve True Signal : Figure 145 lists five dual-in-line integrated circuits that may be employed in the ALU. The following table gives an ~! example of how the two ALU ROM chips shown in Figures 142-143 : .-can be constructed to implement the above described ALU functions(in this table each "1" represents a "low" state and each "O"
represents a "high" state):

`
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~058760 ROM # 1 `~ / 1000; 1/ 0000; 2/ 0000; 3/ 1000 .. 4/ 1000; 5/ 0000; 6/ 0~00; 7/ 1000 8/ 0000; 9/ 0000; 1~/ 000~; 11/ 1000 ` 12/ 000~, 13/ 0000; 14/ 0000; 15/ 1000 ., 16/ 0000; 17/ 10~0; 18/ 1000; 19/ 1000 " 20/ 0000; 21/ 1000; 22/ 1000; 23/ 1000 .` 24/ 1000; 25/ 1000; 26/ 10~0; 27/ 1000 28/ 1000; 29/ 1000; 30/ 1000; 31/ 1000 ~j 32/ 1000; 33/ 0000; 34/ ~000; 35/ 1000 ` 36/ 1000; 37/ 0000; 38/ 0000; 39/ 1000 40/ ~000; 41/ 0000; 42/ 0000; 43/ 1000 44/ 0000; 45/ 0000; 46/ 0000; 47/ 100 ;.' 48/ 0000; 49/ 1000; 50/ 1000; 51/ 100~
52/ 0000; 53/ 1000; 54/ 1000; 55/ 1000 56/ 1000; 57/ 1000; 58/ 100~; 59/ 1000 .~ 60/ 1000; 61/ 1000; 62/ 1000; 63/ 1000 64/ 1100; 65/ 1100; 66/ 1100; 67/ 1100 68/ 1100; 69/ 1100; 70/ 1100; 71/ 1100 :. 72/ 0000; 73/ 0~00; 74/ 0000; 75/ 1000 76/ 0000; 77/ 0000; 78/ 0000; 79/ 1000 80/ 0100; 81/ 0100; 82/ 0100; 83/ 1100 , 84/ 0100; 85/ 0100; 86/ 0100; 87/ 1100 88/ 0000; 89/ 10~0; 90/ 1000; 91/ 0100 : 92/ 1000; 93/ 0100; 94/ 01~0; 95/ 1100 ' 96/ 1100; 97/ 1100; 98/ 11~0; 99/ 1100 ~ 100/ 1100; 101/ 1100; 102/ 1100; 103/ 1100 :;~ 104/ 0000; 105/ 0000; 106/ 000~; 107/ 1000 `~ 108/ 0000; 109/ 0000; 110/ 0000; 111/ 1000 ' 112/ 0100; 113/ 0100; 114/ 0100; 115/ 1100 ~ 116/ 0100; 117/ 0100;118/ 0100; 119/ 1100 :. 120/ 0000; 121/ 1000; 122/ 1000; 123/ 0100 ;', 124/ 10~0; 125/ 0100;126/ 0100; 127/ 1100 128/ 0~00; 129/ 0000;130/ 0000; 131/ 0000 ~ 132/ 0000; 133/ 0000; 134/ 0000; 135/ 0000 :~ 136/ 0010; 137/ 1010; 138/ 1010; 139/ 0110 ` 140/ 1010; 141/ 0110; 142/ 0110; 143/ 1110 :`i 144/ 0001; 145/ 1001; 146/ 1001; 147/ 0101 `` 148/ 1001; 149/ 0101; 150/ 0101; 151/ 1101 152/ ~011; 153/ 1011; 154/ 1011; 155/ 0111 ` 156/ 1011; 157/ 0111; 158/ 0111; 159/ 1111 ` 160/ 0000; 161/ 0000; 162/ 0000; 163/ 0000 " 164/ 0000; 165/ 0000; 166/ 0000; 167/ 0000 . 168/ 0~10; 169/ 1010; 170/ 1010; 171/ 0110 172/ 1010; 173/ 0110; 174/ 0110; 175/ 1110 176/ 0000; 177/ 0000; 178/ 0000; 179/ 00~0 180/ 0000; 181/ 0~00; 182/ 0000; 183/ 00~0 184/ 0011; 185/ 1011; 186/ 1011; 187/ 0111 :` 188/ 1011; 189/ 0111; 190/ 0111; 191/ 1111 192/ 0000; 193/ 0000; 194/ 0000; 195/ 0000 196/ 0000; 197/ 0000; 198/ 0000; 199/ 0000 200/ 1010; 201/ 001~; 202/ 0110; 203/ 1010 . 204/ 0110; 205/ 1010; 206/ 1110; 207/ 0110 ~ 2~8/ 1011; 209/ 0010; 210/ 0111; 211/ 1011 `` 212/ 0111; 213/ 1011; 214/ 1111; 215/ 0111 ~` 216/ 1001; 217/ 0001; 218/ 0101; 219/ 1001 220/ 0101; 221/ 1001; 222/ 1101; 223/ 0101 224/ 0000; 225/ 000~; 2~6/ 0~00; 227/ 0000 ` 228/ 0000; 229/ 0000; 230/ 0000; 231/ 0000 ; 232/ 1011; 233/ 0011; 234/ 0111; ` 235/ 1011 236/ 0111; 237/ 1011; 238/ 1111, 239/ 0111 240/ 0000; 241/ 0000; 242/ 0000, 243/ 0000 244/ 0000; 245/ 0000; 246/ 0000; 247/ 0000 248/ 1010; 249/ 0~10; 25~/ 0110; 251/ 1010 252/ 0110; 253/ 101~; 254/ 1110; 255/ 0110 lOS8760 ROM #2 / 00~0; 1/ 0000; 2/ 0000; 3/ 000~
4/ 0000; 5/ 0~00; 6/ 0000; 7/ 0~00 8/ 0000; 9/ 0000; 10/ 0000; 11/ 0000 12/ 0~00; 13/ 0000; 14/ 000~; 15/ 0000 16/ 0000; 17/ 0000; 18/ 0000; 19/ 000 20/ 0000; 21/ 0000; 22/ 0000; 23/ 0000 24/ 0000; 25/ 00~0; 26/ 0000; 27/ 0000 28/ ~000; 29/ 0000; 30/ 0000; 31/ 0000 32/ 0000; 33/ 0000; 34/ 0000; 35/ 0000 36/ 0000; 37/ 00~0; 38/ 0000; 39/ 0000 40/ 0000; 41; 0000; 42/ 0000; 43/ 0000 44/ 0000; 45/ 0000; 46/ 0~00; 47/ 0000 48/ 0000; 49/ 0000; 50/ 0000; 51/ 0000 52/ 00~0; 53/ 0000; 54/ 0000; 55/ 0000 56/ 0000; 57/ 0000; 58/ 0000; 59/ 00~0 60/ 0000; 61/ 0000; 62/ 0000; 63/ 0000 64/ 0000; 65/ 0000; 66/ 0000; 67/ 0000 68/ 0000; 69/ 0000; 70/ 0000; 71/ 0000 72/ 0000; 73/ 0000; 74/ 0000; 75/ 00~0 76/ 0000; 77/ 0000; 78/ 0000; 79/ 0000 80/ 0~0~; 81/ ~00~; ~2/ 0000; 83/ 0000 84/ 0000; 85/ 0000; 86/ 0000; 87/ 0000 88/ 0000; 89/ 0000;90/ 0000; 91/ 0000 92/ 0000; 93/ 0000;94/ 000~; 95/ 0000 96/ 0000; 97/ 0000;98/ 0000; 99/ 0000 100/ 0000;101/ 00~0;102/ 0000; 103/ 0000 ~4/ 0000;105/ 0000;106/ 0000; 107/ 0000 108/ 0000;109/ 0000;110/ 00~0; 111/ 0000 ` 112/ 0000;113/ 0000; 114/ 0000; 115/ 0000 116/ 0000;117/ 0000; 118/ 0000; 119/ 0000 120/ 0000;121/ 0000; 122/ 0000; 123/ 0000 124/ 0000; 125/ 0000; 126/ 0000; 127/ 0000 128/ 1111; 129/ 1101; 130/ 1~11; 131/ 1001 132/ 0111; 133/ 0000; 134/ 0000; 135/ 0000 136/ 1101;137/ 1011; 138/ 10~1; 139/ 0111 140/ 1110;141/ 0000; 142/ 0000; 143/ 0000 144/ 1011; 145/ 1001; 146/ 0111; 147/ L110 148/ 1100; 149/ 0000; 150/ 0000; 151/ 0000 152/ 1001; 153/ 0111; 154/ 1110; 155/ 1100 156/ 1010; 157/ 0000; 158/ 000~; 159/ 0000 160/ 0111; 161/ 1110; 162/ 1100; 163/ 1010 164/ 1000; 165/ 0000; 166/ 0000; 167/ 0000 168/ 0000; 169/ 0000; 170/ 0000; 171/ 0000 172/ 0000; 173/ 0000; 174/ 0000; 175/ 0000 176/ 0000; 177/ 0000; 178/ ~00~; 179/ 0000 180/ 0000; 181/ 0000; 182/ 0000; 183/ 0000 184/ 0000; 185/ 0000; 186/ 0000; 187/ 0000 188/ 0000; 189/~_0000; 190/_0000; 191/ _000 192/ 1101; 193/ 1011; 194/ 1001; 195/ 0111 196/ 1110; 197/ 0000; 198/ 0000; 199/ 0000 200/ 1011; 201/ 1001; 202/ 0111; 203/ 1110 204/ 1100; 205/ 0000; 206/ 0000; 2~7/ 0000 208/ 1001; 209/ 0111; 210/ 1110; 211/ 1100 212/ 1010; 213/ 0000; 214/ 0000; 215/ 0000 216/ 0Ill; 217/ 1110; 218/ 1100; 219/ 1010 220/ 10~0; 221/ 000~; 222/ 0000; 223/ 0000 224/ 1110;. 225/ 1100; 226/ 1010; 227/ 1000 228/ 0110; 229/ 0000; 230/ 0000; 231/ 0000 232/ 0000; 233/ 0000; 234/ 0000; - 235/ 0000 236/ 0000; 237/ ~000; 238/ 0000; 239/ 0000 240/ 0000; 241/ 0000; 242/ 0000; 243/ 0000 244/ 0000' .245/ 0000; 246/ 0~00; 247/ 0000 248/ 0000; 249/ 0~00; 250/ 0000; 251/ 0000 252/ 0000; 253/ ~00~; 254/ 0000; 255/ 0~00 MEMORY UNIT
The calculator uses an all semiconductor memory system. Peripheral circuitry is bipolar and the memory con-sists of n-channel ,UOS read only memory (ROM) and p-channel ~ MOS read~write memory (R~M).
:' Addressing and physical layout of the memory module is done so that the number of words can be increased from 3K
in the basic machine to 7.5R in the largest machine. The smallest increment of memory that can be added is 512 words.
Provisions have been made to contain all add-on RWM within the memory module. Add-on ROM is external to the memory module, behind the display.
The basic machine contains 3~ words o~ memory, organized into 2K x 16 ROM, 512 x 16 and 512 x 6 ~W~. The 16 bit RWM words are divided into 109 user registers (4 `~ words) and 76 words for processor use. The 6 bit RW~ words ; are program steps. The largest machine contains 5~ words o~
ROM and 2.5K words of RWM, of which 512 words are 16 bit.
Read~Write ~emory As shown in Figures 146-150 memory is made up o~ 1024 1, dynamic, Read/write memory chips ~Intel 1103). These ....
de~ices are P-channel, ~OS using silicon gate technology. To maintain the contents of memory, the device must be refreshed every 2 ms. This is accomplished by performing a read cycle at a given address. On each chip are 32 re~resh amplifiers `~ so that each read cycle, 32 cells get refreshed. The entire chip is then re~reshed by cycling through the lower 5 address bits and read~ng each distinct address. The re~resh period is 2~ ~s at least every 2 ms.
Logic levels on all input lines to the RW~ chips are ' .
., .

O to + 16Y. This includes the 3 clock lines (chip select, Y-enable or write, and precharge), 10 address lines, and input data. The output data, however, is a current of 600 or more into lK ohms or less. This low le~el output is "wire-or able~' with other chips to build larger systems.
Read Only Memory As shown in Figure 146, 147, 151, and 152 ROM chips are 4096 bit, n-channel MOS arranged 512 x 8. The devlces are static and consume no power when not enabled. Data is retrieved ~rom the ROMs by pulling the chip enable line ~rom O to + 12v (turning the chip on), addressing the desired cells (O or 4v levels) and selecting ~hich output devices are to be enabled t4v or Ov). The output levels are suf-ficient to drive o~e TTL gate directly, and ca~ be "wire-or/ed" for large systems.
As further shown in Figures 153 and 154A-D, each ROM chip - comprises s~x input buffers. These input buifers generate both the input and its complement. On the basis of the 64 possible combinations o~ the 6-inputs Io-I5, one oi the 64 lines in the decoder is selected. The selected line enables one of the vertical lines in the 64 x 64 bit storage array.
For eæample, let Io - I5 ~ O and I6 ~ I8 be "don't cares".
This means line XOO (octal) is selected.
The two 8 out of 32 select decoders must choose 16 lines from the 64 horizontal lines selected by the vert~cal line XOO. ~The 8 out o~ 32 select decoder is actually a 2 out of 8 decoder repeated 4 times in each of the sections ` A - Bo) The output from four MOS FET's a, b, c, and d are 'rwire or~ed"~ MOS de~ices a', b', c', and d' are also con-- 30 nected similarly. ri I6 and I7 ~ O, horizontal lines lXX, ~ -412-~058760 2XX, 3XX, 5XX, 6X~, 7XX arc groullded in eacll of the four sections A-B. This insures that MOS FET's b, c, d, b', c', and d' are non-conductive. This allows signals on lines OXX
and 4XX to pass into the outp-lt sections through transistors a and a' The output section contains the output buffer, 1 out of 2 decoder, and the output drivers s The output butter provides a stage of gain and "wire or's" 4 lines from the storage array The 1 our of 2 decoder clamps the gates of 2 of the 4 output drivers in each section A-B by enabling either line I8 or its complement (~). This disables 1 of 2 signals coming from the output buffer. The output drivers then can be tied together with line (e) for a 512 x 8 organi-zation.
Each of the above-listed constants and routines and subroutines of basic instructions employed by the calculator is stored in these ROM chips. This is accomplished by parti-tioning the O to 16777 octal addresses of the memory map of ;i Figure 4 into 5121oX 81o blocks which is the capacity of each 4096-bit ROM chip These blocks are represented in the memory map of Figure 155. The next step is the inversion of the 8 bits (if the input was "1", it is now a "O") and com-plimenting of the address (i.e. once the octal addresses O - 16777 are partitioned into 512 x 8 blocks, only the last 3 octal digits are important)~ For this reason, address 7778 goes to 000,7768 goes to 001, ....... , and 000 goes to 7778.
The sixteen bits of each constant and basic instruc-tion are stored in the 5121o x 81o ROM chips by organizing the ROM chips into 64 x 64 bit matrices and computing the ,. . .

row and column numbers of e~ch bit of ench matri~ by operating on each address and the particular bit (15 through 8, or 7 through 0) The column number is computed by subtracting the last two digits o~ the address ~rom 1008 For example, the column number of address 000 = 18 ~ 8 ~ 100 ~ 641o and the column number of address 777 ~ 18 ~ 778 ~ 1. The computation of the row number (referred to as IR in the ~low-chart of Figure 156) can best be described by referring to t~e flowchart o~ Figure 156 and the associated table of Figure 157. Once the row and column numbers are ~ound it is a simple matter of storing in that location of the matrix that partieular bit (i.e., a "1" or a "0"). A "0" is stored at a designated location by forming a metal gate to complete a MOS FET device at that location, and a "1" is stored at a `~ designated location by leaving of~ the metal gate so that a MOS ~ET device is not ~ormed at that location.
~-Register ` As shown in Figures 146, 147, and 158A-D included on the M-Register board is the 16 bit Address or ~-Register, all ` 20 chip enable decoding and bu~fering, and address b~f~ers ~or both ROM and RW~. The register uses ~our, four bit, serial in and out, parallel in and out shi~t Registers. Upon receipt o~ a T-T~ instruction from the microprocessor, serial data from i the T-Bus is accepted into the M-register. Nothing is done with this data unti} either a read or write instruction is received, then one of two decoders are enabled. These chip Enable decoders uni~uely decode which block of 512 words, either RO~ or RMW, ~s being addressed. If ROM is being addressed, .~, the signal is inverted and amplif~ed to +12v. For R~Y~I the Chip Enable enables a gate, which allows a lG Volt cloc~
' -~14-si~nal to re~c~l the en~bled RW~I chips. The clock wave-form is generated on the control card The dynamic characteristic of the RWM chips, requires that all chips be enabled simultaneously during a refresh cycle, to refresh the entire read/write memory. The bu~fer circuits in the output of the Chip Enable decoders allow the chip select clock to reach all of the R~l chips during refresh but only those betng accessed, during a read or write cycle.
Open collector nand gates with resistor pull-ups are used as buffers ior the ~0~ address lines. Using the open collector gates, the address lines can be pulled above the re-quired 4v lev~1. The nand gates àre enabled during a memory cycle so that the RO~ address lines are inhibited at a 5v le~el. The R~l address lines must pull ~rom Ov to ~ 16~.
~igh voltage, open collector, i~erters with discrete transistor pull-ups are used as buffers for the 5 most significant bits.
The 5 least signi~icant address bits are bussed to the control card where they are used i~ part of the refresh circuitry.
Control ~ memory cycle consists o~ a read or write instruction from the processor accompanied by 12 clock pulses ~rom the shift clock. As shown in Figures 146, 147, 159A-~ and 160, control uses these pulses and instructions to generate the clocks required by the RWM chips. A synchronous 4 bit counter (SN74193) is used to count clock pulses a~d the 4 outputs are decoded by a 1 o~ 16 de~oder (SN74154) to generate J and K
i~put to ~l~p-flops. The outputs from the flip-~lops are the~
bu~fered to become the required clock signals (Precharge, ~-enzble, chip select).
Refreshing the read/write memory is zlso taken care of by the control c3rd. An ~st~le multivibr~tor with ~ repetition rate o~ 500 h~ minimum generates a signal whicl~ allo~vs ~ re-~resh cycle to occur. A flip-~lop ~ener~tes the actual signal (REF), but only if the astable multivibrator si~nal is high, there is no read or write cycle in progress and the processor signal, ~E~, is high. ~F~ goes high between processor in-structions, thus it is known that nothing is going to be in-i terrupted when REF is generated. REF is then buf~ered by an ., , open collector in~erter and gtven to the processor as ~R~.
INE halts the machine and the re~resh cycle begins.
; The same counter used ~or a memory cycle, is used during refresh to again generate the necessary clocks (Pre-charge and chip select). When the counter returns to state 0 and REF is present, a second co~nter is advanced one count.
This second counter provides the refresh addresses which go to i the RWM only if REF is present. ~hen this counter returns to state 0, it ca~ses REF and ~E to return to preset couditions ` and the machine continues normal operatlon.
A further function o~ the control card is to make the 1024~1 me~ory chips appear to the processor like 51~ ~ 2 chips.
This is done by accessing the R~nM twice during each memory cycle. Hence, hal~-way through each re~resh or memory cycle a flip-flop changes state to generate one address bit. The ~-register thus provides only 9 address bits and the control card 1 bitJ independent o~ the M-register.
Other signals generated on the control card, direct the ~low o~ data in the T-register.
T-Register 3ata to and from the memory is temporarily stored in the T--re~ister. As shown in Figures 146, 147, ~nd 161A-D four 4-bit, serial in ~nd out, p~rallel in and out shift registers -~16-:

,.
make up the actual T-registcrO Tho registors have a mode control tT~lC) wllicll whcn low, allows serial data flow and when high, allows parallel data flow.
Serial data enters the T-register in tlle presence of a TTT instruction. Data is serially transmitted to the S-bus during a TTS instruction, and simultaneously recirculated into the T-register to prevent loss of data.
Parallel data is accepted from either ROM or RWM
during a read cycle. The ROM data is buffered by nand gates and the RWM by sense amplifiers followed by the same nane gates. Multiplexing the RWM means that only one-half the data bits are transmitted between RWM and the R-register during each half of the memory cycle. The first half of the read cycle, the odd bits are loaded into the T-register. To com-plete the transfer these bits must be shifted right one place ~r~ and the odd bits again loaded from the RWM. This is done by allowing the odd bits to appear as data at the input of the ` even bitso When new data is clocked into the T-register during the second half of the read cycle, the even inputs are also clocked in, filling the T-register. This isn't done with ROhl since all ROM is transferred 16 bits parallelO
Data is written into memory in a manner similar to the way data is read from RWMo The bits are 16v levels, after buffering, and are written by the odd bits followed by the even bits. The nand gates between the T-register and the 16v buffers are gates from the control card to handle the write multiplexing~

_~17-' , INPUT-OUTPUT CONTROL UNIT
The input-output control unit allows the calcu-lator to communicate with the internal input, input-output, and output units and with external peripheral devlces. As shown in Figures 14oA-c and 162A-D, the input-output control unit is contained on two printed circuit boards; the "Control a~d System Clock~ board and the "I/O Register and Gate Interface" board. A third board, shown in Figure 163, is an I/O motherboard providing room for connecting four ex-ternal interface cards to the calculator.
The internal input, input-output, and ouput units are distinguished from peripheral devices by the fact that the I/O language set addresses them directly. Eence each I/O instruction contains an internal peripheral address as part of its makeup. The iive iDternal directly-addressable iDpUt, input-output, and output UDitS are the I/O register, the magnetic card reader, the output printer, the x-, y-, a~d z- register display, and the keyboard mode lights The external peripheral devices are indirectly `~ 20 addressable and are connected via cable to an inter~ace card which is plugged into the I/O motherboard at the rear of the calculator. The term indirectly addressable is de-fined here to mean the ex~ernal peripheral de~ices are addressed by lines leading from the four most significant bits in the I/O register, thereby requiring an address word to be loaded into the directly addressable I/O register.
I/O CONTROL AND SYSTEM CLOCK SECT}ON
:
The fu~nction of the I/O Control and System Clock Section is to provide control to the }/O Register and Gate Interfacc Section. This is accomplished by use o~ an I/O

~ .

instr~lction set stored in the main memory of the calculator.
~` Tlle microprocessor causes instructions from the memory unit to be loaded into the T-Register and then to be transferred to the Q-Register. The microprocessor deter-mines the type of instruction and causes the proper execution of the instruction. If the instruction is an I/0 type, con-trol is transferred by the microprocessor to the I/0 Control ~ and System Clock Section.
; The microprocessor remains in a two state waiting - 10 loop while the I/0 Control section is active. Time in the wait loop is between .72 u seconds and 6.5 u seconds.
i Bits 5 through 10 from the Q-Register are connectedi to the I/0 Control section and remain constant during an ` I/0 instruction execution time. Bits 5 through 8 repre-senting the I/0 instruction code are gated to the I/0 address flip flops and entered on each clock time while the I/0 is inactive. The four outputs of the address flip flops are connected to the address input of a 1 of 16 de-coder and represent the starting state address of the I/0 instruction to be executed. When the I/0 Control Section is enabled, the input gates passing bits 5 through 8 to ; the I/0 address flip flops are closed aDd the 1 of 16 de-coder enabled This allows the starting state I/O micro instructions to come from the 1 of 16 decoder. The next state address coming from the closed input ga~es will be the exit state (1111=178) unless modified by reopening the gates to let the original starting state code through or by modifying the output of one or more of the input gates using a "wire or" connection coming from the 1 of 16 de-coder output. This address is sent to the I/0 address ~x -~19-. . .

~os~760 flip flops inputs nnd clockcd in on thc leadin6 edgc of the first halI clock cycle. The first half clock cycle turns off the 1 of 16 decoder and the address changes. The second half clock cycle enables the 1 of 16 dccoder, allowing the next state micro instruction to appear (See Figure 164 for the timing described above.) This process continues until the exit state is encountered. On the exit state, the I/O Control is disabled and control is returned to the microprocessor.
The I/O instructions involving the transfer of data between the I/O and the CPU (OT, LI, MI), require 16 passes through the same state (1 pass for each of 16 bits). This is achieved by checking the output of a 16 bit down coùnter and then decrementing after each pass through the state.
If the counter indicates "O" has not been reached, it causes the starting state address to be reloaded into the address flip flops by opening the input gates. When 16 passes have been indicated by the counter, the input gates are not allowed to open; however, the next state (1111) is modified by the output of the 1 of 16 decoder through a "wire or"
connection on the 2cd bit to give state 1101. This address is input to the I/O address flip flops as in the preceeding paragraph.
The above-described operation of the I/O control section is also illustrated and further described in the flow chart of Figure 165.
Bit 9 is called a hold/clear bit. It allows a clear flag (CLF) to take place or not to take place after execution of the other I/O instructions. (STF excepted) ! 30 Bit 10 is used in conjunction with the micro instructions -~20-` 1058760 PTR and XTR to give control to the I/O.
Ihe I/O control and programmable clock mnemonics are given in the following table:

CC0 Clock Code Zero CCl " " One `; CC2 " " Two CC4 " " Four CC8 " " Eight CCT Control Clock to Tester CEM Call Extended Memory CLC Clear Control CLF Clear Flag DRC Data Register Clock ! EBT Eight Bit Transfer EOW End of Word IIO Inhibit Internal OSC
INH Inhibit Clock IPS Inhibit Primary/Secondary i ITS Input to S-Bus MCK Memory Clock POP~ Power On Pulse PTR P-Reg to R-Bus QFG Qualifier Flag Q5 " Five Q6 " Six I Q7 " Seven Q8 " Eight Q9 " Nine Q10 " Ten QRD " ROM Disable RCA ROM Clock Address , ItO CONTROL BOARD MNEMNNICS (Continued) RCF ROM Clock Flip Flop ~-~ SCB Set Carry Rit SCK Shift Clock SCT " " to Tester Service Request Acknowledge STC Set Control STF Set Flag TCK Tester Clock TTO T-Bus to Output TTX T-Bus to A/B Reg.
XTO External OSC
XTR A/B Reg. to R-Bus NOTE:
( ) indicates negative true signal I/O REGISTER AND GATE INTERFACE SECTION
As shown in Figure 162, the directly addressable I/O Register (address Ol) is a 16 bit universal (Parallel in/out, Serial in/out) register that is connected to the calculator processor by the serial-in S-Bus and the serial-out T-Bus. Information is passed non-inverted from the A or B regis-ters bit serial to the I/O Register with the I/O instruction OTX ~1. Sixteen lines connected to the parallel outputs of the I/O Register provide data out ~ to the internal input, input-output, and output uni~s and to the external i output interfaces. (NOTE: each I/O unit or interface may place only 1 TTL
load on the output lines~) Parallel entry to the I/O Register is through 12 party lines con-nected to the 12 least significant parallel inputs. The input lines are negative true with all input ' . .
. .

~058760 interfaces tyin~ to the lines tllrou~h open collectors.
Care must be taken to insure there i9 no disturbance to the lines while an interface is inactive. Input informa-tion is passed inverted to the A or B Register Bit serial with the I/0 instructions LIX 01 or MIX 01. (The inversion puts positive true information into the A or B register,) Input information is entered into the I/0 Register in three ways:
a) Service Request.
Entry by the service request method is con-trolled by a service inhibit flip flop. When the service inhibit flip flop has been cleared with the I/0 instruction CLF 01, a service re-quest may be initiated by returning the SSI
(Service Strobe Input) party line to ground through an open collector OD the interface.
This signal causes the parallel inputs to be , strobed into the I/0 Register and sends a re-3 quest for service (QNR) to the microprocessor.
The microprocessor prior to receiving a request , for service would have been cycling through . various instruction paths and checking for a service request after execution of each instruc-tion. Upon receipt of a request for service, the processor interrupts the sequence of instruc-. tions it was doing and loads an address into the M-Register which contains the starting address of the service routine. At the same time a sig-nal, ~ (Service Request Acknowledge), turns , 30 off the service inhibit flip flop and also sets , ~

-~23-~05~760 the single service flip Ilop wllich permits only one service interrupt to the processor per ser-vice strobe input. The single service flip flop is reset when the service strobe is removed.
- All lines from an interface using the service re-quest method for entering information are inhib-ited when the Service Inhibit flip flop is set.
b) Return of Channel Flag After Command .ras Given to an External Peripheral Device.
This method implies the calculator must control , the peripheral. That is to say the calculator transmits the indirect address and control en-able (CE0) from the "I/O Register and gate inter-face" section to the interface with the expecta-tion of information being rel-urned by the peri-pheral through the interface to the I/O Register.
Because of this expectation, only limited instruc-~- tions may be performed by the calculator while waiting. The Service Request method must be inhibited during this wait so that input informa-tion is not destroyed by another peripheral using Service Request.
When a controlled peripheral responds, its flag and data are processed at the interface. The signal CFI (Channel Flag In) causes the loading of parallel data from the interface into the I/O
register and clears the control enable flip flop so that the CEO signal is removed from the inter-face. The calculator can interrogate the Control Enable flip flop with the instructions SFS 01 ., : `
-~2~-' or SFC 01 to determine when data has been loaded in.
c) Giving the I/O Instruction STF 01 The instruction ST~ 01 as described in (a) sets the service inhibit flip flop inhibiting the service request mode of entry. Tlle STF 01 instruction also causes a parallel load of the input lines into the I/O Register.
The I/O Register is used to transfer data and con-trol between the calculator and the directly addressable magnetic card reader (address 02). To record information on a card, the control word and data is transferred from the A Register to the I/O Register. The I/O instruction STC02 clocks this information via MLS into a latch located at the card reader. The strobe bit for the recorded data `~ is output to the I/O negiSter from the B Register. The I/O instruction STF02 clocks the strobe latch located at the card reader via MCR. The I/O instruction STF01 loads ' status from the card reader into the I/O Register (see l-C).
I 20 This status is transferred to the A or B Register where it is processed.
To enter information from the magnetic card reader a control word is transferred from the A-Register to the card reader latch as above. When a strobe is encountered from the card, the card reader sends a signal, MFL, to the I/O Register and gate interface section, which sets the magnetic card flag flip flop. The I/O instruction SFS02 is used to determine the state of the magnetic card flag flip flop. ~Yhen the flip flop is set, data is loaded into the I/O Register with the I/O instruction STF01.

-~5-105~3760 The dircctly-addressable output printer (address 0~) requires 26 bits of parallel information from the calculator.
Sixteen bits come from the I/O Register and 10 bits come from a register at the printer. A 16 bit word with "don't cares" in the least 6 significant bits is transferred to the I/O Register with the I/O instruction OTX 01. A second 16 bit word is transferred to the I/O Register with the instruction OTX 04. The 10 valid printer bits already in the I/O Register overflow into the 10 bit printer register. The significance of the address 0~ in the OTX instruction is that it allows the micro instruction EO~Y (End of ~rord) to set the printer enable flip flop after the 16th bit has been transferred.
At the end of the printers response it returns a signal (PTF) to the printer enable flip flop clearing it. The printer enable flip flop can also be cleared with the I/O
instruction CLF 04. The state of the printer enable flip flop is checked with the I/O instructions SFC 0~ or SFS 04.
The directly-addressab~e output display (address 08) , recieves information from the I/O Register. A 16 bit word is transferred to the I/O Register with the instruction OTX
08. The address 08 allows the display enable flip flop to be set with the micro-instruction EOW after the 16th bit has been transferred. The display enable flip flop sends ` a signal DEN to the display indicating information is readyin the I/O Register. The display enable flip flop is cleared with the I/O instruction CLF 08.
The directly-addressable keyboard indicator lights (address 16) are used to indicate the mode for various keys.
The lights are driven from a latch or series of latches which get information from the I/O negister. Information -~26-~05~760 ; is transIerred to tlle I/O Register Wit]l the I/O instruction OTX 16. After the 16th bit has been transferred, 1:1le micro-instruction EO~V and address 16 send a signal KLS which strobes the information from the I/O Register into the keyboard lights latch.
.::
` The keyboard does not have an address. It transfers information to the CPU through the I/O Register using the Service Request method described in (a) above. The keyboard is disabled while the service inhibit flip flop is set except for the stop key which when depressed sends the signal STP
which is processed independent of the service inhibit flip flop.
All external peripheral interfaces are indirectly ii~
, addressed from the four most significant bits in the I/O

i~ Register. Thus to communicate with an external peripheral, ';
; an address (0000 excluded) must be loaded into the I/O

~ Register. Data and status will be loaded at the same time ;:g if the peripheral is to act as a receiver. If the peripheral is to act as a transmitter, only the address and status need -~ 20 be loaded. Next, the I/O instruction STC 01 sets the Control Enable Out flip flop. This flip flop sends a signal CEO
~` to all external interface slots. The CEO signal and the decoded (from the 4 bit address) address allow the interface to command the peripheral. After the peripheral has responded, information given back to the interface by the peripheral is processed to the I/O Register in the manner described under (b), "Return of Channel Elag A~ter Command was Given to an External Peripheral Device".

The I/O Register and gating control circuit mnemo-nics are given in the following table:

-~27-lOS8760 I/O REGISTER AND GATE BOARD

CEO Control Enable Out CFI Channel Flag In CLF Clear Flag CO0, 1,2,3 Code Out DEN Display Enable DI0, 1,2,3,4,5,6,7 Data In CD0, 1~2,3,4,5,6,7 Data Out DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word IOD I/O Data KLS Key Lights Strobe MCR Mag Card Reset MFL Mag Flag MLS Mag Latch Strobe PEN Printer Enable POP Power On Pulse PTF Printer Flag Q0 Qualifier Bit 0 Ql " "
Q2 " " 2 Q3 " " 3 QFG " Flag QNR " Not Request SIH Service Inhibit SI0, 1,2,3 Status In SO0, 1,2,3 Status Out SRA Service Request Acknowledge SSI Service Strobe In STC Set Control STP Stop STF -428- Set Flag I/O Rl~,Gl.STEr~ ~ND GATJ'T30A~n (C'0)l1lin~1t~tl) 'r~ s T-~us TTO T Bus to Output NOTE:
( ) indicates negative true signal As shown in Figure 166, when addressing a periphcral device, bits loaded into the 4 most significant locations in the I/O re~ister ~rom the CPU constitute the peripheral address code. As part of the output party line system the address code is routed to all I/O interface slots. Each I/O inter-face card decodes the 4 line address code to a unique single `, line for use on that particular I/O card. The binary codes 10 through 15 have been reserved for dedicated peripheral addresses which are used by dedicated keys (from the key-board) and dedicated I/O drivers. Binary codes 1 through 9 are for general use. Code "O" is a non-addressing code and '~ is used in operations that do not involve addressing a specific peripheral. The following table summarizes the address code assignments:
1, , , ADDRESS CODE ASSIGN~IENTS
ADD- 4-BIT ¦ ASSIGNED PERIPHERAL
RESS CODE
Hl{HH TYPEI~RITER
_ .~ 14 HHHL PLOTTER
.~

_ .¦ 12 IlllLL KEYBOARD & XEY'BOARD-LIXE PERIPIIERALS
`.
: 11 HLIII{
}ILIIL

-- liLLll GENERAL USE; ONE OF NINE SELECTABLE
:, 8 IILLL ,.
.~
,. ~ 7 Llll{ll ..
_ 6 Li'lilL
' ' 5 LIILII
4 LIILL ,.
3 LLIIII ..
.~ 2 I,LIII, . 1 LLI,II ,.
~ ;1.1) t).'`; IN'l`l'l~ ll''l' I/t~ At~ CAl~l)S
P 1.1,1,1. WIII-'N ~ l,l uHrl;ltoJI~s ENAI~I.I I) ,_ ,~, --~2 9--The general usage codes (1~9) are decoded outputs from a 4 line to 1 of 10 decoder (SN 7442 for e~amplc). It is in-tended that the codes 1 tllrou~ll 9 be jumpcr selectable. This would allow the user to select a code ~or his system peripherals or allow him to use more than one of the same peripheral by ; selecting different address codes.
Since the I/0 register is used to communicate with the internal input, input-output, and output units as well as peripheral devices, a given peripheral's address code will appear randomly in the I/0 register address field with there being no intention of expecting the peripheral to respond:
Therefore, a second piece of information is necessary for the I/0 interface card to form a unique signal which will indicate to the peripheral to respond. This second piece of informa-tion is control information and is described hereinafter.
The I/0 inter~ace cards contain TTL compatible logic - ~or manipulating control and data from the calculator and/or the peripheral. All I/0 interface cards which are intended to be used with the calculator must provide storage either on the I/0 interface card or in the peripheral. Thus data being transferred from the calculator to the I/0 card must be stored at the instant the peripheral is requested to respond. Like-wise data coming from a peripheral must be stored until the calculator accepts it. This requirement is important and ; must be considered on all compatible interface cards.
The calculator can supply up to 100 ma. maximum at ~5 volts to each I/0 interface card. Power exceeding this abso-lute maximum must be supplied by the peripheral.
The following table lists the pin assignmellts for all I/0 lines at the plug-in slots on the calculator back plane, ~s ~icwcd ~l~om thc rcar oL the calc~llatol-, lort to ri~ht.

EXTEI~NAL I/O INTER~CI~
PIN ~SSIGN~I~N'l`S

2 ~5 B ~5 4 USED D ~ 10/20 ~ ~ 8 DI 3 J DO 3 10 D0 4 L DI 4 ~
! ~ 11 D0 5 - M DI 5 o 13 D0 7 r ~I 7 ~! 19 co 2 W CO 3 i~ 20 SSI ` X SIH

Figure 167 lists all I/O lines with brief de~initions and specifications and Figure 163 shows the source and rela-tive relationship of the I/O lines. The output address data lines (Co 0-3) transmit the address code along the party lines to all interface slots. These lines will go high and low ac-cording to information being shifted in or out of the I/O
Register. At anytime a peripheral is addressed the lines will -~31-beeome steady 1 inSt~ ctioll time (8 IlS) bel`ore eontrol inLorma-tion is passed to t31e I/O interface card or bcrore data or status is taken from the I/O interfaee card or before data or status is taken from the I/O interfaee card and will remain ; eonstant until the eontrol information is removed. After the eontrol information is removed~ the state of the I/O lines beeome unpredictable until the next addressing takes place~
Address data coming to the I/O interface card is positive true and each interface may place 1 TTL load on eaeh address line.
The output data lines (DO 0-7) output data from the A or B accumulator in 8 bit bytes from the 8 least signifieant loeations in the I/O register to all interface card slots.
The logic state is positive true (Data = 1 = High). Eaeh ` interface eard may plaee 1 standard TTL load on each data line.
The output data status lines (SO 0-3) output status data from the A or B aecumulator and are driven from the next four loeations above the data out positions in the I/O register (DO positions = O thru 7; SO positions = 8 thru 11 ) These `~ 20 lines are used for sending additional information to a peri-pheral The logic state is positive true. One standard TTL
load may be plaeed on each output data status line. (Speeial drivers, fast data transfer, and interrupt do not make use of SO 3.) 3 The input data lines (DI 0-7) transmit input data in .
8 bit bytes to the 8 least significant bit positions of the I/O
register (locations 0 thru 7) from the I/O interface card.
~aeh "Data In" line has a lK pull up resistor to +5 volts and under the party line system must be driven low for a logical 1 from open eollector ates on each addressed I/O interface -~32-card, The logic state is negntive true.
The input data status lines (SI 0-3) receive in~orma-tion from the I/0 interface cards and transmit it to loca-tions 8 through 11 in the I/0 register, ~ach line has a lK
pull us resistor to ~5 volts~ These lines are used to provide additional information to the calculator about the state of a peripheral, The logic state is negative true, The negative true "Device Ready" output line (~E~) transmits a control signal, which when combined with an ad-dress code will initiate a peripheral response on the ad-dressed I/0 interface card. Device Ready is controlled by the I/0 interface driver and therefore may look different depending upon the driver. For example, when the calculator wishes to transmit data to the I/0 interface card or to initiate a peripheral response prior to receiving data from the peri-i pheral, the calculator causes the "Device Ready" output line to go low and stay low until the peripheral response is over , and the calculator receives the signal "Device Request" (~~O
J from the I/0 interface cardO The "Device Ready" flip-flop t 20 always receives a clear signal whenever the I/0 register com-; pletes a parallel load.
The "Device Request't party line CFI when driven low from an open collector gate on the I/0 interface card will cause the loading to parallel input information into the 12 least significant locations of the I/0 register. The active state of the line is low (negative true)~
The peripheral ~lag, indicating to the I/~ interface card the peripheral has received data/control or is ready to input data, is gated through an open collector nand gate onto the Device Request (C~I) party line. The open collector gate -~33-~058760 is enabled by t~le I/O interlace card's address and Devicc Ready (~). The Device Requcst line is pulled up inside tllc calculator by a lK resistor to +5 volts.
The Device Request (CFI) signal must stay low until Device Ready (CEO) has been cleared (goes high). At this time data transfer has terminated and peripher~l's flag and control must be cleared in preparation for the next pass~
Since a parallel load in the I/O register causes the Device Ready flip-flop to receive a clear signal, when a Device Request (~F~) is entered, a parallel load takes place and afterward Device Ready (~EO is cleared. The calculator uses Device Request in its general mode of data transfer.
The Half Status output line (~) is a line that goes low when the STOP key on the calculator is depressed. It will stay low for the duration of the key depression. One standard TTL load may be placed on this line by each I/O
interface card.
The Prevent Interrupt output line (~), when low in-dicates to the I/O interface card that a request for service must not be given to the calculator. One standard TTL load may be placed on this line by each I/O interface card.
The Service Request (Lo) line (SSI), when driven low, causes the loading of parallel input information into the 12 least significant locations of the I/O register and causes a CPU interrupt for service. The peripheral's request for service is gated with the Prevent Interrupt (~IO line onto the Service Request party line through an open collector nand gate~ A
lK pull-up resistor to +5 volts is connected to the line in-side the calculator.
The line 10/20 is used on the I/O interface card to -~3~-di~erentiate betwcen the present calculator and other cal-culators, thereby permittin6 the use o~ compatible I/O inter-face c~rds It is grounded in the case of the present cal-culator and open in the case of others.
The general format for all data transfer consists of 8 bit parallel bytes (this calculator, like the Hewlett-Packard model 9100 calculator uses a 7 bit field). Other data ~orm~ts are handled by specially developel drivers, , .................... .
such as the ROM plug-in module employed for dr~ving the type~
writer.
The state o~ a peripheral is generally ch~cked before attempting an output. This is done by first inhibiting the interrupt system. The address of the I/O interface card is shifted into the I/O register. The decoded address code en-;~ ables the open collector gates on the I/O interface card. Thestatus of the peripheral is passed to the Status In lines and loaded into the I/O re~ister with an I/O instruction issued by the calculator. ~he I/O register information is trans-~erred to the A or B accumulator and processed. If the peri-pheral is ready, the output data word consisting of the ad-; dress code, output status (if necessary) and the eight bit data byte is formed in the A or B accumulator. The output data word is transferred to the I/O register a~ter which the Device Ready (~E~) flip-flop is set. The I/O inter~ace card receives the data, address cod and Device Ready and a peri-pheral response is initiated. The calculator interrogates the state of the Device Ready flip-~lop to determine when the I/O
interface card has received the information and the peripheral response is done. The peripheral I/O interface card signals ~0 the calculator it is done ~y transmitting th~ Device Request ., .

., .

(CIF) signal to the calculator. The output waveforms are shown in Fîgure i 168.
Before inputing data from an I/0 interface card it is necessary to determine if the peripheral has responded and is ready to input data.
After a peripheral response has been initiated, as described previously, the calculator waits for the Device Request (CFI) which loads the data into the I/0 Register and clears the Device Ready (CE0). The calculator checks the state of Device Ready and when it goes false ~CE0 = HIGH), the cal-culator knows data is present in the I/0 Register and proceeds to shift it into the A or B accumulators for processing. The input waveforms are shown in Figure 169.
When blocks of data are to be transferred between a peripheral ~ and the calculator, the interrupt is turned off, and transfer rates as high i as 100,000 bits/sec may be possible. Before either input or output of a block of data can start, it is necessary for the calculator to check the status of the peripheral to see if it is turned on and ready. Register will remain unchanged during the block transfer. A single I/0 instruction ~ shifts the 8 bit byte of data from the 8 least significant locations in A
; or B to the 8 data locations in the I/0 Register; gives Device Ready (CE0 goes low) 120 ns after the shift is completed; and shifts the 8 most significant bits in A or B to the 8 least significant locations in A or B in preparation for the next transfer. (Note the Address and status field in the I/0 Register are not disturbed in the shifting.) Device Ready stays true (low) until the peripheral has received the data and is ready for more.
The I/0 inter-., ~OS8760 face card then returns Device Request (CFI) to the calculator. The receiving of Device Request by the calculator causes loading of the parallel input party lines into the input status and input data locations of the I/0 t Register, and clears the Device Ready signal (CE0 goes high). The logic sense of Device Ready is observed by the calculator and when it goes false (CE0 = High) the CPU proceeds to output the next eight bit byte of data.
` If the output I/0 interface card is not returning information on the input lines all input l;nes will be high when the loading, described in the preceeding paragraph, takes place. Therefore, if at the beginning ` 10 the code in the output status field is being used by the I/0 interface card and must remain something other than all high it will be necessary for the I/0 interface card to receive the output status from the calculator and return it back to the status inputs so that when Device Request occurs the status field does not get changed in the I/0 Register.
Input: After determining if the peripheral is ready to start transferring a block of data the calculator turns off the interrupt and shifts the ad-dress code into the I/0 Register. (The Address code remains unchanged during the block transfer.) The Device Ready is given (CE0 = Low) to the calculator when the 8 bit data byte is ready for input. The Device Request signal causes the input data and status to be loaded into the I/0 Register and causes Device Ready to go false (~ High). The calculator by checking when Device Ready goes false knows the data has been loaded. A
single I/0 instruction shifts the 8 bit data byte from the I/0 Register into the 8 most significant locations in thc ~ or B accumulators (shirting tlle previous information in A or B 8 placcs to thc right) and causes Device Ready to go true (CE0 = Low) 120 ns after the last bit has bee~l shifted into A or B. As beforc if output status is to be retained on the I/0 interface card it must be returned to the I/0 Register upon each input data transfer.
Wave forms illustrating high speed operations resemble the wave forms for the calculator in Figures 8 and 9.
The interrupt system is controlled by the Service Inhibit flip-flop. An interrupting peripheral is allowed to request service for input from the processor anytime the Pre-vent Interrupt line is disabled (~IH = High). The calculator ~ allows only those peripherals which use the calculator key-¦ codes to interrupt, and these must be user controlled such that only one interrupt at a time is taking place. Data (keycodes) is loaded into the I/0 Register at the il~stant the Service Request is given by the I/0 interface card (SSI = Low) if Prevent Interrupt is disabled (SIH = High) or if Prevent Interrupt having been enabled (~ = Low) goes high while ', 20 Service Request is being givenO At the same time a qualifier is routed to the CPU indicating a request for service is active.
Recognizing the request for service the CPU branches to the service routine which enables Prevent Interrupt (~E = Low) and j loads the starting address for the software service routine into the M-Register. After servicing the interrupt entry the Prevent Interrupt is disabled (SIH = High) and the next inter-rupt a710wed to take place. The interrupt waveforms are shown in Figure 170.
The following table lists the general I/0 instruction set and the associated codes:
.

, 10587160 ', I /O I NSTI~UCTION SET
.
NAllIl~ lNST~tUCTION INSTl~UCTION CODE
I~XECUTION
_ 'l'I~ 15 1~1 13 12 11 10 9 8 7 G 5 4 3 2 1 _.___ ~ 5~ ~
STF 9 llS H II H II - II L II H Il II SE:LECT CD
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CLF g llS Il IE IE IE - H Il II EI H II "
SFC 9 ,us II H H 1~ - H II/C Il H II L

CLC 9 lls HII H H - H H/C H L IE H
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STC 9 11 s H H H H - H H/C H H L L
_ OT* 15 ~us ~E H H H A/B H II/C LL H II "
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LI * 15 ,us H H H H A/B H H/C L H L H
. _ ._ MI * 15 ,us H H H H A/B H H/C L L L H "

-~39--The following describes the function of each I/0 instruction with the 5 allowable select codes.
STF <SC> Set the flag. STF is a 240 ns positive true pulse which accomplishes the following with the various select codes.
' STF 0~ Not used by the calculator.
; STF ~1 a. Sets the Service Inhibit flip-flop tothe true state (SIH = Low; interrupt not allowed).
b. Causes parallel input data and status to be loaded into the I/0 Reg~ster.
STF 02 Generates a 240 ns positive true MCR pulse for the m2gnetic card reader.
STF P4, P8, 16 Not used by the calculator.
CLF <SC> Clear the flag. CLF is a 240 ns positive true pulse which accomplishes the following with the various select codes.
' CLF P0 Not used by the calculator ` CLF Pl a. Clears the Service Inhibit flip-flop to the false state. (SIH = High; interrupt allowed.) b. Loads address locations in I/0 Register with 0's. (p = Low) c. Clears Device Ready flip-flop (CE0 = High).
CLF`~2 Clears magnetic card reader flag flip-flop.
CLF P4 Clears Printer Enable flip-flop (PEN = Low).
` CLF ~8 Clears Display Enable flip-flop (DEN = High).

lOS8760 ; CLF 16 Generates a 240 ns positive true KLS pulse.SFC <SC> H/C Skip if flag clear. SFC is a 240 ns positive true pulse which accomplishes the following with the various select codes. If C is given a 240 ns CLF pulse is given after SFC.
SFC ~0 Causes the next instruction to be skipped if the STOP key has not been depressed.
SFC 01 Causes the next instruction to be skipped if Device Ready is true (CEO = Low).
SFC 02 Causes the next instruction to be skipped if ' the magnetic card reader flag flip-flop is clear.
SFC 04 Causes the next instruction to be skipped if the printer enable flip-flop is clear. (F~ = Low).
SFS cSC> H/C Skip is flag set. SFS is a 240 ns positive true pulse which accomplishes the following with the various codes. If C is given then a 240 ns CLF
, Pulse ~s issued after SFS.
SFS 0~ Causes the next instruction to be skipped if the STOP key is depressed.
SFS 01 Causes the next instruction to be skipped if Device Ready is false (CEO = High~.
SFS 02 Causes the next instruction to be skipped if the g~gnetic card reader flag flip-flop is set.

~058760 SFS 04 Causes the next instruction to be skipped if the printer enable flip-flop is set (PEN = High).
CLC <SC> H/C Clear Control. CLC is a 240 ns negative true pulse and is not used by the calculator. If C
is given then a 240 ns positive true CLF pulse is given after CLC.
STC <SC> H/C Set the Control. STC is a 240 ns positive true pulse which accomplish~s the following with the various select codes. If C is given a 240 ns CLF pulse is issued after STC.
STC 00 Not used by the calculator.
STC ~1 Sets the Device Ready flip-flop (CEO = Low).
STC 02 Generates a 240 ns positive true MLS pulse for the magnetic card reader.
STC P4, 08, 16 Not used by the calculator.
OTX <SC> H/C Output A or B causes data bits from A or B to be shifted to the I/O Register and accomplishes the ! following with the various select codes. If C
is given, a 240 ns CLF pulse is given after OTX is , 20 executed.
OTX 0P The 8 least significant blts in the A or B register are shifted non-inverted to the 8 least significant locations in the I/O Register, and 120 ns after the 8th shift the Device Ready flip-flop is set (CEO = Low). The 8 most significant bits are shifted right 8 places and the least 8 significant bits are recirculated to the 8 most significant locations in the A or B registers.
The 8 most signifirant bits in the I/O Register are untouched.
OTX 01 Sixteen bits from the A or B register are shlfted non-inverted to the I/O Register. The data in A
or B recirculates.
OTX 02 Not used by the calculator.
OTX 04 Same as OTX ~1 and in addition, 120 ns after the 16th bit has been shifted the printer enable flip-flop is set.
OTX 08 Same as OTX 01 and in addition, 120 ns after the 16th bit has been shifted the display enable flip-flop is set.
OTX 16 Same as OTX 01 and in addition, 120 ns after the ; 16th bit has been shifted the 240 ns KLS signal is generated.
LIX <SC> H/C Load into A or B. Loads data bits from the I/O
Register into the A or B Registers and accompl~shes the following with the various select codes. If C is given, a 240 ns CLF pulse is given after LIX
is executed.
LIX 00 The eight least significant bits in the I/O Register are shifted inverted to the eight most significant locations of A or B, and 120 ns after the 8th shift the 105~760 Device Ready flip-flop is set (CE0 = Low). A
or B is shifted right eight places as the I/0 Register data comes in. The 8 most significant bits in the I/0 Register are untouched.
LIX 01 The 16 bits of the I/0 register are transferred inverted to the A or B register. Data in the I/0 Register is lost.
LIX 02, 04, 08, 16 Not used by the calculator.
MIX <SC> H/C Merge into A or B. Merges data from the I/0 Register into A or B registers and accomplishes , the following with various select codes. If C is given, a 240 ns CLF pulse is given after MIX ~s executed.
MIX 00 The eight least significant bits in the I/0 register are merged with the eight least signifi-cant bits of the A or B register and shifted to the 8 most significant locations of A or B; 120 ns after the merge takes place the Device Ready flip-flop is set (CE0 = Low). A or B shifts right 8 places as the data is merged and shifted to the most significant locations. The 8 most significant bits of the I/0 Register are untouched.
MIX 01 The 16 bits of the I/0 Register are merged with the 16 bits of the A or B register and contained in the A or B register.

105~3760 MIX 02, ~4, 08, 16 Not used by the calculator. Examples of various drivers which transfer data are given below:
Example 1 Typical Subroutine to Get Status of I/O Device.
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Calling Sequence:
LDB Select Code JSM Stat Stat STF 1 Turn off the interrupt system.
OTB 1 Load I/O Register with select code.
STF 1 Load I/O Register with status of I/O device.
LIA 1 Load A Register with status information.
CLF 1 Turn on interrup.
` RET Return.
Example 2: Typical Subroutine to Output an 8 bit character.
Calling Sequence:
OTA 1 Output 16 bits to the I/O Register.

` SFS 1 Loop until I/O flag is set by the . JMP *-1 output device.

20 Example 3: High speed output where the calculator is faster than output device.
Calling Sequence:
ST* I -(Number of 16 bit words to be output) +1 ST* J Address of first word in the array.
; LDB SC Select Code JSM O~T2 OUT2 JSM STAT Get status of output device RAR 9 and position it.

~058760 ', Example 4A: Typical subroutine to input an 8 bit character.
Calling sequence is:
LDB Select code JSM In ... Return is made with the data in the A Register.
IN STF 1 Turn off interrupt system OTB 1 Load I/O Register with the select code STC 1, C Pulse the flag & turn interrupt system on JSM STAT Get status off the input device RAR 9 and position it.
SAP *-2, C If device is busy then continue to loop SAR 7 else position data bits RET Return.
SAP OUT2 If device is busy, continue to loop STF 1 Turn off interrupt system.
OTB 1 Output select code LDB 1 BlCounter for number of words to be output LDA J, I Load next data word SEC *~1, C E~0 OTA 0 Output 8 bits from A
SFS 1 Loop until device sets JMP *-1 flag.
SEC *-3, S If E=0 and E+J then loop to output last 8 bits ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished.
CLF 1 Turn on interrupt system RET Return Example 3B: If the output device is faster than the calculator then fewer in-~; 30 structions can be used.

. , ~, lOS8760 OTA 0 Output first 8 bits OTA 0 Output second 8 bits.

ExamPle SA: High speed input where the calculator is faster than the input device.
Calling sequence:
ST* I -(Number of 16 bit words to be input) + 1 ST* J Address ~, LDB SC Select code JSM In2 In 2 JSM STAT Get status of input device RAR 9 and position it.
SAP In2 If device is busy, continue to loop STF 1 Turn off interrupt system OTB 1 Output select code STC 1 Command device to read LDB I R+Counter for number of words to be input SEC *+1, C E~P
SFS 1 Loop untll input JMP *-1 devlce sets flag LIA 0 Load 8 bits from I/O Register SEC *-3, S If E=0 and E~l then loop to input last 8 bits STA J, I Save data word in array ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished.
; CLF 1 Turn on interrupt system RET Return Example 5B: If the input device is faster than the calculator then the number of instructions can be reduced.

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105~3760 LIA 0 Input first 8 bits LIA 0 Input second 8 bits .
All output I/0 interface cards which are to be fully inter-changeable with both the present and other calculators must have storage either on the I/0 interface card or in the peripheral to which information is being transmitted. Figure 171 illustrates the logic used to interface an X-Y plotter which has storage on the I/0 interface card.
Blocks (A) and (B) are the storage latches which store information coming from the I/0 register. When the nutput of gate (C) goes high, data is latched; when low, the outputs of the latch track the inputs. Gates (D) decode the Address code (14 = 1110) and pass it positive true to gate (E).
Dev~ce Ready (CE0) is also passed positive true to gate (E). Gates (H) are open collector and pass status and Device Request (CFI) onto the input party lines. An example of a 9810A output would be: Output the address 14 which enables status gates (H) and see if the power is on. If on, output address, status, and data to gates (A), (B), and (D). The output of (C) is low allowing data and status to pass. Next give Device Ready (CE0 = Low) this enables flip-flop (G), clocks flip-flop (F) which causes (A) and (B) to latch, and sends - control to the peripheral. The peripheral acknowledges receipt of control by returning FLAG (FLAG = High) in a busy state this continues to keep (A) and (B) latched and clears control flip-flop (F). When ~058760 thc pcriplleral is done acting, thc FL~G is ret~lrned to thc not busy statc (FLAG = Low) which clocks flip-flop (G) and causes output at (C) to go low enablillg (A) and (B). The output of (G) drives the CFI gate which has been enabled from (E) and CFI goes low. -~ is received by the calculator which responds by returnillg CEO high This causes the output of (E) to go low~ clearing flip-flop (G) and returning CFI
high. This completes 1 output cycle.
All input I/O interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/O interface card or in the peripheral from which information is being received. Figure 172 illustrates the logic required on a general purpose interface card with storageO
Block (A) is used to store information coming from the peripheralO (B) stores status coming from the I/O-register which may be needed by the peripheralO The output tracks the input whenever the enable on the latch is low.
Block (C) decodes the address code into one of 10 addresses 2Q which are jumper selectable. An example of a calculator input would be as follows. The ad~l-ess code would be de-coded by (C)O The calculator would load status through the open collector input status gates (D). If the peripheral is on and ready, the address code and output status (if necessary) would be sent to (B) and (C). The decoded address is passed, ; positive true, to gate (E). The enable at (B) is low so that status is passed to the peripheral. The Device Ready is given (CEO = Low) and comes to (E) positive true. The output of (E) clocks Ilip-flop (F) through gate (H)~ The Z 30 output of (F) gives control to the peripheral and also enables -(A) to receivc data. The periphcral responds in a busy state (FLAG = lli~h). ~hcn data is ready to be input the FLAG is driven lowO Data is latched when the FLAG goes low in (~). Also when FLAG ~oes low, (C), having been enabled by the output of (Il), is clockcd driving (J) from its Q output. (I) is enabled by the output of (II) and so CFI is driven low. Data is loaded into the I/O
register from open collector gates ~I) and CEO driven high as a result of the calculator receiving CFI This clears flip-flop (G) and disables the input gates (I) completing an input cycleO
Figure 173 illustrates the logic required, on an I/O interface board, to input using the interrupt.
A power preset eircuit, bloek (A), will be neees~
sary on this eard to prevent an interrupt when the peripheral power is turned o$f or on7 This can usually be done by sensing the peripherals' +5 volts and presetting when the voltage drops below 3 to 4 volts.
The calculator must be in a display routine such that the Prevent Interrupt is false (~I~ = High) before an interrupt can take place. This enables the flip-flop (B) to be clocked from the peripheral FLAG. The cloc~
inputs to ~E) and (F) have been high enabling the storage latches prior to the receipt of FLAG. FLAG clocks (B) causing (E) and (F) to latch, enabling open collector gates (H) throuDh gates (I) and (J), and drives gate (G) which sends Service Interrupt (SSI = Low) to the calculator.
The calculator responds by loading the data into the I/O
register and returning Prevent Interrupt true (~r~ = Low).
This clears (B). Prevent Interrupt is rcturned false after the entry has becn processod and the cycle is completc.

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i KEYBOA~D INPUT UNIT
The keyboard input unit is shown in Fi~ures 174A-D and 175. It include~ a contactless keyboard of the type shown and described in U S Patent 3,668,697, issued June 6, 1972.
The contactless keyboard is made up of an array of printed circuit transformers. Each transformer has its secondary and primary interlaced in a spiral coil as shown in Figures 176-177. The secondaries o~ all the coils are tied in series to form the sense line. The primaries of the coils are arranged in sep~rate pairs. Each coil is connected i~ series, with opposite polarity, to its pair as shown in Figure 178.
Every pair has a dr~ve and sink line, which is bel~g selected and driven by the scanner.
Centered above each coil is a metal disc at the end of the key shaft. When a key is depressed the disc proxi-mates the coil. The disc acts like a shorted turn and re-duces the coupling of the coil, and unbalances t~e pair.
This unbalance is amplii'ied by the comparator~ when it is greater than the on bias. The comparator triggers the one ., .
shot, which turns off the scanner and lowers the on bias.
The scanner remains at its present state, which corresponds to the drive and sink line of the key depressed. This state is the keycode of the key pressed. When the key is released a spring retracks the key and disc. When the unbalance is less than the new bias, the comparator turns off ~nd the scanner starts again ready for a new key. The two bias levels give the key mechanical hysteresis.
Whe~ two keys are depressed the first one do-~n will . . .

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105#760 be entcred, and as long as a key is down no other Icey call be entered. An exception is wllen the other kcy is its pair. In this case the t~vo keys will cancel each other. Whcll tlle first key is released, the second one ~vill bc entcred. ~Yhen the first key is released, while more tllan one other key is down, the next key to be entered will be the next in the scan sequence, not necessarily the second key down.
For the keyboard to work each pair of primary coils must be balanced. To balance a pair of coils tlle following rules should be used when laying out the printed circuit board:
1 Sense lines must run in pairs. The closer the better They should be thin traces.
2. The sense windings of a pair of coils can be anywhere on the sense line. For best results they should be close.
30 Drive lines should be in pairs when possible. Drive clamp and source lines should be grouped together well away from the sense lines. When a drive line crosses a sense line it should be at right anglesO
`~ 20 4. Connect to spiral so to add a turn (or part of a turn) not to subtract. Try to duplicate additional turns on a spiral ;~ pair. Connect to spiral at a right angle, from a distance.
5. For a pair of spirals separated by some distance, run the common connection away from the sense line and in the -~ drive grouping.
6. Check each pair of spirals for errors in drive or sense polarity. This can cause either an incorrect code (least digit), or a constant full output. One method to check ~,, for proper polarity is to assign current direction for both drive and sense. Then at each spiral check for proper polarity. This is illustrated in Figure 179.

MAGNETIC CARD READING AND RECORDING UNIT
The magnetic card reading and recording unit is shown in the block diagram of Figure 180 and in the detailed schematic diagram of Figure 1~1.
The manner in whlch it interacts with the calculator and operates to record and load secure and unsecure programs and to separately record and load data is shown and described in the block diagram of Figure 182, the flow charts of Figures 60-61 and 63-65, and in the memory map of Figure 62.
Operation of the card reader is largely automatic. It is only necessary to specify the type of operation and the limits desired. These commands are entered via the calculator keyboard. The calculator then determines the necessary commands required to cause the magnetic card reader to perform the desired operation.
- Several modes of operation are possible. Programs can be recorded . on magnetic cards and loaded back into the calculator. Similarly, program and data information can be recorded and loaded, or data alone. Very long programs or blocks of data can be stored on several cards. The information is loaded back into the calculator by inserting the cards into the reader in the same sequence as they were recorded. The proper linking of the information ` stored on the cards is automatically performed by the calculator.
Information is stored on the magnetic card in 3 bit bytes. Three tracks record the in~ormation and a fourth track provides a timing mark. Two bytes form six bit words in the calculator. The card reader automatically begins and terminates the recording, irrespective of the length of card used.
D1fferent card lengths can be mixed together without affecting _ ~ 53-, 105~760 tlle OpCl'~tiOI~ O:r t~ l'C~(ICl'. Cal~ds )ll~y l~C i~ rclt~ rcd fl~om one calc-llator to anotllel.
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No mecl-anic; l switchcs are uscd in llle cald reaàcl-.
Tlle only movin~r p~rt is tllc card drive motor and c~pstanO
The mecllanical assembly and electl onics asscmbly are modular and can be replaced as separate and independent units in tlle -; calculator.
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' . -OUT~UT DISPLAY UNIT
As shown in Figures 183 and 184A-B, the output display unit includes three fifteen-character rows of seven-segment light-emitting diode arrays, Each array requires an anode driver ~or each of its seven segments and one for the decimal point.
' The cathodes are common to all the diodés in one character.
Respective anodes for the characters of a register are tied - together to one driver. A series PNP transistor enables one of three sets o~ eight anode drivers each. The cathodes o~ a column of three characters are tied together to one of ~i~teen cathode drivers.
The data required to operate the display is as ? ~ollows 1. Four bits to determine the column to be enabled.
2. O~e of three bits to determine the register.
3, Eight bits to determine the diodes of a character to be lighted.
4. A line to enable the display when the data is pres~nt.
The duty cycle is less than 1/45 requiring pulses o~
more current than a character could stand continuously. A
retriggerable one shot is fired at every display enable pulse and will disable the column drivers after 1/2 ms. i~ the machine han~s up.
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105~760 OUTPUT PRINTE~ UNIT
Several methods have been described for producing printed characters by thermnl means (see particularly U.S.
Patent 3,161,457 issued to ~. Schroe~er et al) but they typically employ a rectangular matrix o~ resistors to form an entire character at once. Commercial versions of this sort of printer are marketed by National Cash ~egister and Texas }nstruments. As described in Schroeder's patent, a matrix ` ~ive elements wide and seven elements high is typically em-ployed.

The output printer unit employed in this calculator is i constructed as ~hown in Figures 185, 186, 187A-B, 188, 189A-D, and l9lA-s~ It includes a row or print elements distributed ~ 5~
~, linearly aCroQs a printing head, as shown in Figure 188, to ~.
~ print a 16-character iine. Each print element i9 an electrical resistor, of a size and shape intended to produce a dot on ; thermally-sensitive paper moved at right angles to the line of ;~ print elements. Dots are formed in the conventional manner ~y pulsing the re3istor element with a pul~e of electrical current, which raises its temperatur by joule heating.

Each o~ the sixteen characters of each line is ~ormed in a 5 x 7 dot matri~. ~or example, as illustrated in ~igure 192 the letter A is produced by printing the darkened dots in the top row and then stepping down to the ne~t row, etc.
Each line o~ print coutains sixteen 5 ~ 7 matrices.
The matrices are made o~ seven rows o~ 80 dots spaced in five dot groups to produce sixteen characters. The printer pro-duces each line~of print by printing the top row of all six-teen characters and then stepping do~n to print row 2 until all seven rows are printed. Three blnnk steps ~re t~en added lOS8760 ,:
to prod~lce thc sp~cc betwcen lines.
Each of thc seven rows o~ printin~ contains 80 dots ~ (5 for each of the SiXtCell characters) whicll m~y or may not be ;~ printed~ This requires tllat eigllty in~ormation bits be sup-plied for each row printed. To accomplisll this, each row is split into four groups of twenty dots (four char~cters).
(Since the I/0 Register of the calculator is only sixteen bits long an extra ten bit shift register is contained in the printer hardware ) Each group of 20 bits is transmitted to the printer along with the group number by the I/0 Register and i.s printed when the printer enable signal is given.
The printer then prints that group of dots and returns a printer flag signal to the calculator. The next group of in-formation is then supplied until all 28 groups have been ` printed. The three step commands are then gi~en to provide the space between linesO
The printer requires the following information to print any group of dots:
(1) Dots to be printed, Y 20 (2~ Group number, and ; (3~ Printer enable.
As shown and described in the flow chart of Figure 193, this information is transmitted to the printer through the cal-culator I/0 register. Since the total number of information bits needed is greater than the I/0 registers length, two 16 bit words are transmitted to the printerO The first 16 bit word contains the dot patterns for characters 1 and 2 as shown in the following table:

-~57-''` 1058760 CONTl;.NT OF I /O I~I~GI STl~:n I~Fl']~.R EII~ST LOI~DING
:: Character 2 Chal ~ctcl.~ 1 . .
j L }l ~ ll L ll r 1~ 11 l l ., Dot ~ Dot Dot l Dot ~ 0 0 ¦ 0 ¦ 0 0 C03 C02 C01 C00 S03 S02 S01 S00 D07 D06 D05 D0~ D03 D02 D01 D0 - Don't Care :
.~ Character one is containcd in bits S02-S00 and DO7, DO6 with the left dot in bit S02 and the right dot in DOG, Character ~; 2 is contained in bit C03-C00 and S03 with the left dot in ,. C03 and the right dot in S03. When the I/O Register is .~ loaded with the second 16 bit word these bits ~vill appear in ,~ .
the internal 10 bit shift register. The second 16 bit word contains the dot pattern for characters 3 and 4 and the group number as shown in the following table:
~.1 I/O REGISTER AFTER SECOND LOADING
~ Character 4 Character 3 Group :~. , --~ __ _ , - ~ C~ ,--_~
., L H R H L H¦ R H O 1 Dot Dot Dot¦ Dot 0 0 0 0 1 1 . C03 C02 C01 C00 S03 S02 S01 S0~ D0? D06 D05 D04 D03 D02 D01 D00 , 0 - Don' t Care .' Character 3 is contained in bits S02-S00 and D07, D06 With the left dot in S02 and the right dot in D06. Character 4 . is contained in bits C03-C00 and S03 with the left dot in C03 ' and the right dot in S03. The group number is contained in bits D00 and D02. Groups are numbered as follows:

. From Left to Right 1 1, 2, 3, 4 o 0 2 5, 6, 7, 8 0 3 9, 10, 11, 12 1 0 -~ 4 13, 14, 15, 16 When group 4 is detected the printer automatically steps to the next line. The time interval between printer enable and the return of printer flag is extendcd to allow the system 30to physically move~
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' - lOS8760 The printin~ speed is given in tlle following table:
Group 18 ms Group 28 ms Group 38 ms . Group 418 ms Row 1 42 ms Row 2 42 ms Row 3 42 ms i Row 4 42 ms Row 5 42 ms ~ Row 6 42 ms '!' Row 7 42 ms Space 18 ms ~ Space 18 ms .~ Space 18 ms '~h Total Time to Pri~t 1 line348 ms .
~ Lines per second 2.87 ms :~ As shown in Figures 185-186, paper is loaded into the output printer unit by li~ting the wire bucket cover 220 and placing a roll of paper 222 with the fres end into the paper bucket ~ormed by the front and rear bucket halves, 224 and 226 respectively. The o~ly care needed by the operator is to be sure that the paper uprolls for~ard from the bottom. The : wire bucket cover performs a dual ~unction o~ keeping the ~ree end o~ the paper in the bucket while loading and after the paper is loaded prevents the ~ree end ~rom reloading itself through the mechanism.
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- 1~58760 Tho wcigl1~ ol` tl~c pa~Cl` thCIl Stl'CtCIleS thc l:'UI)bCr belts 228 a11c~ c J-O].1 Or p;~l cl lO~ ; rOr~v.-r(l u~ ] it rcsts a~ail1st tl1c pal~cl~ ~ui~1c 230 T11c p:lpcr l~olls forward dl1c to t11e "~wl1llil]" slopc ~l: t)1c ~c]t rrom tl1c top Or tl1e rear idlcl pullcy 232 l;o 1;he ~o~lo1n o~ tl~c papcr gl1ic1c.
1Yith the roll ol p.lpcr in tl1c position dcscli1~cd above the belts IllOVillg Iorward, thc frce cnd oI the pa1~cr is con-strai1lcd by tl)e l~elts, papc!r guidc alld roll to move ~elow thc pape) guide and bet~vcen it and thc bclts.
,., Tlle belts are driven by tl~e drivc pulley 234 w11ic1 ^; is in turn drivcn by a gCal` set Lro111 thc p]aten 236. The platen is driven by the motor 238 via a belt and gear set.
The dimneter and speed o~ tlle platen is such that its sur-face speed is ap~roximatclr 5~ faster t11an ~:h~t of 11.~ 7tc j to insurc that the paper is always under tension after loading is completed. Thc drive and rear idler pulleys are crowned so that t11e ~elts will bc self-centering. The front idler pulley 270 is flat and serves to keep the lower portion of the belt out o~ the bucket area.
The print head 242 is pressed against the paper and ;~ platen by means of a spring, hence it is necessary to remove the print head from the platen while loading paper. This ~i is accomplished by the head lifter and paper de~lector 244 such that whell it is rotated on its axis it cams the print , head off the platen and positions a small plate in the path ~`; of the paper which guides the paper up and between the platen and print head.
The paper is guided through t11e mechanism while loading and while the printer is working by edge guiding the paper. Ordinarily paper docs not lend itself well to edge ~` ~ guiding due to its very lo~ CompICSSiVe strength. To over-come this the paper is bent around the convex bottom sur-face of the paper guide and the belt, w11icl1 is under tension, is very near thc edge thereby preventing thc paper from buckling. The relationship of the paper, papcr guide and belts can be seen by looking at Section AA of Figure 186.
When se]ccting materials for the various parts of the loading mec11anism it is important to be sure that the coefficients of friction between the various parts are compatible. The C.F. between the paper and paper guide should be low relative to the C.F. between the paper and belts in order that thc belts can drive the paper thloug11 the mechanis1n. Similarly, the C.F. between t1le paper and platen should ~e higll relative to the C.F. between print head and paper in order that tlle paper can be driven through while printing In addition, the drag introduccd by the belt and paper guide due to the papcr moving faster than~the belt w11ile printing must not be so great as to tear the paper or impose all impossible load 01l thc motor.

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Thc right hal~ of top pallcl 90 ol 1:hc calc~llator housing is hinged at tllc l~aclc and providcd with a handle 24~
at the front so that it may readily be raised by the user and stopped at an obliquc uprigllt position to expose and facili-tate replenishment ol the supply of thermal-sensitive paper for the output printer unit and also to serve as a music .
stand for holding operating or program-running instructions :~ or any other material the user desired. A transparent plastic retainer is mounted on the underside of the hinged right half of the top panel 90 to hold such materialO

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POWER SUPPLY
The power supply system employed in the calculator ; is constructed as shcwn in Figures 194-196 and 197A-B. As ~hown in ,............................................................... .
~ Figure 194, a centertapped transformer secondary is connected ; to terminals 2-3, 2-1, 2~2, and 2-4. The AC voltage from the ` :~
transformer is rectified by diodes CRl and CR2 and filtered by capacitor Cl. The output of this rectifier/filter circuit is nominally 18 volts DC st 2.7 amps with a 2 volt peak to peak ripple.
. ~, ........ .
~ 10 Ql and Q2 serve as a switch to connect the five volt .
output bus to the 18 volt unregulated supply through inductors Ll and L2. CR3 serYes to clamp the input of Ll to ground when Ql and Q2 are switched off. Current flow in Ll and L2 are sub~tantially constant and equal to the load current.
Loss in high current transistor Q2 is mini~nized be-cause Q2 can be completely saturated. Loss in driver tran-sistor Ql is minimi2ed because Ql can also be saturated. Re-sistor R7 limits the maximum drive current to Q2. Losses in R7 can be minimized by proper positioning of the tap on Ll consistent with transistor parameters and circuit require-ments.
ICl is a linear differential amplifier integrated circuit to drive Ql and Q2. Any differential ampli~ier with sufficient voltage capability and bandwidth will work. Since the amplifier employed ~s linear, R7 a~d R4 ha~e been included in the circuit to provide sufficient hysteresis for reliable switching. This hysteresis stabilizes the switching ~requency and thus stabiiizes the switching losses.
Because hysteresis has been added to the circuit, a significant ripple signal (at the switchin~ ~requency) must -~62-/--be present on tho feedb~ck sign~l to the amplifier This need for a ripple sig~lal limits the amount of capacity that can appear between the output of Ll and groulld. L2 serves to isolate this point from the rest of the system. The amount of capacity that can appear between the output o~
. .
L2 and ~round is essentially unlimited and si~nificantly reduces power supply ripple, and greatly improves response to load transients The second winding of L2 is a path for the feedback ;
10 from the remote sensing. The required ripple signal is added i to the feedback signal by transformer action in L2. Another possible configuration is shown in Flgure 198.
The power supply also includes an overvoltage crowbar ' circuit (Qr, CR4, and R9~ and a short circuit shut-down circuit (using Q5). In the e~ent that ~he +5 volt bus is grounded, or the crowbar is triggered, Q5 saturates and locks ` ICl off.
The resistor R8 makes a current generator of ICl. Re-sistors R5 and R6 discharge the bases of Ql and Q2 respecti~ely.
20 IC2 and its associ~ted components generate a "power on pulse't to initialize the instrument. ICl is referenced and powered .~
~rom an egternal +12 volt supply. Powering the IC from +12 rather than the unregulated +18 reduces power dissipation in ICl.
The +24 volt supply of Figure 196 is referenced by the +16 volt supply with the amplifier common returning to +12 volts to minimize power loss and voltage stress in ICl o~
Figure 196. Thè tl2 volt supply of Figure 197A references the -12, +5, and i16 supplies directly. The ~12 amplifier ICl of Figure 197A may be biased either from the unregulated ~upply ,...
for tho +12 volt supply or Lrom tllc operating +lG volt supply.
Diodes CR5 and CRG dctcrmine the nppropriate sourcc. This providcs a greater power supply margin for the +12 volt supply.
Similarly the +lG volt amplificr is biased from the +20 to ~ .
~ive that supply greater mar~in.
:.
All supplies except the +20 volt supply are current limited. The +24 volt supply is current limited at a value greater than the rating of its series fuse. If a short circuit occurs in the +24 volt supply, it will current limit until the fuse opensO The average current from this supply is 1.1 amps with transients to 2 amps. The current limit is set to 2.5 amps. There is not sufficient thermal capacity available to allow Ql of Figure 196 to carry sustained short circuit current so the fuse has been included to protect the various power supply components. All supplies except the +20 volt supply are crowbar protected against over-voltage.

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TYPE~RITER INTERFACE
This interface couples the Facit-Odllner model 3841 output typewriter to the calculator.
The unit mounts directly on the back of the typewriter.
Communications with the calculator are made tllrough about five ., feet of cable which is terminated by the I/O plug containing a board for buffering and some lo~ic.
Referring to Figures 199A-B and 200A-C, characters from the calculator appear on the data lines as ASCII codes. These codes ~e recoded by a ROM into the six bit Facit*typewriter code for the 46 type bars, and one bit for upper case shift.
- Functions such as space, tab, line feed, etc. are recoded for easy recognition in the interface since each function must ;~ be driven by a separate line. A data latch after the RO~
holds codes for processing. If new data arrives during this processing, the t~o codes are compared to determine if they both drive the same type bar and if they are both numbers.
Non-repeating numbers can be typed at 14.5 characters per i~ second, otherwise typing speed is 12 characters per second ~reduce these speeds 17~ for 50HZ operation). Codes in the latch are gated to the program solenoids or the function :
solenoids by the control logic.
To understand the coding, notice that two blocks of codes on the Facit typewriter code map are empty. If all function codes are put in these blocks, they can be identified by contro~ logic by testing for (~-4). Each function code puts a 1 on one of five lines and this line opens the correct solenoid gate `~ 8it 8 is use~ to discriminate between two sets of function gates. In the case of a program solenoid code, bit 8 identifies numerals.
* trade mark The control clock is provided by a sync. pulse which is generated in the typewriter by a vaned wheel attached to the end of the main drive shaft. The ~anes interrupt a light beam. When a type cycle is initiated, a modulo eight counter counts sync. pulses and the count is decoded by a 1 or 8 decoder. At each of the eight st~tes~ combinational logic can enable solenoid gates, set or clear flag ~lip-~lops or change the counter to state zero, or state 6, or inhibit the countor.
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Claims (4)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An electronic calculator comprising: keyboard input means including a plurality of keys for entering information into the calculator; memory means for storing information that has been entered into the calculator; processing means, coupled to the keyboard input means and memory means, for processing information stored in the memory means to perform selected functions; output means, coupled to the processing means, for selectively providing an indication of the results of information processed by the processing means; the keyboard input means including a plurality of definable keys, each of which may be associated with a function defined by the user, and a plurality of control keys for defining a function and for associating that defined function with a selected one of the plurality of definable keys; the processing means being responsive to actuation of a selected one of the plurality of definable keys that has previously been associated with a defined function for performing that associated defined function.

2. An electronic calculator as in claim 1 wherein the memory means stores each function that has been defined and associated with a selected one of the plurality of definable keys.

3. An electronic calculator as in claim 2 wherein: the keyboard input means includes a plurality of editing control keys for selectively altering information stored in the memory means, and further includes a memory protect control key; and the processing means is responsive to actuation of the memory protect control key, following association of a defined function with a selected one of the plurality of definable keys, for inhibiting the alteration of that defined function.

4. An electronic calculator as in claim 3 further comprising:
magnetic reading and recording means for loading information stored on an external magnetic record member into the memory means and for recording information stored in the memory means onto an external magnetic record member; the keyboard input means including reading and recording control means for initiating the transfer of information between the memory means and an external magnetic record member; the processing means being responsive to selective actuation of the read-ing and recording control means for causing the transfer of information between the memory means and an external magnetic record member; the keyboard input means including memory protect control means for designating a memory protect mode of operation of the calculator; the processing means being responsive to actuation of the memory protect control means for thereafter inhibiting the transfer of information from the memory means to an external magnetic record member.