CA1058328A - Complementary enhancement mode mos transistor structure with silicon gate - Google Patents

Abstract

COMPLEMENTARY ENHANCEMENT MODE MOS
TRANSISTOR STRUCTURE WITH SILICON GATE
Abstract of the Disclosure A p+ doped silicon gate metal oxide comple-mentary transistor structure fabricated on a p-type substrate of semiconductor material with an insulating layer of silicon dioxide on the surface of the substrate and an outer layer of glass disposed over the insulating layer, An intermediate layer of electrically conductive p+ doped polycrystalline silicon is disposed between the layers of silicon dioxide and glass, This layer forms the silicon gate for enhancement mode complementary MOS transistors.

Description

Background of the Invention Field of the Invention . . .
This invention relates generally to integrated circuit technology and more particularly to a p+ doped silicon gate semiconductor device fabricated on a p-type substrate, Descri~tion of the Prior Art .

In conventional complementary MOS transistor structures, a n-type substrate is commonly used, P-channel devices are fabricated in the n-type substrate background whlle the n-channel devlces are fabricated in a p-type "well" disposed in the substrate. When an aluminum gate is used, the work function di~ference between the alumlnum and silicon together with the positive surface state charge, tends to make the flat-band voltage negative, Accordingly, to prevent the n-channel transistor from becoming a depletion mode ~.

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, 43, 144 1~583Z8 device, a relatively heavily doped p-type well must be utilized, For high fre~uency operation, it is necessary to reduce the channel length, Unfortunately, when channel length is reduced to a few microns, the punch-through voltage becomes very low, Thus, in conventional complementary MOS structures, the p-channel length is o~ten made larger than the n-channel length to avoid the punch-through e~ect, Thls is not desirable, however, because ~or symmetrical characteristics, the p-channel MOS tran~lstor should have a narrower length to com-pensate ~or the lower mobility of the holes, In other words, it is more desirable to fabricate the p-channel device on a more highly doped background, Moreover, in silicon gate technology, the threshold voltage ~or p-channel transistors is differ- -ent from that for aluminum gate devices due to the difference in work ~unction, A p-doped silicon gate p-channel device fabricated on low surface state density -~
surfaces such as ~100~ oriented crystals tends to operate in the depletion mode, Similarly, an n-doped silicon gate n-channel device also tends to operate in the depletion mode unless the high impurlty concentra-tion p-type substrate ls used, This high concentration increases the stray capacitance and deteriorates the ~requency response, Where, however~ silicon gate tech-nology is used on high sur~ace charge density surfaces such as ~111> oriented crystals, the p-channel MOS tran-sistor will operate in the enhancement modeJ but the n-channel devices will further tend to be in the de-43,1L~4 :. ' ~5~3328 ~

pletion mode, Thus if conventional silicon gate tech- :
nology is to be utilized for enhancement mode complemen-tary MOS devlces, neither the <100> crystal orientation nor the ~111> crystal orientation can satisfy the requirements, Summary of the Invention Briefly, the subject invention overcomes the foregoing problems by the provislon of a metal oxide semiconductor structure comprised of a body or sub- ;~
strate of p-type semiconductor material having a rela-tively light doping concentration with an insulating layer of silicon dioxide fabricated thereon, A layer of p+ doped polycrystalline silicon or a metal of com-parable work function is disposed over the ~ilicon dioxide layer and an outer layer of glass is disposed over the intermediate layer of polycrystalline silicon, This polycrystalline silicon layer is used as a p+
doped gate for not only n+channel MOS transistors, but is particularly adapked to provide an enhancement mode complementary MOS transistor structure by the inclusion of an n-type well of relatively high doping concentra-tion diffused in the p-substrate. Aligned openings are further provided at least in the outer and inter-mediate layers to provide for metal electrodes contact-ing various regions, Brief Descri~tion o~ the Drawin~s Figures 1 through 7 are sectional views show-ing the sequential steps of the preparation of a single n+channel metal o~ide semiconductor device according to the present invention;

-. ~3,144 Figure 8 is an enlarged sectional view o~ the preferred embodiment o~ the sub~ect invention and being illustrative o~ complementary MOS transistors ~abri-cated within a common substrate; and Figure 9 is a graph helpful in understanding the sub~ect invention. ~ -DescriF~t$on of the Preferred Embodiments Gen~rally, the production of reliable semi-conductor structures involve the comblnation of tech-inques utilizing vapor deposition of thin metal films, glass formation, and annealing, In Figure 1, a semiconductor wafer, generally indicated by re~erence numeral 11, comprises a body or substrate o~ slngle crystal<lOO>oriented silicon o~ p-type conductivity and havlng a planar outer sur~ace 15, An insulating layer 21 is shown in Flgure 2 consisting of silicon dioxide is applied on the surface 15 of the substrate 11 such as by placing the wafer in an oxidizing atmosphere such as oxygen or steam at a high temperature until the silicon dioxide layer 21 is :
formed to a thickness ranging ~rom about 800A to 1600A~
The wafer 11 is then cleaned in boiling concentrated :
sulfuric acid and rinsed in successive rinses of a deionized water and isopropyl alcohol prior to placing it in a reactor or an evaporator.
Next in Figure 3 an intermediate layer 23 is -then deposited on the silicon dioxide layer 21, The layer 23 consists of at least one material selected ~rom the group consisting o~ silicon, and other metals which can withstand a high di~usion temperature without penetrating into the oxide such as refractory metals, ' ' . ~, ~ " ' '~ ' ' . , lOS83Z8 ~or example, molybdenum, tantalum and zirconium.
Generally, however, any metal that adhers to ~he oxide layer 21 may be used such as chromium, ~ere the layer

2~ is metal, the layer consists of metal crystals o~
substantially oriented pattern. I~here the layer 23, on the other hand is silicon, the structure is poly~
crystalline and the crystals are randomly disposed and include a p~ type dopant to improve the conduc-tivity. me pre~erred element ~or the layer 23 is silicon doped with p+ type impurities such as boron.
me layer 23 has a thickness in the range from about O O
~OOOA to 7000A. The layer 23 thus fabricated forms the gate electrode for at least one MOS transistor. Such a use of the polysilicon layer as the gate region with an etching away elsewhere as taught ln conventional silicon gate technology is set forth in an article entitled "Silicon Gate Technology" which appeared in the October, 1969 issue o~ Spectrum, a publication of the :
Institute of Electrical and Electronics Engineers, Inc.
The prior art teaches that when desirable, layer 23 can additionally act as a shield in non-gate areas, Further in Figure ~, an outer glass layer 25 is deposited over the en~ire upper surface of the inter-mediate polysilicon layer 2~, The glass layer 31 is composed of a suitable material such as a low temperature pyrolytic oxide and has a thickness of less than lo,OOOA
which is only slightly greater than the thlckness of the intermediate layer 2~. Pyrolytic oxide is silicon 43J14~
.

~0~i8328 dioxide produced by the chemical decomposition o~ a silicon compound such as SiH4 with oxygen in a rlOw system.
As shown in Figure 4, windows 27 and 29 are next opened suoh as by etching through layers 21, 23 and 25 in order to provldq for the subsequent diffusion ~or the formation of source and drain regions, The n~ reglons 17 and 19 are dif~used into the substrate 11, Suitable dopants for that purpose are phosphorus -and other elements of the Group IV o~ the periodic table. During the drive-in di~fusion, a thin layer of thermal oxide 31 is also grown as shown in Figure 5.
Thereafter as shown ln Figure 6, openings 33, ;
35 and 37 are provided such as by phot~etching with buffered hydrofluoric acid through the thermal oxide layer 31 and the glass layer 25' at the gate region :~ .
to provide access for 9ub9equently applied electrodes, The openings 33 and 37 extend through the n+ regions 17 and 18 in the substrate 11. The opening 35 extends through the glass layer Z5' to the p~ doped silicon :~
gate material 23, A thin layer of electrode material ls ne~t evaporated on the khermal oxide layer 31 and into the openings 33, 35 and 37, This layer i.s then selectively etched as shown in Figure 7 to provide electrical contacts or eiectrodes 39, 41, and 43 for the desired interconnection, The electrode material ~:
may be composed of a metal having a high coefficient of electrical conductivity such as aluminum, The elec-trode 39 leads to region 17 which may be designated as the source, The electrode 41 connects to the`polysilicon 1~3,144 ~ 58 ~ 8 layer 23 and serves as the gate electrode and finally the electrode 43 leads to the region 19 which serves as the drain in an n-channel MOS transistor, The present invention, moreover, provides a means ~or fabricating complementary enhancement mode MOS transistors with narrower p channel lengths for hlgher frequency operation. The embodiment o~ the subJect invention utilizes a p-doped substrate of sili con having a <100> orientation which serves as the background for n+channel transiskors and an n-type well diffused in the subætrate which serves as the background for p+ channel transistors, The substrate has a rela tively low doping concentration, whçreas the n-type well has a relatively higher doping concentration, By including a p+ d~ped silicon gate as previously set forth, an enhancement mode complemen~ary device which is structurally symmetrical is provided, Figure 8 discloses the preferred embodiment of such a device and is prsduced by the following steps:
1, Selective diffusion of an n - "well"
reglon;
2, Selective diffusion of spaced apart n +
source and drain regisns ad~acent the well region;

3, Growth o~ gate oxide;

4, Growth of p+ doped polycrystalline gate and where desirable shield;

5, Growth o~ glass;

6. Selective opening o~ diffusion windows ~-and diffusion o~ spaced apart p+ source and drain regions in the n - well region;

- 7 ~3, 144 lOS83Z8 7. Etching of polycrystalline ~llicon *or isolating the gate;

8, Opening of contact windows;

9, Evaporatlon of aluminum layer; and

10, Selective etching o~ aluminum, -Referring now to Figure 8~ in the first step of the selective dlffusion of the n - well region 12, it i9 a thermal diffusion process through a photographic mask of a suitable dopant such as phosphorus. In a simllar manner, the two spaced n+ regions 17 and 18 are diffu~ed in the wa~er as source and draln regions, Following this, the two spaced p+ region~ 16 and 18 are dl~fu~ed ~nto the well 12 a~ souroe and drain regions of opposit;e conductivity ~rom the source and drain regions 17 and 19. An in~ulatlng layer 21 of silicon dioxlde i~ then applied to the substrate 11 as descrlbed with respect to Figure 2, A layer 23 is then applied by a vapor deposi-blon on the silicon dioxide layer 21, The layer 23 is similar in composltlon and other parameters to the layer 23 shown in Flgure 3 and is preferably silicon.
Moreover~, the layer includes p~ type dopant such as boron when the`layer i8 polycrystalline silicon, Next the glass layer 25 is grown over the entire inter-mqdiate layer and ~uitable opening~ provided therein for electrode material, The gate regions are isolated by a photoetching operation using a suitable etchant ~uch as a mixtu~e of 5:1:1 parts by volume of nitric acidJ acidic acid and hydrofluoric acld, A layer of metal consisting of at least one metal selected ~rom ~ . . .

43,144 ~583Z~3 the group consisting of aluminum and gold is evaporated like the layer applied in Figure 7. By a subsequent etchlng procedure, several parts shswn in Figure 8 are provided, including contact and interconnection members 3~, 41, 42, 43, and 44 and a cross-over 45, The use of a pf doped gate for both n+ channel and p+ channel metal oxide semiconductor transistors fabricated on a <lO0~ oriented crystal is based on work ~unction considerations. As shown by the graph illustrated in Figure 9, when a silicon gate is doped with p+ type impurities, the work function is increased shifting the flat-band voltage toward the posit~e, The e~fect o~ this shlft is reflected ln the threshold voltages of both p~ and n~ channel transistors for <100 crystals, For the p~ channel transistors, the p+ doped gate makes the device a depletion mode on lightly doped background but an enhancement mode device on a moder-ately or heavily doped background. Thus a relatively greater doping concentration of the well 12, e,g, ~ x 1016 atam/cm3 which is illustrated by reference numeral 50 of Figure 9 will result in an enhancement mode device. For the n~ channel transistors, the p+
doped gate increases the threshold and requires a lightly doped background for low threshold voltage~. Accordingly, the substrate ll then requires a relatively lighter impurity concentration, e.g. 1 x 1015 atoms/cm3 such as shown by reference numeral 52 shown in ~igure 9 with resulting enhancement mode devices.
Thus it can be seen that for low threshold voltages, a positive threshold voltage for the n+ channel 43,144 :
1~583Z~3 ~
~ . :. ....
transistor and the negati~e threshold voltage for the p+ channel transistors indicate that both transistors are enhancement mode devices when the n~ channel tran- -sistor is fabricated on a low impurity concentration substrate but whereas the p+ channel transistor is fabrlcated in the more heavily doped n- type well.
Ac~ord~ngly, the device of the present inventian re-qulres no addltional reverse blas as ls generally in-conveniently required. This advantage can be taken for both slngle channel or complementary MOS structures.
In summation then, the use of a p~ doped gate for both the n+ channel and p+ channel metal oxide semlconductor tran9istors fabricated on <lOO> oriented crystals is based upon work funcbion considerations.
When a silicon gate is doped with p+ type impurlties, the work function is increased such that with a rela-tlvely lesser doped substrate and a relatively greater doped well, devices having lower threshold voltages than aluminum gate devices can be realized.
Having described what is at present considered to be khe preferred embodiment of the sub~ect invention, . . .

Claims (8)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A complementary enhancement mode MOS transistor structure having p doped silicon gates, comprising in combination:
a substrate of p type semiconductive material having a relatively light doping concentration;
a region of n type of conductivity, having a relatively heavy doping concentration, disposed within the substrate;
a first pair of spaced-apart regions comprised of p type conductivity disposed in said n type conductivity region;
a second pair of spaced-apart regions comprised of n type conductivity disposed in said substrate and respectively spaced from said first recited region of n type conductivity;
all of said regions having surfaces in one surface of said substrate;
an insulating layer of silicon dioxide on said one surface of the substrate;
an intermediate layer doped with p type con-ductivity materials;
a layer of glass formed on said intermediate layer;
walls forming aligned openings fabricated in said insulating, said intermediate and said glass layers to said first and second pairs of spaced-apart regions, a thermal oxide layer lining said openings and the outer surface of said glass layer;
selected openings formed in said thermal oxide layer and said outer layer of glass to the surface of said intermediate layer and in said thermal oxide layer to the surface of said pairs of spaced-apart regions; and respective electrodes extending through said selected openings and electrically connected to the surfaces of the intermediate layer and said spaced-apart regions.

2. The structure of claim 1 wherein the substrate consists of silicon having a p-type dopant, said first recited region of n type conductivity within the substrate has an n-type dopant, the first pair of spaced-apart regions has a p+ type dopant, and said second pair of spaced-apart regions has an n+ type dopant, and said intermediate layer has a p+ type dopant.

3. The structure of claim 2 wherein the substrate is comprised of a <100> oriented crystal of silicon.

4, The structure of claim 2 wherein the insulating layer is of SiO2 has a thickness of from 800 to 1600.ANG..

5. The structure of claim 2 wherein the intermediate layer has a thickness of from 3000 to 7000.ANG..

6. The structure of claim 2 wherein the intermediate lager is doped with a metal selected from Group III elements of the periodic table.

7. The structure as defined by claim 6 wherein the selected metal comprises boron.

8. The structure of claim 2 and additionally including an interconnection between one of the electrodes connected to said first pair of spaced-apart regions and the nearer electrode of the electrodes connected to said second pair of spaced-apart electrodes.

(9.) A complementary pair of field effect transistor devices formed in a semiconductor substrate and including polycrystalline silicon as the gate electrodes thereof, wherein said gate electrodes are doped with a P-type impurity.

(10.) In the method for forming a complementary pair of field effect transistors which include a semiconductor substrate having regions therein for N- and P-channel devices and silicon gate electrodes for said devices, the improvement comprising:
doping both said gate electrodes with a P-type impurity.