CA1057388A - Method and apparatus for the ultrasonic measurement of the flow veiocity of fluent media - Google Patents
Method and apparatus for the ultrasonic measurement of the flow veiocity of fluent mediaInfo
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- CA1057388A CA1057388A CA257,785A CA257785A CA1057388A CA 1057388 A CA1057388 A CA 1057388A CA 257785 A CA257785 A CA 257785A CA 1057388 A CA1057388 A CA 1057388A
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Abstract
ABSTRACT OF THE DISCLOSURE
Ultrasonic signals are transmitted alternately upstream and downstream in a fluent media. A reference signal timed to occur at the estimated time of arrival of the alternate signals is used to ascertain whether the actual signals arrive earlier or later than the reference signal.
Control circuitry responsive to the early and late signal generates two signal levels associated with transmission direction which adjusts the time position of the reference signal until it coincides with the actual arrival times. One signal level is related to flow velocity. The other signal level is related to sound velocity in the fluent media.
Ultrasonic signals are transmitted alternately upstream and downstream in a fluent media. A reference signal timed to occur at the estimated time of arrival of the alternate signals is used to ascertain whether the actual signals arrive earlier or later than the reference signal.
Control circuitry responsive to the early and late signal generates two signal levels associated with transmission direction which adjusts the time position of the reference signal until it coincides with the actual arrival times. One signal level is related to flow velocity. The other signal level is related to sound velocity in the fluent media.
Description
` ~5~3~8 ~:
BACKG~OUND OF THE INVENTION
This invention relates to ultrasonic flowmeters and, more partlcularly, to method and apparatus for the ultrasonic measurement of the flow velocity of fluent media.
An ultrasonic measuring apparatus is known from U.S. patent 3 818 757, which issued June 18, 1974 to A.E. Brown, ln which frequencies are generated which are a frequency fl on `
~ downstream measurement related to the downstream speed o~ sound ; and a frequency f2 on upstream measurement related to the up-stream speed of sound. From the instant Or transmitting the ultrasonic signal, a predetermined number, for cxample 256, of output pulse~ of the oscillator are counted, whercupon a refer-cnce signal is transmitted. If it is found in a comparator that the ultrasonic signal recelved occur~ earlier than the reference ~ignal, the frequency of the oscillator is ln-creased by means of a slgnal level generator in the form of an integrator, so that the tlming of the reference signal i8 adJusted to the actual arrival time of the ultrasonlc slgnal. If the ultrasonlc signal received occurs later than the reference signal, the frequency of the oscillator is re- -duced. The frequencies fl and f2 thus determined alternately are passed to a respectlve evaluatlng eircuit, stored there until the arrival of the other frequency, and then processed to measuring data corresponding to the flow velocity or ~onic velocity, respectively.
An apparatus of the kind referred to is known from U.S. patent 3 780 57* whlch issued December 25, 1973 to A.E. Brown wherein a signal level generator is providcd for both transmission directions, lt being possible to transmit the early or late signals to the inputs of the signal level generator only lf the associated .- ~
, ::
logic elements simultaneously contain an upstream or a downstream signal, respectively. In this case, the signal .
level is also available in the respective other transmission direction during the measurement. By way of summation and sub~equent lntegration of the signal level) one receives a voltage for controlling an oscillator of which the output frequency is selected as a measurement for the sonic velocity.
The flow velocity is obtained by producing trapezoidal waves from the two signal levels. These trapezoidal waves are 10 generated in a certain relationship to each other by means of s~itches, a quick-acting integrators and comparators. In addition, the output frequency of the oscillator is stepped down to one quarter and modulated by the trapezoidal waves to produce the frequencies fl and f2. The reference signal occurs after each 256 impulsès of the frequencies fl or f2.
Extraordlnarily high requirements are placed on the accuracy of operation of these apparati because the transmisQion time differences are only 10 8 or 10 9 seconds for most applications. To achieve this accuracy, known apparati call 20 for a considerable expenditure. Thi8 refers toJ inter alia, certain circuit configurations, operational ampli~iers of high quality and precision components. This tend~ to make the apparatus expensive.
`~ The underlying ob~ect of the invention is to provide an ultrasonic measuring apparatus of the aforementioned kind having the desired measuring accuracy or even a greater ;` measuring accuracy, parti~ularly for the ~low velocity, and . .
x which can be ~ade considerably more cheaply as a result o~
using a simple circuit construction and normal compone~ts.
.
, , ~057388 '~
SUMMARY OF THE INVENTION
In a preferred embodiment, the apparatus includes at least one measuring path which is provided wlth two ultrà~onic transducers, each of which have at least one component extendlng ln the direction of flow and through which ultrasonic signals are transmitted alternately upstream and downstream, comparator means on the receiving side for re-celving on the one hand arrival signals associated with the time of receiving the ultrasonic signals and on the other ; 10 hand reference signals delayed with respect to the transmlssion ! ~ time and for dellvering early and late signals when the arrival ~ignal~ arrive earlier or later than each reference signal, respectively; a control circuit whlch, in logic elements, links to the early and late signals upstream and downstream signals occurring ln dependence on the transmisslon directlon and which contains at least two signal level generators con-trolled ln relatlon thereto so as to produce two control ~lgnals associated with the transmission direction; and at -least one timing generator controlled by the control signals 20 for providing the reference signal.
In such apparatus, the transit time of an ultrasonlc slgnal transmitted downstream along the measuring path ls compared with the translt time of an ultrasonic slgnal trans-mitted upstream along the measuring path. The flow velocity of the medium is then proportional to the difference between, and the sonic velocity in the flowing medium ls proportional to the sum of, the reciprocals of the transit time. In one embodiment the tranæit time is measured by counting a predetermined number of oscillations generated with a vari-30 able frequency oscillator, the flow velocity is proportional : - 4 -i ~357388 to the difference between, and the sonic velocity is propor-tional to the sum of, two frequencies fl and f2 associated with the downstream measurement and upstream measurement, resE~ectively.
The output of the first æignal level generator and the output of the second signal level generator are respectively applied as main signal and auxiliary signal to an adder or summing circuit in which for at least one control signal the auxiliary signal is added to and/or subtracted from 10 the main slgnal. A switch controlled by the transmission direction is provlded by which two different delay periods are alternately made effective for the reference signal.
I~ only one time generator, e.g. an oscillator with series-connected counter ls provided, the swltch may be ln the input for the auxlll~ry slgnal to the summating clrcuit. t Th18 time generator ls therefore alternately fed with an upstream control signal and a downstream control signal, so that the delayed reference 8i~ can be adapted to the arrival time of the ultrasonic signal on upstream measurement 20 or downstream measurement, respectively.
When using two time generators, the switch may be connected after at least a first section of these time generators. When using oscillators with a series-connected common counter, this switch can for example be disposed between the oscillators and the counter.
In such a construction o~ the apparatus, the auxil-iary signal is a direct measure of the flow velocity. This auxiliary signal is effective in at least one of the two regulating circuits that are f~rmed during the upstream 3 measurement or downstream measurement. In these regulating , .:
circuits, the time of occurrence Or the delayed reference signal is adjusted with high accuracy to the arrival time of the received ultrasonic signal. Even if inaccuracies occur within these regulatlng circuits as a result of slmple circuit groups, cheaper components or the llke, they are compensated by the function of the regulating circuit. -Consequently the auxillary signal and thus the measured e flow veloc~ty also have the desired accuracy independently of the quality of the components that are used.
: .
To increase the accuracy, the auxil$ary signal may -be proportionally reducible at the input of or in the summating .. i: -. .
clrcult. The auxillary signal is therefore transmissible by the second signal level generator with a higher proportionality , factor than the maln signal from the first signal level r~ generator. The second signal level generator therefore operates with a comparatively high output level. ~hl~ is po~sible because the main signal and the auxiliary signal are produced separately and fed to the summating circuit through separate paths which could have different loop gains.
In one embodiment, the one control ~ignal i8 formed by the maln signal and the other control slgnal by the sum of or difference between the main signal and the auxiliary signal. If the transit time ls measured by ~requency ~orma-' tion, the main signal corresponds to the frequency fl or *
and the auxiliary signal to the difference between these frequencies so that the control signal alternately corresponds to fl or f2. This can be achieved with a circuit ln which ~ the first signal level generator comprises an integrator ~or ij receiving early signals of one sign and late signals of the opposite sign at its input associated with one of the ~, ., ., :`
- ~, . - .
~0~73~
transmission directions, and in which the second ~ignal level generator comprises an integrator for receiving early slgnalæ of one sign and late signals of the opposite sign at ltæ output associated with the other transmission direction.
In a preferred second embodlment, the one control signal ls formed by the sum of and the other control signal by the difference ~etween the maln signal and the auxiliary BiBnal. Thi8 iS because the main signal is a direct measure-ment for the ~onic velocity in the flow. One can therefore derive both measuring values of principal interest directly from the regulating circuits and with high accuracy. With a tlme measurement on a frequency basis, the main signal corresponds to the mean value of the frequencies fl and f2 and the auxiliary signal to half the difference between these two frequencles.
In a clrcuit that is particularly suitable in this connectionJ the first signal level generator comprises an lntegrator for receiving at its input all early signals of both transmission directions of one sign and all late signals of both transmission directions of the opposite sign, and the second signal level generator comprises an integrator for re-ceiving at its input the early signals or late ~ignals of both transmission directions, the signals of one transmission direction having one sign and the signals of the other trans-mission direction having the opposite sign. In thls construc-tion signals from the upætream measurement as well as the down-stream measurement are evaluated in both signal level generators.
Since all ~arly and late signals of both trans-mission directions are utilized to obtain the maln signal, a very accurate main signal is obtained as a result of the high . . .
~057388 information content. All the early and late signals of both transmlssion directions can also be utilized for the auxili-ary signal, This is achieved for example in that the second slgnal level generator comprises a main integrator and an additional integrator, the additional integrator processing the signals not processed by the main integrator in the same way as the main integrator and the output of the additional integrator being connected to one input of the ma~n integrator.
A simple circuitry is achieved if the second signal level generator comprises a correcting element through which the early signals and the late signals of the one transmission dlrection have the early signals and the late signals of the i other transmission direction added to them before they are fed to the integrator.
In a preferred embodiment, it is insured that the control circuit i8 provided with a ~irst row of two logic elements of which the outputs are occupled in dependence on the presence of the arrival signal and one early or late signal and connected on the one hand to the input circuit of the first integrator of the flrst signal level generator and on the other hand to the input of a second row of four logic elements which can additionally be fed with upstream or down-stream signals in such a way that their outputs are associated with the early signals of the one transmission direction, the early signals of the other transmission direction, the late signals of the one transmission direction or the late signals of the other transmission direction. Two or four of the last-mentioned outputs then serve to feed the second signal level generator.
To the output of the second signal level generator ~573~8 ; there may be applied the input of an amplifier of which the output is connected through two incandescent diodes of i opposite polarity disposed in parallel branches to a voltage reference polnt such as earth, one of the diodes possibly being in series with a Zener diode. This produces indicator means for indicating the measured flow direction by lighting up of one of the two incandescent diodes.
Further, the output of the first signal level generator may have applied to it through a full wave voltage limiter the input of an amplifier of which the output is connected through two parallel incandescent diodes of opposite polarity to a voltage reference point such as earth. In this case one of the incandescent diodes lights up when the sonic velocity exceeds the upper or lower limits of a permissible range.
~ ccording to the method of this invention, fluid flow rate and sound propagation velocity through a fluid are ; measured using upstream and downstream transducers by generat-ing a transmit pulse, generating a reference pulse delayed in time to said transmit pulse, directing the transmit pulses alternately upstream and downstream of the flowing medium, ; receiving the transmitted pulses, comparing the phase of the received and reference pulses, generating logic signals in accordance with the early and late arrival of said received pulses relat~ve to said reference pulses, obtaining the statistical average of all early and all late signals to provide a first signal level related to the sound speed in said medium, generating logic signals corresponding to the early and late arrival of signals relative to said reference signals correlated with the direction of transmission, _ g _ , obtaining the statistical average of at least one pair of --early and late arrival signals to provide a second signal level related to fluid flow velocity of sald medium, selectively subtracting and adding said first and second signQl level for each of said upstream and downstream trans-missions thereby to vary the delay time of said reference pulses for each of said upstream and downstream transmissions such that sald reference pulses track the actual time of arrival of said transmitted pulses.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in more detail wlth reference to examples shown in the drawing, wherein:
Figure 1 is a diagrammatic circuit lay out of a measuring apparatus according to the invention;
Flgure 2 ls a modl~ication of part of the circuit;
Flgure 3 ls a further modlflcation of the clrcuit;
Fi~ure 4 ls an embodiment of the control circuit;
Figure 5 ls a modification of part of the control circuit;
Figure 6 i~ part of the circuit containing the summating element and the switch;
Figure 7 shows the control circuit, switch and ~.
summating circuit for the FIa. 2 embodiment;
Figure 8 is an alternative embodiment of part of the circuit of FIG. 1 uæing an analog time base;
Figure 9 is an indicating circuit for deviatlons in the sonic velocity;
Figure 10 is a circuit for indicating the flow direction; and Figure 11 is a table of the corrections accurring _ 10 --.
~0573~8 in the FIGS. 1, 3 to 5 or 6 embodiments with the various combinations of upstream and downstream, early and late B ignals.
According to FIG. 1, a channel 1 contains an ultra-sonlc measurlng path 2 which is defined by two ultrasonic transducers 3 and 4 and is disposed obliquely to the direction -~
5 of flow of the fluent medium through the channel 1. One transmission device 6 i8 able to pass to the transducer 3 through the line 7 a D. C. impulse S7, which shock excites the transaucer at its resonant frequency so that lt thereupon passes through the medium in the channel 1 an ultrasonic 8 ignal having a frequency of for example 1 MHz. This signal is received by the transducer 4 at the end of the transit time and converted to an electric signal S8 which is fed through a line 8 to receiver means 9. The lines 7 and 8 are interchange-able through a switch 10 so that the transducers 3 and 4 can serve alternately as ultrasonic transmitter and as ultrasonic receiver. Alternatively separate transmitters and receivers may be employed as described in U.S. Patent 3,780,577. In the receiving means 9, a defined arrival signal Sll is obtained from the high frequency signal S8 by means of a zero cross-over detector such as that described in U.S. Patent 3,780,577;
the signal Sll being passed through a line 11 to comparator means 12. These comparator means slmultaneously receive through a line 13 a reference signal S13 with which the arrival signal Sll is compared on a time ~asis.
A voltage-controlled oscillator 14 may serve as time generator; it passes its output oscillations as an impulse chain S15 to a counter 16 through a line 15. On commencement of counting, this counter delivers a transmission signal S17 ~057388 , . .
- to the transmission means 6 through a line 17. At a pre-determined counter content, e.g. 256 impulses, the reference signal S13 is delivered. At an earlier instant (be~ore ~-256 impulses), e.g. 128 impulses, a receiver readiness ;; signal S18 was passed through a line 18 to prepare the ' comparator means ~or measurement. Subsequent to measurement, e.g. 384 impulses, the receiver readiness signal S18 is terminated, thereby disabling the receiver and comparator and protecting against shock excitation during transmission. -Finally a signal Sl9 is fed through a line 19 to a bistable transmission generator 20 which alternately delivers down-stream signals S21 and upstream signals S22 through a pair of signal lines 21 and 22, the latter signals then switching the switch 10 over.
When an arrival signal Sll arrives in the comparator means 12, a signal of predetermlned, constant amplitude and duration appears at the output 23. If thls arrival signal Sll haA arrived earller than the reference signal S13, a signal appears at the output 24. If the arrival signal was determined later than the reference signal, a signal occurs at the out-put 25. A flrst row 26 of logic elements links these three output signals in such a way that in a line 27 an early signal S27 occurs having a constant amplitude and the same time duration as the signal occuring at output 23 and a late signal S28 occurs also having a constant amplitude and the - same time duration as the signals occurring on outputs 23 and 25.
In an integrating signal level such as a generator integrator 29 all early signals S27 are integrated in one direction and all late signals S28 in the opposite. By way - 12 _ ~L~57388 of convention, the + and - signs in the blocks 29 and 38 indicate the direction of integration of early signals S27 ; and late signals S28 which in the embodiments both have posLtive ~oing polarity. For instance, the early signals could be fed to the non-inverting input and the late signals to the inverting input of an operational amplifier serving as an integrator. At the output 30 of the integrator, a main ; signal S30 occurs in the form of a signal level that is variable by the early and late signals. This main signal S30 can be derived directly at an output terminal 31 through an evaluating circuit such as a meter and used as a measure-ment for the sonic velocity c of a medium flowing through the channel 1. In addition, this main signal S30 is passed to an input of a summing circuit such as an adder 32.
The early and late 8 ignals S27 and S28 are addi-tionally fed to a second row 33 of logic elements~ which also have fed to them the downstream and upstream signals S21 and S22. In this way early upstream signals S34, early downstream signals S35, late upstream signals S36 and late downstream signals S37 are obtained at four outputs 34 to 37. A second integrating signal level generator such as an integrator 38 ; is fed with the early downstream signals S35 with positive sign and the early upstream signals S34 with negative sign and possibly also the late downstream signals S37 with negative sign and the late upstream signals S36 with positive sign.
As a result, an auxiliary signal S39 is produced at the out-put 39 in the form of a signal level dependent on the signals S34 to S37.
This auxiliary signal S39 is fed directly to an output terminal 40 from which the flow velocity v of the medium flowing in the channel 1 can be taken directly through `:``
~L~57388 an evaluating circuit. In addition, the auxiliary signalS39 is fed through a switch 41 alternately to the positlve and the negative second input of the summating circuit or adder 32. The switch 41 which ma~ be an analog switch is operated by the downstream and upstream signals S21 and S22.
Control 8 ignals S43 and S44 therefore alternately occur at -the output 42 of the adder, these signals corresponding to the sum of or difference between, respectively, the main signal S30 and the auxiliary signal S39. These control signals S43 and S44 control the voltage-controlled oscillator 14 in such a way that the pulse train S15 alternately has a higher frequency fl associated with the downstream measure-ment and a lower frequency f2 associated with the upstream measurement.
This results in the method of operation to be described hereinafter in con~unction with FIG. 11. Entered in the flve rows 1 - 5 on a time reference there are the transmission signal S17, the arrival signal Sll occurring after the transit time tl, and the reference signal S13 occurring after a delay period tv which may be greater than or less than tl for the downstream measurement as well as for the upstream measurement. There is also an indication as to whether the main signal S30, the auxiliary signal S39 and the control sienals S43 and S44 are increasing, decreasing or remaining unchange*.
Case 1: It is assumed that all arrival signals Sll occur earler than the reference signal S13. The result of this is that the level integrator 29 merely receives posit$ve signals and the main signal S30 increases. On the other hand, positive and negative signals are alternately fed to the 1~57388 second integrator 38 so that the auxiliary signal S39 remains unchanged. Consequently both control signals S43 and S44 in-crease. The frequencies fl and f2 of the pulse trains from the VC0 14 lncrease. The delay period tv is therefore de-creased in both transmission directions because the 256 lmpulses were on each occasion counted in a shorter period of time by the counter 16. During the respective next up-stream or downstream measurement, therefore, the delay period tv has been more closely adapted to the actual transit time tl. Since this procedure is repeated for each measurement, there is ultimate coincidence between the delay period and the transit time or, stated in other words, the frequencies fl and f2 are a measure of or are proportional to the actual transit time tl.
Case 2: All arrlval signals Sll occur later than the associated reference slgnals S13. Exactly the opposite conditions to those ln Case 1 occur. The main slgnal S30 decreases. The auxiliary signal S39 remains unchanged. m e control slgnals S43 and S44 both become smaller. The fre-, 20 quencies ~1 and ~2 both decrease.
Case 3: During the downstream measurement the arrival signal Sll occurs earlier than the reference slgnal S13 and during the upstream measurement lt occurs later. In this case the integrator 2g is alternately supplied wlth positive and negative signals so that the main slgnal S30 re-mains unchanged. on the other hand the second integrator 38 is only supplied with positive signals. Consequently the auxiliary signal S39 increases. As a result the control signal S43 and thus the frequency fl increase but the control 3~ signal S44 and thus the frequency f2 decrease.
1~573~38 Case 4: The arrival signals Sll occur later than the reference signals S13 dur~ng the downstream measurement but earlier during the upstream measurement. The circum-stance~ are the reverse Or those in Case 3. m is means that the frequency fl drops and the frequency ~2 rlses.
Case 5: All arrival signals Sll coincide with the reference signals S13. m e signal level generators 29 and 38 receive no signal. The main signal S30 and auXlliary signal S39 remaln unchanged, as do the frequencies fl and f2.
This is an ideal condition which in practice almost never occurs.
The clrcuit therefore forms a regulating clrcuit in which solely by the statistical evaluation of the early and late signals during the upstream and downstream measurement an ad~ustment of the delay period tv occurs in such a way that the latter accurately coincides wlth the translt time t after a few lndividual measuremcnts. mis regulation takes place with a relativcly high accuracy independently of the quality of the components provided in the regulating circuit.
When the frequencies fl and f2 occur by summstion and subtraction Or the main signal S30 and auxiliary signal S39, a ~imple calculatlon will show that the maln signal S30 is a relatively accurate measure of or proportional to the mean value (fl + f2)/2 and the auxlliary signal S39 is a relatively accurate measure of or proportional to half the difference (fl - f2)/2 of the two frequencies fl and f2. How-ever, since this mean value is proportional to the sonlc velocity of the medium flowing in the channel 1 and the difference is proportional to the flow velocity of thls medium, one can connect output terminals 31 and 40 directly ~57388 to the outputs 30 and 39 to derive signals corresponding to the sonlc velocity c and flow velocity v, respectively.
These signals may have an extraordinarily high accuracy be-, cause they can be derived directly from the self-compensating reeulatlng clrcuit.
Instead of the time generator conslstlngOf the oscillator 14 and counter 16, one can also use an analog time generator such as is illustrated in FIG. 8 and described here-inafter.
lû FIG. 2 shows a modification of the solution accord-ing to FIG. 1, in which the signals S34 to S37 feed two 8 ignal level generators or integrators 43 and 44 ln such a way that the integrator 43 is fed with the early upsteam sig-nal S34 of positive sign and the late upstream signal with negative sign and the integrator 44 is fed with the early downstream signal S35 with positlve sign and the late downstream signal S37 with negative sign. At the output 45 ~-of the integrator 44 a main signal S45 occurs which is applied 1O the one input of the summating clrcult 32. At the output S~ 20 46 of the integrator 43 there occurs an auxiliary signal S46 whlch can be applied to the other input of the summating ~ circuit 32 through a switch 47 that is again controlled by ; the signal direction generator 20. The output terminal 40 -from which a quantlty corresponding to the flow velocity v is derivable ls connected to the output 46 of the integrator 43.
Let one assume that the switch 47 is open during the downstream measurement. The control signal S43 then corresponds to the main signal S45 during the open period. The latter changes in dependence on whether the volatage si gnal integrator 44 is fed with early downstream signals or late downstream ~357388 signals. If only the integrator 44 is included in the re-gulating circult, the main signal S45 therefore corresponds to the frequency fl for the downstream measurement.
If during the upstream measurement the swltch 47 is closed, the auxlliary signal S46 is added to the main signal S45. The auxiliary signal changes in dependence on whether the integrator receives early upstream signals or late up-stream signals. Since during this measurement the control signal S44 is set to a value corresponding to the frequency f2, the auxiliary signal S46 must correspond to the di~ference fl ~ f2. A signal proportional to the flow velocity v can , therefore again be obtained in this way with high accuracy.
' In the embodiment according to FIG. 3 there is shown another modification of the circuit according to FIG. 1.
Here the maln slgnal S30 and the auxiliary signal S39 are fed to two summating circuits 48 and 49 in such a way that the control signal S43 is constantly produced by the sum and the control signal S44 by the difference. The voltage-controlled oscillators 50 and 51 are supplied with these control signals and constantly deliver impulses S52 of the frequency fl or impulses S53 of the frequency f2, respectively. A switch 54 controlled by the signal direction generator 20 applies these impulse chains alternately to a common counter 55 corresponding to the counter 16.
FIG. 4 shows an example of the FIG. 1 control circuit in more detail, in which instead of the reference numerals for the line~ there are in some cases only the reference numerals for the slgnals occurrlng therein. The first row 26 of logic elements~onsists of two AND elements 56 and 57 and the second row 33 of logic elements of four AND elements 58 ~C~57388 to 61. The signal level generator 29 comprises an amplifier 62 having all late signals S28 fed to its non-inverting input and all early signals S27 to its inverting input. This ;~; amplifier is followed by an integration amplifier 63 from the output of which the main signal S30 is derivable. The signal level generator 38 comprises an amplifier 64 having the early upstream signals S34 applied to its non-inverting input and the early downstream signals to its inverting input. A
- correcting circuit 65 permits the inverting input of the amplifier 64 also to be fed with the late upstream signals S36 and the non-inverting input with the late downstream signals S37. The amplifier 64 is followed by an integration amplifier 66 from the output of which the auxiliary signal S39 ~, is derivable.
,' In the embodiment according to FIG. 5 the early j upstream signals S34 are fed to the non-inverting input of the amplifier 64 and the early downstream signals to the -inverting input of this amplifier. The output of the ampli~
fier is again connected to the inverting input of the inte-gration amplifier 66. The late upstream signals S36 are fed to the inverting input of a further amplifier 67 and the late downstream signals S37 to the non-inverting input of this amplifier. The amplifier output feeds an integration ampli-fier 68 of which the output is fed to the non-inverting input of the integration amplifier 66. Here, too, the auxiliary signal S39 can be derived from the output of the integration amplifier 66.
FIG. 6 shows an embodiment of the summing circuit 32 together with the switch 41 according to FIG. 1. The su~mating circuit 32 comprises a first resistance 69 through 573~38 . .:
which the main signal S30 is fed~ a second resistance 70 through which the processed main signal S39 is fed, and a summing bias resistor 71. The summation signal is amplified !~, in an amplifier 72. The amplifier output is applied through ~r a potentiometer 73 to a voltage of +12V, so that the control t~ signals S43, S44 which can be tapped at the potentiometer 73 r:
~, can receive an additional setting for fixing the operating ,..~
,, range.
The switch 41 consists of two electronic switch ' 10 elements 74 and 75 which are made alternately operative by the d~wnstream signals S 2 1 and the upBtream s~gn~ls S22. The auxiliary signal S39 is consequently alternately fed to the inverting an the non-inverting input of an ampli~ier 76, , whilst the re8pective other input of the amplifier 76 is ,s supplied wlth a ~ixed voltage tapped from a voltage divider ~ 77 and 77~. m e ~witched signals S39 is biased by the re-¦ sistor 77' to the same voltage level as the fixed voltage.
The unnumbered blocks in the figures represent various gain setting resistors.
FIG. 7 shows details of the circuit according to FIG. 2, the components to some extent corresponding to those of FIGS. 4 and 7. The first row 26 of logic elements is pro-vided with NAND-elements 56l and 57', the second row 33 is provided with NOR-elements 58', 59', 60' and 61'.
;, The signals S34 to S37 derivable from the second row 33 of logic elements 58' to 61' are here evaluated as follows. The early upstream signals S34 are fed to the in-; verting input of an amplifier 78 and the late upstream signals , S36 to the non-inverting input of this amplifier. The ampli-fier 78 output feeds an integration amplifier 79 from the ~0~7388 output of which the auxiliar~ signal S46 is derivable. The early downstream signals S35 are fed to the inverting input of a~n amplifier 80 and the late downstream signals S37 to the non-invertlng input of this amplifier. The amplifier output feeds an integration amplifier 81 from the output of which -~
the maln signal S45 is tapped. Main signal S45 is passed through a unity gain inverting amplifier 72l to summing cir-cuit 32 for logic purposes. During each upstream measurement, the auxiliary signal s46 is transformed through the amplifier lo 76 and tapped at a potentiometer 82. The control signal S43 therefore corresponds to the main signal S45 or the frequency fl and the control signal S44 to the difference between the main signal S45 and auxiliary signal S46 or the frequency f2.
With the aid of the amplifier 76 in FIGS. 6 and 7 : .
or the voltage divlder 82 in FIG. 7, the auxiliary signal S39 or S46, respectively, can be proportionally reduced by the value occurring at the output of the respective voltage level generator 38 (FIG.l) or 43. This means that at the outputs 39 or 46 of this voltage level generator there occur auxiliary signals which are sharply increased as compared with the values of the main signals S30 or S45, thereby providing larger amplitude signals at the output terminal 40 which in-creases the acouracy of the readout.
For the calibration of the apparatus, switch 83 may be used to apply a k~own constant voltage level to the invert-ing input of amplifier 76. The oDnstant voltage level is provided by a resistor 84 and a zener diode 85. This voltage level simulates a definable value for the auxiliary signal S46 corresponding to a definable flow veloclty. To effect this calibration, first the potentiometer 73 is adjusted until the output levels S43,S44 correspond to the mean sound velocity. Next the sw~ff tch 83 is switched to apply the known voltage and the potentiometer 82 is adjusted. For example, the signal S15 (FIG. 1) can be fed to a measuring device and the potentlometer 82 can be adjusted until the period of the VC0 will have a value corresponding to the defined flow velocity plus mean sound speed. ;
In Figure 8 another circuit is shown according to -.. . .
which the reference signal S13, the transmission signal S17, the receiver readiness signal S18 as well as the downstream signal S21 and the upstream signal S22 of FIG. 1 are produced ,- by the main signal S30 and the auxiliary signal S39.
The auxiliary signal S39 is inverted in an inverting i,f amplifier 86 having the ampllfication factor of one. The ; non-lnverted and the inverted auxiliary signal S39 is fed alternatlvely to the summing circult 32 by means of the ; switch 41 which i8 constructed as an analog switch being controlled from the downstream and upstream signals S21 or S22J respectively. A potentiometer 87 serves to set the magnitude of the auxiliary signal S39 to be entered into the summing circuit 32. The main signal S30 is fed through re-sistor 88, the auxiliary signal S39 is fed through a resistor 89. A zener diode 90 in connection with resistances 91 and 92 serves to produce a summ1ff ng bias voltage.
The timing generator 14 includes an analog time base in the present exa~ple. For such purpose, the control ~- signals S43 and S44 from the summing circuit 32 were fed to an integrator 93 at the output line 94 of which a gradually increasing signal S94 appears, therefore, until switching back takes place which is described later. Said signal S94 is fed to the non-inverting input of four comparators 95 - 98.
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The inverting inputs of said comparators are connected to a voltage divider which is formed by the resistors 99 - 102 and a Zener diode 103. Therefore, the comparators deliver a corresponding output signal S95, S96, S97 and S98 at di~ferent lnstants depending upon when the rising signal S94 ;~ reaches the bias voltage of each.
m ese output signals S95 - S98 actuate three D-fllpflops 104, 105 and 106 as well as a monostable multi-vibrator 107. The signal S96 is fed to the C-input of flip-flop 106. Therefore, the receiver readiness signal S18 appears at the Q-output. Sometime later the signal S97 which could be used directly as reference signal S13, appears at comparator 97. Again some time later signal S98 appears which is applied to one input of an AND~element 108 the other inhibit input of which is connected to a polnt of reference potential. The monostable multlvibrator 107, which is triggered by the appearance of signal S98, therefore produces at its output Q a signal S109 which is applied to the C-input of flipflop 104 which therefore effects a switching from downstream signal S21 to upstream signal S22 or vice versa.
At the end of a predetermined delay time a signal SllO appears at the ~-output of the monostable multivibrator 107, which is applied on the one hand to the R-input of flipflop 106 and therefore finishes the receiver readiness signal S18 and on the other hand to the C-input of flipflop 105. This provides a signal Slll at the Q-output which is applied through a diode 112 and a resistor 113 to the input of the integrator 93.
Said signal has such polarity that the output signal S94 de-creases quickly to zero. As soon as the comparator 95 detects that zero level is reached, signal S95 is applied to the R-input ~S7388 of fliprlop 105 to reset the flipflop. Startlng from this moment, integrator 93 is fed again by one of the signals S43 or S44, respectively,andat the Q-output of flipflop 105 the transmisslon sienal S17 appears. Now a new cycle starts.
Flgure 9 shows an indicator apparatus with two back to back lncandescent dlodes 114 and 115 which are connected from the output Or an amplifier 116 to ground. The one ampllfier input is connected to the connecting terminal 31 for the sonic velocity c through a bipolar voltage reference diode in the form of the series circuit of Zener diodes 117 and 118 of oppoæite polarity. As soon as the voltage at the output terminal 31e~ceeds the blocking voltage in the one or other direction, one or other incandescent diode lights up depend-ing on the voltage directlon so as to indicate that the set operating range of the apparatus i~ exceeded. The permissible ~i operatlng range can then for example be reset bg ad~u~ting the potentiometer 73.
Figure 10 relates to an indicating apparatus for the ilow direction. Connected to the output terminal 40 for the flow velocity v there i8 the one input of an amplifier 119 of which the output i8 applied to earth through the æeries clrcuit Or an incandescent diode 120 and a zener dlode 121 both in shunt with an incandescent diode 122, in each case with the corresponding current limiting reslstors 124 and 123. Down-stream flow produces a positive signal at the terminal 40 and thus a negative voltago at the amplifier 119 output. The in-candescent diode 122 therefore lights up. On reverse flow a positive voltage occurs at the amplifier output so that the incandescent diode 120 lights up and a reverse flow signal is derivable at an output 125 between the incandescent diode 120 and Zener diode 121.
It is also pos~ible to ad~ust the apparatu~ with the ;~
aid of thls lndicator circuit. By reason of the rapid re-spon~e or tracking of the circuit and the omitted feedback at the amplifier ll9~ posltlve and negatlve voltages occur alternately at the output of the ampllfier at zero flow veloclty, whereby the lncandescent dlodes 120 and 122 llght up alternately ln rapid sequence. For the purpose of ad~ustment one can therefore lnterrupt the flow and effect compensatlon lO untll the incandescent dlodes uniformly llght up alternately ~ `
to lndicate zero flow.
In the examples the lndividual amplifiers are opera-~ tional amplifiers which are posslbly adapted for their partl-; cular purpose by ohmic or capacitatlve feedbacks. The signals S30, S39, S43 to S46 are analog slgnals, the slgnals S21, S22 are blnary, quantltles 1 or 0 of substantlally the same duratlon, and S23, S27 S2~, and S34 to S37 are binary quantities 1 or 0 of substantlally the same duration and amplitude. The other signals, apart from the ultrasonic signal of high fre- ~ 20 quency, are lmpul~es or likewlse binary ~ignals. The various unnumbered blocks in the drawings depict gain ~etting re-sistors necessary for the proper functioning of the integrated circuits.
The arrival signal Sll need not be compared directly ; with the reference signal Sl3; ln some cases it is preferable to use a corrected reference signal which is slightly delayed with respect to the reference signal Sl3 as described in ~ USP 3 780 577.
i The several circuit components herein described are of conventional design and available commercially as o~f-the shelf-items By way of example the tran~mission , , . .. .. ~ ,. . . .
, - . , . . ~ .
- . . . . - - .
738~3 device 6 is simply a pulse generator which is capable of shock exciting the transducer 3. In like manner the receiver meal~s 9 is a pulse amplifier capable of amplifying the high frequency pulse trains device from the receiving transducer 4. The switch 10 can be any suitable translstor switching circuitry. The comparator 12 may be of the type described in USP 3,780,577, which receives the transmitted pulse trains and compares it in time phase with the re~erence signal and provides output signals indicative of whether the received signals are early or late with respect to the reference signal.
The voltage controlled oscillator is of a well known design, but, for example, may be in an integrated clrcuit ICL8038.
The operatlonal amplifler used in the various logic circuitry may be for the most part 301A's. The various and/or logic and NOR/NAND logic can be integrated circuits of the 7400 series. The analog switches may be CA4016 circuit chips.
; In like manner the bistable transmission generator 20 may be an element similar to that described in con~unction with the US Patent 3,780,577.
In its simplest form it may be a bistable multi-vibrator or flipflop and the counter 16 may be a conventional binary counter with suitable dividers. The remaining elements of the circuit depicted, particularly by blocks 26, 33, 38, 29, and 41, are all described in detail in the remaining figures of the description of the drawing and are for the most part conventional operational amplifier circuits; they are available from many sources.
3 A relatively stable integration circuit may be made ' 057388 ' utilizing an integrator circuit up-down counter, and the up-down countsr has inputs that are derived in one instance from the early and late signals and in the other instance from the upstream and downstream signals correlated according to time of arrlval such that the counter will count up on the receipt of downstream tlme correlated signals and conversely - .:
`~ will count down upon the receipt of the upstream time correlated signals. The binary output of the counter is applied to a conventional digital analog converter which 10 provides, as is known, an analog voltage which may be used directly to control, through suitable switching circuitry, the voltage controlled oscillator.
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,~ .
`
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BACKG~OUND OF THE INVENTION
This invention relates to ultrasonic flowmeters and, more partlcularly, to method and apparatus for the ultrasonic measurement of the flow velocity of fluent media.
An ultrasonic measuring apparatus is known from U.S. patent 3 818 757, which issued June 18, 1974 to A.E. Brown, ln which frequencies are generated which are a frequency fl on `
~ downstream measurement related to the downstream speed o~ sound ; and a frequency f2 on upstream measurement related to the up-stream speed of sound. From the instant Or transmitting the ultrasonic signal, a predetermined number, for cxample 256, of output pulse~ of the oscillator are counted, whercupon a refer-cnce signal is transmitted. If it is found in a comparator that the ultrasonic signal recelved occur~ earlier than the reference ~ignal, the frequency of the oscillator is ln-creased by means of a slgnal level generator in the form of an integrator, so that the tlming of the reference signal i8 adJusted to the actual arrival time of the ultrasonlc slgnal. If the ultrasonlc signal received occurs later than the reference signal, the frequency of the oscillator is re- -duced. The frequencies fl and f2 thus determined alternately are passed to a respectlve evaluatlng eircuit, stored there until the arrival of the other frequency, and then processed to measuring data corresponding to the flow velocity or ~onic velocity, respectively.
An apparatus of the kind referred to is known from U.S. patent 3 780 57* whlch issued December 25, 1973 to A.E. Brown wherein a signal level generator is providcd for both transmission directions, lt being possible to transmit the early or late signals to the inputs of the signal level generator only lf the associated .- ~
, ::
logic elements simultaneously contain an upstream or a downstream signal, respectively. In this case, the signal .
level is also available in the respective other transmission direction during the measurement. By way of summation and sub~equent lntegration of the signal level) one receives a voltage for controlling an oscillator of which the output frequency is selected as a measurement for the sonic velocity.
The flow velocity is obtained by producing trapezoidal waves from the two signal levels. These trapezoidal waves are 10 generated in a certain relationship to each other by means of s~itches, a quick-acting integrators and comparators. In addition, the output frequency of the oscillator is stepped down to one quarter and modulated by the trapezoidal waves to produce the frequencies fl and f2. The reference signal occurs after each 256 impulsès of the frequencies fl or f2.
Extraordlnarily high requirements are placed on the accuracy of operation of these apparati because the transmisQion time differences are only 10 8 or 10 9 seconds for most applications. To achieve this accuracy, known apparati call 20 for a considerable expenditure. Thi8 refers toJ inter alia, certain circuit configurations, operational ampli~iers of high quality and precision components. This tend~ to make the apparatus expensive.
`~ The underlying ob~ect of the invention is to provide an ultrasonic measuring apparatus of the aforementioned kind having the desired measuring accuracy or even a greater ;` measuring accuracy, parti~ularly for the ~low velocity, and . .
x which can be ~ade considerably more cheaply as a result o~
using a simple circuit construction and normal compone~ts.
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, , ~057388 '~
SUMMARY OF THE INVENTION
In a preferred embodiment, the apparatus includes at least one measuring path which is provided wlth two ultrà~onic transducers, each of which have at least one component extendlng ln the direction of flow and through which ultrasonic signals are transmitted alternately upstream and downstream, comparator means on the receiving side for re-celving on the one hand arrival signals associated with the time of receiving the ultrasonic signals and on the other ; 10 hand reference signals delayed with respect to the transmlssion ! ~ time and for dellvering early and late signals when the arrival ~ignal~ arrive earlier or later than each reference signal, respectively; a control circuit whlch, in logic elements, links to the early and late signals upstream and downstream signals occurring ln dependence on the transmisslon directlon and which contains at least two signal level generators con-trolled ln relatlon thereto so as to produce two control ~lgnals associated with the transmission direction; and at -least one timing generator controlled by the control signals 20 for providing the reference signal.
In such apparatus, the transit time of an ultrasonlc slgnal transmitted downstream along the measuring path ls compared with the translt time of an ultrasonic slgnal trans-mitted upstream along the measuring path. The flow velocity of the medium is then proportional to the difference between, and the sonic velocity in the flowing medium ls proportional to the sum of, the reciprocals of the transit time. In one embodiment the tranæit time is measured by counting a predetermined number of oscillations generated with a vari-30 able frequency oscillator, the flow velocity is proportional : - 4 -i ~357388 to the difference between, and the sonic velocity is propor-tional to the sum of, two frequencies fl and f2 associated with the downstream measurement and upstream measurement, resE~ectively.
The output of the first æignal level generator and the output of the second signal level generator are respectively applied as main signal and auxiliary signal to an adder or summing circuit in which for at least one control signal the auxiliary signal is added to and/or subtracted from 10 the main slgnal. A switch controlled by the transmission direction is provlded by which two different delay periods are alternately made effective for the reference signal.
I~ only one time generator, e.g. an oscillator with series-connected counter ls provided, the swltch may be ln the input for the auxlll~ry slgnal to the summating clrcuit. t Th18 time generator ls therefore alternately fed with an upstream control signal and a downstream control signal, so that the delayed reference 8i~ can be adapted to the arrival time of the ultrasonic signal on upstream measurement 20 or downstream measurement, respectively.
When using two time generators, the switch may be connected after at least a first section of these time generators. When using oscillators with a series-connected common counter, this switch can for example be disposed between the oscillators and the counter.
In such a construction o~ the apparatus, the auxil-iary signal is a direct measure of the flow velocity. This auxiliary signal is effective in at least one of the two regulating circuits that are f~rmed during the upstream 3 measurement or downstream measurement. In these regulating , .:
circuits, the time of occurrence Or the delayed reference signal is adjusted with high accuracy to the arrival time of the received ultrasonic signal. Even if inaccuracies occur within these regulatlng circuits as a result of slmple circuit groups, cheaper components or the llke, they are compensated by the function of the regulating circuit. -Consequently the auxillary signal and thus the measured e flow veloc~ty also have the desired accuracy independently of the quality of the components that are used.
: .
To increase the accuracy, the auxil$ary signal may -be proportionally reducible at the input of or in the summating .. i: -. .
clrcult. The auxillary signal is therefore transmissible by the second signal level generator with a higher proportionality , factor than the maln signal from the first signal level r~ generator. The second signal level generator therefore operates with a comparatively high output level. ~hl~ is po~sible because the main signal and the auxiliary signal are produced separately and fed to the summating circuit through separate paths which could have different loop gains.
In one embodiment, the one control ~ignal i8 formed by the maln signal and the other control slgnal by the sum of or difference between the main signal and the auxiliary signal. If the transit time ls measured by ~requency ~orma-' tion, the main signal corresponds to the frequency fl or *
and the auxiliary signal to the difference between these frequencies so that the control signal alternately corresponds to fl or f2. This can be achieved with a circuit ln which ~ the first signal level generator comprises an integrator ~or ij receiving early signals of one sign and late signals of the opposite sign at its input associated with one of the ~, ., ., :`
- ~, . - .
~0~73~
transmission directions, and in which the second ~ignal level generator comprises an integrator for receiving early slgnalæ of one sign and late signals of the opposite sign at ltæ output associated with the other transmission direction.
In a preferred second embodlment, the one control signal ls formed by the sum of and the other control signal by the difference ~etween the maln signal and the auxiliary BiBnal. Thi8 iS because the main signal is a direct measure-ment for the ~onic velocity in the flow. One can therefore derive both measuring values of principal interest directly from the regulating circuits and with high accuracy. With a tlme measurement on a frequency basis, the main signal corresponds to the mean value of the frequencies fl and f2 and the auxiliary signal to half the difference between these two frequencles.
In a clrcuit that is particularly suitable in this connectionJ the first signal level generator comprises an lntegrator for receiving at its input all early signals of both transmission directions of one sign and all late signals of both transmission directions of the opposite sign, and the second signal level generator comprises an integrator for re-ceiving at its input the early signals or late ~ignals of both transmission directions, the signals of one transmission direction having one sign and the signals of the other trans-mission direction having the opposite sign. In thls construc-tion signals from the upætream measurement as well as the down-stream measurement are evaluated in both signal level generators.
Since all ~arly and late signals of both trans-mission directions are utilized to obtain the maln signal, a very accurate main signal is obtained as a result of the high . . .
~057388 information content. All the early and late signals of both transmlssion directions can also be utilized for the auxili-ary signal, This is achieved for example in that the second slgnal level generator comprises a main integrator and an additional integrator, the additional integrator processing the signals not processed by the main integrator in the same way as the main integrator and the output of the additional integrator being connected to one input of the ma~n integrator.
A simple circuitry is achieved if the second signal level generator comprises a correcting element through which the early signals and the late signals of the one transmission dlrection have the early signals and the late signals of the i other transmission direction added to them before they are fed to the integrator.
In a preferred embodiment, it is insured that the control circuit i8 provided with a ~irst row of two logic elements of which the outputs are occupled in dependence on the presence of the arrival signal and one early or late signal and connected on the one hand to the input circuit of the first integrator of the flrst signal level generator and on the other hand to the input of a second row of four logic elements which can additionally be fed with upstream or down-stream signals in such a way that their outputs are associated with the early signals of the one transmission direction, the early signals of the other transmission direction, the late signals of the one transmission direction or the late signals of the other transmission direction. Two or four of the last-mentioned outputs then serve to feed the second signal level generator.
To the output of the second signal level generator ~573~8 ; there may be applied the input of an amplifier of which the output is connected through two incandescent diodes of i opposite polarity disposed in parallel branches to a voltage reference polnt such as earth, one of the diodes possibly being in series with a Zener diode. This produces indicator means for indicating the measured flow direction by lighting up of one of the two incandescent diodes.
Further, the output of the first signal level generator may have applied to it through a full wave voltage limiter the input of an amplifier of which the output is connected through two parallel incandescent diodes of opposite polarity to a voltage reference point such as earth. In this case one of the incandescent diodes lights up when the sonic velocity exceeds the upper or lower limits of a permissible range.
~ ccording to the method of this invention, fluid flow rate and sound propagation velocity through a fluid are ; measured using upstream and downstream transducers by generat-ing a transmit pulse, generating a reference pulse delayed in time to said transmit pulse, directing the transmit pulses alternately upstream and downstream of the flowing medium, ; receiving the transmitted pulses, comparing the phase of the received and reference pulses, generating logic signals in accordance with the early and late arrival of said received pulses relat~ve to said reference pulses, obtaining the statistical average of all early and all late signals to provide a first signal level related to the sound speed in said medium, generating logic signals corresponding to the early and late arrival of signals relative to said reference signals correlated with the direction of transmission, _ g _ , obtaining the statistical average of at least one pair of --early and late arrival signals to provide a second signal level related to fluid flow velocity of sald medium, selectively subtracting and adding said first and second signQl level for each of said upstream and downstream trans-missions thereby to vary the delay time of said reference pulses for each of said upstream and downstream transmissions such that sald reference pulses track the actual time of arrival of said transmitted pulses.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in more detail wlth reference to examples shown in the drawing, wherein:
Figure 1 is a diagrammatic circuit lay out of a measuring apparatus according to the invention;
Flgure 2 ls a modl~ication of part of the circuit;
Flgure 3 ls a further modlflcation of the clrcuit;
Fi~ure 4 ls an embodiment of the control circuit;
Figure 5 ls a modification of part of the control circuit;
Figure 6 i~ part of the circuit containing the summating element and the switch;
Figure 7 shows the control circuit, switch and ~.
summating circuit for the FIa. 2 embodiment;
Figure 8 is an alternative embodiment of part of the circuit of FIG. 1 uæing an analog time base;
Figure 9 is an indicating circuit for deviatlons in the sonic velocity;
Figure 10 is a circuit for indicating the flow direction; and Figure 11 is a table of the corrections accurring _ 10 --.
~0573~8 in the FIGS. 1, 3 to 5 or 6 embodiments with the various combinations of upstream and downstream, early and late B ignals.
According to FIG. 1, a channel 1 contains an ultra-sonlc measurlng path 2 which is defined by two ultrasonic transducers 3 and 4 and is disposed obliquely to the direction -~
5 of flow of the fluent medium through the channel 1. One transmission device 6 i8 able to pass to the transducer 3 through the line 7 a D. C. impulse S7, which shock excites the transaucer at its resonant frequency so that lt thereupon passes through the medium in the channel 1 an ultrasonic 8 ignal having a frequency of for example 1 MHz. This signal is received by the transducer 4 at the end of the transit time and converted to an electric signal S8 which is fed through a line 8 to receiver means 9. The lines 7 and 8 are interchange-able through a switch 10 so that the transducers 3 and 4 can serve alternately as ultrasonic transmitter and as ultrasonic receiver. Alternatively separate transmitters and receivers may be employed as described in U.S. Patent 3,780,577. In the receiving means 9, a defined arrival signal Sll is obtained from the high frequency signal S8 by means of a zero cross-over detector such as that described in U.S. Patent 3,780,577;
the signal Sll being passed through a line 11 to comparator means 12. These comparator means slmultaneously receive through a line 13 a reference signal S13 with which the arrival signal Sll is compared on a time ~asis.
A voltage-controlled oscillator 14 may serve as time generator; it passes its output oscillations as an impulse chain S15 to a counter 16 through a line 15. On commencement of counting, this counter delivers a transmission signal S17 ~057388 , . .
- to the transmission means 6 through a line 17. At a pre-determined counter content, e.g. 256 impulses, the reference signal S13 is delivered. At an earlier instant (be~ore ~-256 impulses), e.g. 128 impulses, a receiver readiness ;; signal S18 was passed through a line 18 to prepare the ' comparator means ~or measurement. Subsequent to measurement, e.g. 384 impulses, the receiver readiness signal S18 is terminated, thereby disabling the receiver and comparator and protecting against shock excitation during transmission. -Finally a signal Sl9 is fed through a line 19 to a bistable transmission generator 20 which alternately delivers down-stream signals S21 and upstream signals S22 through a pair of signal lines 21 and 22, the latter signals then switching the switch 10 over.
When an arrival signal Sll arrives in the comparator means 12, a signal of predetermlned, constant amplitude and duration appears at the output 23. If thls arrival signal Sll haA arrived earller than the reference signal S13, a signal appears at the output 24. If the arrival signal was determined later than the reference signal, a signal occurs at the out-put 25. A flrst row 26 of logic elements links these three output signals in such a way that in a line 27 an early signal S27 occurs having a constant amplitude and the same time duration as the signal occuring at output 23 and a late signal S28 occurs also having a constant amplitude and the - same time duration as the signals occurring on outputs 23 and 25.
In an integrating signal level such as a generator integrator 29 all early signals S27 are integrated in one direction and all late signals S28 in the opposite. By way - 12 _ ~L~57388 of convention, the + and - signs in the blocks 29 and 38 indicate the direction of integration of early signals S27 ; and late signals S28 which in the embodiments both have posLtive ~oing polarity. For instance, the early signals could be fed to the non-inverting input and the late signals to the inverting input of an operational amplifier serving as an integrator. At the output 30 of the integrator, a main ; signal S30 occurs in the form of a signal level that is variable by the early and late signals. This main signal S30 can be derived directly at an output terminal 31 through an evaluating circuit such as a meter and used as a measure-ment for the sonic velocity c of a medium flowing through the channel 1. In addition, this main signal S30 is passed to an input of a summing circuit such as an adder 32.
The early and late 8 ignals S27 and S28 are addi-tionally fed to a second row 33 of logic elements~ which also have fed to them the downstream and upstream signals S21 and S22. In this way early upstream signals S34, early downstream signals S35, late upstream signals S36 and late downstream signals S37 are obtained at four outputs 34 to 37. A second integrating signal level generator such as an integrator 38 ; is fed with the early downstream signals S35 with positive sign and the early upstream signals S34 with negative sign and possibly also the late downstream signals S37 with negative sign and the late upstream signals S36 with positive sign.
As a result, an auxiliary signal S39 is produced at the out-put 39 in the form of a signal level dependent on the signals S34 to S37.
This auxiliary signal S39 is fed directly to an output terminal 40 from which the flow velocity v of the medium flowing in the channel 1 can be taken directly through `:``
~L~57388 an evaluating circuit. In addition, the auxiliary signalS39 is fed through a switch 41 alternately to the positlve and the negative second input of the summating circuit or adder 32. The switch 41 which ma~ be an analog switch is operated by the downstream and upstream signals S21 and S22.
Control 8 ignals S43 and S44 therefore alternately occur at -the output 42 of the adder, these signals corresponding to the sum of or difference between, respectively, the main signal S30 and the auxiliary signal S39. These control signals S43 and S44 control the voltage-controlled oscillator 14 in such a way that the pulse train S15 alternately has a higher frequency fl associated with the downstream measure-ment and a lower frequency f2 associated with the upstream measurement.
This results in the method of operation to be described hereinafter in con~unction with FIG. 11. Entered in the flve rows 1 - 5 on a time reference there are the transmission signal S17, the arrival signal Sll occurring after the transit time tl, and the reference signal S13 occurring after a delay period tv which may be greater than or less than tl for the downstream measurement as well as for the upstream measurement. There is also an indication as to whether the main signal S30, the auxiliary signal S39 and the control sienals S43 and S44 are increasing, decreasing or remaining unchange*.
Case 1: It is assumed that all arrival signals Sll occur earler than the reference signal S13. The result of this is that the level integrator 29 merely receives posit$ve signals and the main signal S30 increases. On the other hand, positive and negative signals are alternately fed to the 1~57388 second integrator 38 so that the auxiliary signal S39 remains unchanged. Consequently both control signals S43 and S44 in-crease. The frequencies fl and f2 of the pulse trains from the VC0 14 lncrease. The delay period tv is therefore de-creased in both transmission directions because the 256 lmpulses were on each occasion counted in a shorter period of time by the counter 16. During the respective next up-stream or downstream measurement, therefore, the delay period tv has been more closely adapted to the actual transit time tl. Since this procedure is repeated for each measurement, there is ultimate coincidence between the delay period and the transit time or, stated in other words, the frequencies fl and f2 are a measure of or are proportional to the actual transit time tl.
Case 2: All arrlval signals Sll occur later than the associated reference slgnals S13. Exactly the opposite conditions to those ln Case 1 occur. The main slgnal S30 decreases. The auxiliary signal S39 remains unchanged. m e control slgnals S43 and S44 both become smaller. The fre-, 20 quencies ~1 and ~2 both decrease.
Case 3: During the downstream measurement the arrival signal Sll occurs earlier than the reference slgnal S13 and during the upstream measurement lt occurs later. In this case the integrator 2g is alternately supplied wlth positive and negative signals so that the main slgnal S30 re-mains unchanged. on the other hand the second integrator 38 is only supplied with positive signals. Consequently the auxiliary signal S39 increases. As a result the control signal S43 and thus the frequency fl increase but the control 3~ signal S44 and thus the frequency f2 decrease.
1~573~38 Case 4: The arrival signals Sll occur later than the reference signals S13 dur~ng the downstream measurement but earlier during the upstream measurement. The circum-stance~ are the reverse Or those in Case 3. m is means that the frequency fl drops and the frequency ~2 rlses.
Case 5: All arrival signals Sll coincide with the reference signals S13. m e signal level generators 29 and 38 receive no signal. The main signal S30 and auXlliary signal S39 remaln unchanged, as do the frequencies fl and f2.
This is an ideal condition which in practice almost never occurs.
The clrcuit therefore forms a regulating clrcuit in which solely by the statistical evaluation of the early and late signals during the upstream and downstream measurement an ad~ustment of the delay period tv occurs in such a way that the latter accurately coincides wlth the translt time t after a few lndividual measuremcnts. mis regulation takes place with a relativcly high accuracy independently of the quality of the components provided in the regulating circuit.
When the frequencies fl and f2 occur by summstion and subtraction Or the main signal S30 and auxiliary signal S39, a ~imple calculatlon will show that the maln signal S30 is a relatively accurate measure of or proportional to the mean value (fl + f2)/2 and the auxlliary signal S39 is a relatively accurate measure of or proportional to half the difference (fl - f2)/2 of the two frequencies fl and f2. How-ever, since this mean value is proportional to the sonlc velocity of the medium flowing in the channel 1 and the difference is proportional to the flow velocity of thls medium, one can connect output terminals 31 and 40 directly ~57388 to the outputs 30 and 39 to derive signals corresponding to the sonlc velocity c and flow velocity v, respectively.
These signals may have an extraordinarily high accuracy be-, cause they can be derived directly from the self-compensating reeulatlng clrcuit.
Instead of the time generator conslstlngOf the oscillator 14 and counter 16, one can also use an analog time generator such as is illustrated in FIG. 8 and described here-inafter.
lû FIG. 2 shows a modification of the solution accord-ing to FIG. 1, in which the signals S34 to S37 feed two 8 ignal level generators or integrators 43 and 44 ln such a way that the integrator 43 is fed with the early upsteam sig-nal S34 of positive sign and the late upstream signal with negative sign and the integrator 44 is fed with the early downstream signal S35 with positlve sign and the late downstream signal S37 with negative sign. At the output 45 ~-of the integrator 44 a main signal S45 occurs which is applied 1O the one input of the summating clrcult 32. At the output S~ 20 46 of the integrator 43 there occurs an auxiliary signal S46 whlch can be applied to the other input of the summating ~ circuit 32 through a switch 47 that is again controlled by ; the signal direction generator 20. The output terminal 40 -from which a quantlty corresponding to the flow velocity v is derivable ls connected to the output 46 of the integrator 43.
Let one assume that the switch 47 is open during the downstream measurement. The control signal S43 then corresponds to the main signal S45 during the open period. The latter changes in dependence on whether the volatage si gnal integrator 44 is fed with early downstream signals or late downstream ~357388 signals. If only the integrator 44 is included in the re-gulating circult, the main signal S45 therefore corresponds to the frequency fl for the downstream measurement.
If during the upstream measurement the swltch 47 is closed, the auxlliary signal S46 is added to the main signal S45. The auxiliary signal changes in dependence on whether the integrator receives early upstream signals or late up-stream signals. Since during this measurement the control signal S44 is set to a value corresponding to the frequency f2, the auxiliary signal S46 must correspond to the di~ference fl ~ f2. A signal proportional to the flow velocity v can , therefore again be obtained in this way with high accuracy.
' In the embodiment according to FIG. 3 there is shown another modification of the circuit according to FIG. 1.
Here the maln slgnal S30 and the auxiliary signal S39 are fed to two summating circuits 48 and 49 in such a way that the control signal S43 is constantly produced by the sum and the control signal S44 by the difference. The voltage-controlled oscillators 50 and 51 are supplied with these control signals and constantly deliver impulses S52 of the frequency fl or impulses S53 of the frequency f2, respectively. A switch 54 controlled by the signal direction generator 20 applies these impulse chains alternately to a common counter 55 corresponding to the counter 16.
FIG. 4 shows an example of the FIG. 1 control circuit in more detail, in which instead of the reference numerals for the line~ there are in some cases only the reference numerals for the slgnals occurrlng therein. The first row 26 of logic elements~onsists of two AND elements 56 and 57 and the second row 33 of logic elements of four AND elements 58 ~C~57388 to 61. The signal level generator 29 comprises an amplifier 62 having all late signals S28 fed to its non-inverting input and all early signals S27 to its inverting input. This ;~; amplifier is followed by an integration amplifier 63 from the output of which the main signal S30 is derivable. The signal level generator 38 comprises an amplifier 64 having the early upstream signals S34 applied to its non-inverting input and the early downstream signals to its inverting input. A
- correcting circuit 65 permits the inverting input of the amplifier 64 also to be fed with the late upstream signals S36 and the non-inverting input with the late downstream signals S37. The amplifier 64 is followed by an integration amplifier 66 from the output of which the auxiliary signal S39 ~, is derivable.
,' In the embodiment according to FIG. 5 the early j upstream signals S34 are fed to the non-inverting input of the amplifier 64 and the early downstream signals to the -inverting input of this amplifier. The output of the ampli~
fier is again connected to the inverting input of the inte-gration amplifier 66. The late upstream signals S36 are fed to the inverting input of a further amplifier 67 and the late downstream signals S37 to the non-inverting input of this amplifier. The amplifier output feeds an integration ampli-fier 68 of which the output is fed to the non-inverting input of the integration amplifier 66. Here, too, the auxiliary signal S39 can be derived from the output of the integration amplifier 66.
FIG. 6 shows an embodiment of the summing circuit 32 together with the switch 41 according to FIG. 1. The su~mating circuit 32 comprises a first resistance 69 through 573~38 . .:
which the main signal S30 is fed~ a second resistance 70 through which the processed main signal S39 is fed, and a summing bias resistor 71. The summation signal is amplified !~, in an amplifier 72. The amplifier output is applied through ~r a potentiometer 73 to a voltage of +12V, so that the control t~ signals S43, S44 which can be tapped at the potentiometer 73 r:
~, can receive an additional setting for fixing the operating ,..~
,, range.
The switch 41 consists of two electronic switch ' 10 elements 74 and 75 which are made alternately operative by the d~wnstream signals S 2 1 and the upBtream s~gn~ls S22. The auxiliary signal S39 is consequently alternately fed to the inverting an the non-inverting input of an ampli~ier 76, , whilst the re8pective other input of the amplifier 76 is ,s supplied wlth a ~ixed voltage tapped from a voltage divider ~ 77 and 77~. m e ~witched signals S39 is biased by the re-¦ sistor 77' to the same voltage level as the fixed voltage.
The unnumbered blocks in the figures represent various gain setting resistors.
FIG. 7 shows details of the circuit according to FIG. 2, the components to some extent corresponding to those of FIGS. 4 and 7. The first row 26 of logic elements is pro-vided with NAND-elements 56l and 57', the second row 33 is provided with NOR-elements 58', 59', 60' and 61'.
;, The signals S34 to S37 derivable from the second row 33 of logic elements 58' to 61' are here evaluated as follows. The early upstream signals S34 are fed to the in-; verting input of an amplifier 78 and the late upstream signals , S36 to the non-inverting input of this amplifier. The ampli-fier 78 output feeds an integration amplifier 79 from the ~0~7388 output of which the auxiliar~ signal S46 is derivable. The early downstream signals S35 are fed to the inverting input of a~n amplifier 80 and the late downstream signals S37 to the non-invertlng input of this amplifier. The amplifier output feeds an integration amplifier 81 from the output of which -~
the maln signal S45 is tapped. Main signal S45 is passed through a unity gain inverting amplifier 72l to summing cir-cuit 32 for logic purposes. During each upstream measurement, the auxiliary signal s46 is transformed through the amplifier lo 76 and tapped at a potentiometer 82. The control signal S43 therefore corresponds to the main signal S45 or the frequency fl and the control signal S44 to the difference between the main signal S45 and auxiliary signal S46 or the frequency f2.
With the aid of the amplifier 76 in FIGS. 6 and 7 : .
or the voltage divlder 82 in FIG. 7, the auxiliary signal S39 or S46, respectively, can be proportionally reduced by the value occurring at the output of the respective voltage level generator 38 (FIG.l) or 43. This means that at the outputs 39 or 46 of this voltage level generator there occur auxiliary signals which are sharply increased as compared with the values of the main signals S30 or S45, thereby providing larger amplitude signals at the output terminal 40 which in-creases the acouracy of the readout.
For the calibration of the apparatus, switch 83 may be used to apply a k~own constant voltage level to the invert-ing input of amplifier 76. The oDnstant voltage level is provided by a resistor 84 and a zener diode 85. This voltage level simulates a definable value for the auxiliary signal S46 corresponding to a definable flow veloclty. To effect this calibration, first the potentiometer 73 is adjusted until the output levels S43,S44 correspond to the mean sound velocity. Next the sw~ff tch 83 is switched to apply the known voltage and the potentiometer 82 is adjusted. For example, the signal S15 (FIG. 1) can be fed to a measuring device and the potentlometer 82 can be adjusted until the period of the VC0 will have a value corresponding to the defined flow velocity plus mean sound speed. ;
In Figure 8 another circuit is shown according to -.. . .
which the reference signal S13, the transmission signal S17, the receiver readiness signal S18 as well as the downstream signal S21 and the upstream signal S22 of FIG. 1 are produced ,- by the main signal S30 and the auxiliary signal S39.
The auxiliary signal S39 is inverted in an inverting i,f amplifier 86 having the ampllfication factor of one. The ; non-lnverted and the inverted auxiliary signal S39 is fed alternatlvely to the summing circult 32 by means of the ; switch 41 which i8 constructed as an analog switch being controlled from the downstream and upstream signals S21 or S22J respectively. A potentiometer 87 serves to set the magnitude of the auxiliary signal S39 to be entered into the summing circuit 32. The main signal S30 is fed through re-sistor 88, the auxiliary signal S39 is fed through a resistor 89. A zener diode 90 in connection with resistances 91 and 92 serves to produce a summ1ff ng bias voltage.
The timing generator 14 includes an analog time base in the present exa~ple. For such purpose, the control ~- signals S43 and S44 from the summing circuit 32 were fed to an integrator 93 at the output line 94 of which a gradually increasing signal S94 appears, therefore, until switching back takes place which is described later. Said signal S94 is fed to the non-inverting input of four comparators 95 - 98.
,;
The inverting inputs of said comparators are connected to a voltage divider which is formed by the resistors 99 - 102 and a Zener diode 103. Therefore, the comparators deliver a corresponding output signal S95, S96, S97 and S98 at di~ferent lnstants depending upon when the rising signal S94 ;~ reaches the bias voltage of each.
m ese output signals S95 - S98 actuate three D-fllpflops 104, 105 and 106 as well as a monostable multi-vibrator 107. The signal S96 is fed to the C-input of flip-flop 106. Therefore, the receiver readiness signal S18 appears at the Q-output. Sometime later the signal S97 which could be used directly as reference signal S13, appears at comparator 97. Again some time later signal S98 appears which is applied to one input of an AND~element 108 the other inhibit input of which is connected to a polnt of reference potential. The monostable multlvibrator 107, which is triggered by the appearance of signal S98, therefore produces at its output Q a signal S109 which is applied to the C-input of flipflop 104 which therefore effects a switching from downstream signal S21 to upstream signal S22 or vice versa.
At the end of a predetermined delay time a signal SllO appears at the ~-output of the monostable multivibrator 107, which is applied on the one hand to the R-input of flipflop 106 and therefore finishes the receiver readiness signal S18 and on the other hand to the C-input of flipflop 105. This provides a signal Slll at the Q-output which is applied through a diode 112 and a resistor 113 to the input of the integrator 93.
Said signal has such polarity that the output signal S94 de-creases quickly to zero. As soon as the comparator 95 detects that zero level is reached, signal S95 is applied to the R-input ~S7388 of fliprlop 105 to reset the flipflop. Startlng from this moment, integrator 93 is fed again by one of the signals S43 or S44, respectively,andat the Q-output of flipflop 105 the transmisslon sienal S17 appears. Now a new cycle starts.
Flgure 9 shows an indicator apparatus with two back to back lncandescent dlodes 114 and 115 which are connected from the output Or an amplifier 116 to ground. The one ampllfier input is connected to the connecting terminal 31 for the sonic velocity c through a bipolar voltage reference diode in the form of the series circuit of Zener diodes 117 and 118 of oppoæite polarity. As soon as the voltage at the output terminal 31e~ceeds the blocking voltage in the one or other direction, one or other incandescent diode lights up depend-ing on the voltage directlon so as to indicate that the set operating range of the apparatus i~ exceeded. The permissible ~i operatlng range can then for example be reset bg ad~u~ting the potentiometer 73.
Figure 10 relates to an indicating apparatus for the ilow direction. Connected to the output terminal 40 for the flow velocity v there i8 the one input of an amplifier 119 of which the output i8 applied to earth through the æeries clrcuit Or an incandescent diode 120 and a zener dlode 121 both in shunt with an incandescent diode 122, in each case with the corresponding current limiting reslstors 124 and 123. Down-stream flow produces a positive signal at the terminal 40 and thus a negative voltago at the amplifier 119 output. The in-candescent diode 122 therefore lights up. On reverse flow a positive voltage occurs at the amplifier output so that the incandescent diode 120 lights up and a reverse flow signal is derivable at an output 125 between the incandescent diode 120 and Zener diode 121.
It is also pos~ible to ad~ust the apparatu~ with the ;~
aid of thls lndicator circuit. By reason of the rapid re-spon~e or tracking of the circuit and the omitted feedback at the amplifier ll9~ posltlve and negatlve voltages occur alternately at the output of the ampllfier at zero flow veloclty, whereby the lncandescent dlodes 120 and 122 llght up alternately ln rapid sequence. For the purpose of ad~ustment one can therefore lnterrupt the flow and effect compensatlon lO untll the incandescent dlodes uniformly llght up alternately ~ `
to lndicate zero flow.
In the examples the lndividual amplifiers are opera-~ tional amplifiers which are posslbly adapted for their partl-; cular purpose by ohmic or capacitatlve feedbacks. The signals S30, S39, S43 to S46 are analog slgnals, the slgnals S21, S22 are blnary, quantltles 1 or 0 of substantlally the same duratlon, and S23, S27 S2~, and S34 to S37 are binary quantities 1 or 0 of substantlally the same duration and amplitude. The other signals, apart from the ultrasonic signal of high fre- ~ 20 quency, are lmpul~es or likewlse binary ~ignals. The various unnumbered blocks in the drawings depict gain ~etting re-sistors necessary for the proper functioning of the integrated circuits.
The arrival signal Sll need not be compared directly ; with the reference signal Sl3; ln some cases it is preferable to use a corrected reference signal which is slightly delayed with respect to the reference signal Sl3 as described in ~ USP 3 780 577.
i The several circuit components herein described are of conventional design and available commercially as o~f-the shelf-items By way of example the tran~mission , , . .. .. ~ ,. . . .
, - . , . . ~ .
- . . . . - - .
738~3 device 6 is simply a pulse generator which is capable of shock exciting the transducer 3. In like manner the receiver meal~s 9 is a pulse amplifier capable of amplifying the high frequency pulse trains device from the receiving transducer 4. The switch 10 can be any suitable translstor switching circuitry. The comparator 12 may be of the type described in USP 3,780,577, which receives the transmitted pulse trains and compares it in time phase with the re~erence signal and provides output signals indicative of whether the received signals are early or late with respect to the reference signal.
The voltage controlled oscillator is of a well known design, but, for example, may be in an integrated clrcuit ICL8038.
The operatlonal amplifler used in the various logic circuitry may be for the most part 301A's. The various and/or logic and NOR/NAND logic can be integrated circuits of the 7400 series. The analog switches may be CA4016 circuit chips.
; In like manner the bistable transmission generator 20 may be an element similar to that described in con~unction with the US Patent 3,780,577.
In its simplest form it may be a bistable multi-vibrator or flipflop and the counter 16 may be a conventional binary counter with suitable dividers. The remaining elements of the circuit depicted, particularly by blocks 26, 33, 38, 29, and 41, are all described in detail in the remaining figures of the description of the drawing and are for the most part conventional operational amplifier circuits; they are available from many sources.
3 A relatively stable integration circuit may be made ' 057388 ' utilizing an integrator circuit up-down counter, and the up-down countsr has inputs that are derived in one instance from the early and late signals and in the other instance from the upstream and downstream signals correlated according to time of arrlval such that the counter will count up on the receipt of downstream tlme correlated signals and conversely - .:
`~ will count down upon the receipt of the upstream time correlated signals. The binary output of the counter is applied to a conventional digital analog converter which 10 provides, as is known, an analog voltage which may be used directly to control, through suitable switching circuitry, the voltage controlled oscillator.
, .
,~ .
`
.
Claims (20)
1. In apparatus for the measurement of fluid flow rate using ultrasonic signals, said apparatus having first and second transducers positioned in relative upstream and downstream locations in communication with the fluid to be measured for alternately transmitting said ultrasonic signals in opposite senses therebetween, the combination comprising:
a timing generator for controlling the transmission times of said ultrasonic signals and generating a reference signal delayed with respect to each said transmission time, comparator means for generating early and late signals according to whether the received ultrasonic signals are early or late relative to each said reference signal, a first signal level generator responsive to at least some of said early and late signals for generating a first signal level related to sound speed in said fluid, logic means responsive to said comparator means and to the sense of transmission of said ultrasonic signals for generating early and late signals correlated with transmission direction upstream and downstream, a second signal level generator responsive to at least two of said early and late signals correlated with trans-mission direction for generating a second signal level different than said first level related to said fluid flow rate, and adder means responsive to said first and second signal levels for generating control signals related respect-ively to the upstream and downstream speeds of sound for controlling the timing of said timing generator.
a timing generator for controlling the transmission times of said ultrasonic signals and generating a reference signal delayed with respect to each said transmission time, comparator means for generating early and late signals according to whether the received ultrasonic signals are early or late relative to each said reference signal, a first signal level generator responsive to at least some of said early and late signals for generating a first signal level related to sound speed in said fluid, logic means responsive to said comparator means and to the sense of transmission of said ultrasonic signals for generating early and late signals correlated with transmission direction upstream and downstream, a second signal level generator responsive to at least two of said early and late signals correlated with trans-mission direction for generating a second signal level different than said first level related to said fluid flow rate, and adder means responsive to said first and second signal levels for generating control signals related respect-ively to the upstream and downstream speeds of sound for controlling the timing of said timing generator.
2. Apparatus according to Claim 1 wherein said second signal level generator is responsive to said late upstream and downstream signals.
3. Apparatus according to Claim 1 wherein said second signal level generator is responsive to said late upstream and said early downstream signals.
4. Apparatus according to Claim 1 wherein said second signal level generator is responsive to said early upstream and said early downstream signals.
5. Apparatus according to Claim 1 wherein said second signal level generator is responsive to said early and said late downstream signals.
6. Apparatus according to Claim 1 wherein said timing generator provides an output signal level, the trans-mission times and the delay times of said reference signal being a function of the amplitude of said output signal level.
7. Apparatus according to Claim 1 which includes means for pooportionally reducing the amplitude of said second signal level.
8. Apparatus according to Claim 1 wherein one of said control signals is formed by adding said first and second signal levels and the other of said control signals is formed by subtracting said first and second signal levels.
9. Apparatus according to Claim 1 wherein the first signal level generator comprises an integrator for receiving early signals of one sign and late signals of the opposite sign at its input associated with one of the transmission directions, and that the second signal level generator com-prises an integrator for receiving early signals of one sign and late signals of the opposite sign at its input associated with the other transmission direction.
10. Apparatus according to Claim 1 which includes switch means responsive to transmission direction for effect-ing different delay times for said reference signals for each of said transmission directions.
11. Apparatus according to Claim 10 wherein said adder means includes a first adder for adding said first and second signals, a second adder for subtracting said first and second signals, said switch means being coupled between said first and second adders and said timing generator.
12. Apparatus according to Claim 10 wherein the first signal level generator comprises a first integrator coupled to receive at its input all early signals of both transmission directions of one sign and all late signals of both transmission directions of the opposite sign, and that the second signal level generator comprises a second integrator coupled to receive at its input the early signals and late signals of both transmission directions, the signals of one transmission direction having one sign and the signals of the other transmission direction having the opposite sign.
13. Apparatus according to Claim 12 wherein the second signal level generator comprises a correcting means in which the early signals and the late signals of the one transmission direction have the early signals and the late signals of the other transmission direction added to them before they are fed to the second integrator.
14. Apparatus according to Claim 10 wherein the second signal level generator comprises a main integrator and an additional integrator, wherein the additional integrator is coupled to receive one of said pairs of early signals and late signals of both transmission direction, the main integrator is coupled to receive the other of said pairs of early and late signals of both transmission directions, and the output of the additional integrator is connected to one input of the main integrator.
15. Apparatus according to Claim 12 wherein said logic means is coupled to the input circuit of said first integrator and to the input of a row of four logic elements which can additionally be fed with upstream or downstream signals in such a way that their outputs are associated alternatively with the early signals of the one transmission direction, the early signals of the other transmission direction, the late signals of the one transmission direction and the late signals of the other transmission direction.
16. Apparatus according to Claim 13 wherein said logic means is coupled to the input circuit of said first integrator and to the input of a row of four logic elements which can additionally be fed with upstream or downstream signals in such a way that their outputs are associated alternatively with the early signals of the one transmission direction, the early signals of the other transmission direction, the late signals of the one transmission direction and the late signals of the other transmission direction.
17. Apparatus according to Claim 10 which includes an amplifier connected to the output of the second signal level generator, a pair of incandescent diodes of opposite polarity connected in parallel between a point of reference potential and the output of said amplifier.
18. Apparatus according to Claim 10 which includes a full wave voltage limiter connected to the output of the first signal level generator, an amplifier, the input of a pair of parallel connected incandescent diodes of opposite polarity connected between the output of said amplifier and a point of reference potential.
19. Apparatus according to Claim 10 which includes means coupled to the output of said second signal level generator for providing normal and inverted outputs, and means for selectively adding said normal output to the output of said first generator during upstream flow and said inverted output during downstream flow.
20. A method of measuring fluid flow rate and velocity of sound propagation through a fluid utilizing at least one pair of first and second energy transducers capable of functioning as transmitters and receivers in communication with the fluid which comprises generating a transmit pulse, generating a reference pulse delayed in time to said transmit pulse, directing the transmit pulses alternately upstream and downstream of the flowing medium, receiving the trans-mitted pulses, comparing the phase of the received and re-ference pulses, generating logic signals in accordance with the early and late arrival of said received pulses relative to said reference pulses, obtaining the statistical average of all early and all late signals to provide a first signal level related to the sound speed in said medium, generating logic signals corresponding to the early and late arrival of signals relative to said reference signals correlated with the direction of transmission, obtaining the statistical average of at least one pair of early and late arrival signals to provide a second signal level related to fluid flow velocity of said medium, selectively subtracting and adding said first and second signal level for each of said upstream and downstream transmissions thereby to vary the delay time of said reference pulses for each of said upstream and down-stream transmissions such that said reference pulses track the actual time of arrival of said transmitted pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA257,785A CA1057388A (en) | 1976-07-26 | 1976-07-26 | Method and apparatus for the ultrasonic measurement of the flow veiocity of fluent media |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA257,785A CA1057388A (en) | 1976-07-26 | 1976-07-26 | Method and apparatus for the ultrasonic measurement of the flow veiocity of fluent media |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1057388A true CA1057388A (en) | 1979-06-26 |
Family
ID=4106509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA257,785A Expired CA1057388A (en) | 1976-07-26 | 1976-07-26 | Method and apparatus for the ultrasonic measurement of the flow veiocity of fluent media |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1057388A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113188746A (en) * | 2021-03-12 | 2021-07-30 | 同济大学 | Non-contact regional fluid vorticity measuring method |
-
1976
- 1976-07-26 CA CA257,785A patent/CA1057388A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113188746A (en) * | 2021-03-12 | 2021-07-30 | 同济大学 | Non-contact regional fluid vorticity measuring method |
| CN113188746B (en) * | 2021-03-12 | 2023-03-14 | 同济大学 | Non-contact regional fluid vorticity measuring method |
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