CA1056491A - Apparatus for determining the arrival time of alternating signals - Google Patents
Apparatus for determining the arrival time of alternating signalsInfo
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- CA1056491A CA1056491A CA257,742A CA257742A CA1056491A CA 1056491 A CA1056491 A CA 1056491A CA 257742 A CA257742 A CA 257742A CA 1056491 A CA1056491 A CA 1056491A
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Abstract
Serial No. 257 742 Danfoss A/S
(Brown, Alvin E.) APPARATUS FOR DETERMINING THE ARRIVAL, TIME OF ALTERNATING SIGNALS
ABSTRACT OF THE DISCLOSURE
Received ultrasonic bursts of energy are rectified and converted into pulse trains and also envelope detected.
The envelope is red to a ramp generator whose output is threshold detected to provide an arrival delay signal corresponding in time to the peek amplitude of the received bursts. A regulator circuit varies the timing of the arrival delay signal to coincide with the next negative-going zero crossover of the pulse train, A timing generator provides a reference delay offset, relative to the transmission time of the ultrasonic bursts, by the expected transit time there-of. The timing of the reference signal is varied in the same manner as the arrival delay signal by the regulator circuit and compared with the positive-going zero-crossover in the pulse train next following the negative-going zero-crossover.
Thus determined accurately the actual time of arrival of the bursts, using low cost components.
(Brown, Alvin E.) APPARATUS FOR DETERMINING THE ARRIVAL, TIME OF ALTERNATING SIGNALS
ABSTRACT OF THE DISCLOSURE
Received ultrasonic bursts of energy are rectified and converted into pulse trains and also envelope detected.
The envelope is red to a ramp generator whose output is threshold detected to provide an arrival delay signal corresponding in time to the peek amplitude of the received bursts. A regulator circuit varies the timing of the arrival delay signal to coincide with the next negative-going zero crossover of the pulse train, A timing generator provides a reference delay offset, relative to the transmission time of the ultrasonic bursts, by the expected transit time there-of. The timing of the reference signal is varied in the same manner as the arrival delay signal by the regulator circuit and compared with the positive-going zero-crossover in the pulse train next following the negative-going zero-crossover.
Thus determined accurately the actual time of arrival of the bursts, using low cost components.
Description
1(~5ti4~
BACKGROUND OF THE INVENTION
This invention relates to app~ratus for determln-in~s the arrival time of alternating slgnals and, more particularly, to apparatus for determlning the arrival tlme of an ultrasonic signal.
From German Patent 2,322,749 and U. S. Patent 3,780,577 devices are known for the ultrasonic measurement of the flow velocity of fluent media and the sonic velocity in fluent media, in which ultrasonic signals are alternately transmitted upstream and downstream along a measuring path which is provided with two ultrasonic transducers and has at least one component extending in the flow direction. At the instant of transmission, the transducer on the transmission side ls momentarily energized and a time generator ls simultaneously actuated whlch dellvers a reference signal after the expected transit time. The time generator may include a voltage-controlled oscillator which i~ operated at a frequency fl during downstream measurement and with a frequency f2 during upstream mea~urement. A series-connected counter counts a predetermined number of output impulses after the instant of transmission. If the expected transit time is shorter than the actual transit time, the frequency of the oscillator is reduced by means of regulating circuit; if the expected transit time is longer than the actual transit time, the frequency of the oscillator is increased by means ; of the regulating circuit. By reason of this adaption, the oscillator frequencies correspond to the reciprocal values of the downstream and upstream transit times and can be ~valuated to obtain the flow velocity and the sonic velocity.
If the transducer on the transmission side in such an apparatus .,, ~
,~' ~ 0 5 is energized at the instant of transmis~lon, it will no~
lmmediately emlt the high frequency ultr~sonic signal9 which may for example have a fre~uency of 1 MHz, at maxlmum amplitude; the amplitude rather lncreases gradually. As a result, the end o~ the transit tlme, that is to say the commencement of the ultrasonic signal on the receiver side, can only be determined by the ~act that the transducer on the receiver slde receives an ultrasonlc osclllat10n which is only llttle different from zero. This does not permit accurate measurement. In the known cases, therefore, the actual instant of comparison has been delayed with reference to the commencement of the signal. This occurs on the re-ceiver side with the aid of arrival delay means by which the received ultrasonic signal i~ rectified, at least the first portion of the envelope of the rectified ultrasonlc signal i8 converted to a substantially llnear rising signal, and the latter is fed to a threshold value detector which, on reach-ing the threshold value, delivers an arrival delay signal that ~ is delayed relatively to the actual arrival. In a second 20 channel the received ultrasonic signal is amplified and clipped so that a rectangular signal of the same phase is obtained. The zero crossover of this rectangular signal wlth rising or positive-golng leading edge following the arrival delay signal is utilized as a corrected arrival signal.
Simultaneously, in the reference delay means a reference de-lay time was added at the instant of the actual reference ~ signal, the re~erence delay time being constant, as is the ;~ arrival delay time, but somewhat larger than same. At the end o~ this reference delay time a time comparison signal is delivered as a corrected reference signal which is compared , . . . .
lOS~:;491 with the aforementioned zero crossover. It iR immaterlal whether on the recelver side the commencement of the arrivlng ultrasonic signal is determined very accurately.
Thls 18 because a sllghtly retarded determination of the co~encement of the slgnal merely displaces the arrival de-lay time and thus the arrlval delay signal but not the selected zero crossover that i8 used for the measurement.
Thls results ln a very high measuring accuracy.
However, dlfflcultles arise when the commencement of the arrlving ultrasonlc slgnal is determined so late that the arrival delay signal appears immediately prior to the selected zero crossover. In that case lt can happen that the next zero crossover is instead used for the measurement and the measuring result iA in error. One was therefore compelled to u~e very accurately operatlng components on the receiver side for permitti~g determination of commencement of the slgnal as rapldly as possible, preferably stlll within the flrst half period.
The lnventlon is based on the ob~ect of providing - 20 an lmproved apparatus of the aforementloned klnd in whlch ;
accurate determination of the commencement time 18 possible without placing such high requlrements as hltherto on the accurate determination of the commencement of the arrivlng ultrasonlc signal.
SUMMARY OE THE INVENTION
This ob~ect is ~ul~illed in accordance wlth the invention by a phase detector which determines the phase position of the arrival delay signal with reference to a zero crossover of the trailing edge of one of the pulses in a pulse train derived from the received signal, and by ~OSf~491 regulating means which act on the arrival delay means andJ
in dependence on the phase position, change the arrival de-lay time in the sense of displacing the arrival delay signal tow~ards the last-mentioned zero crossover.
In thls construction, the arrlval delay time is no longer constant but variable. By a regulating circuit it is passed after the zero crossover of the pulse traln which precedes the zero crossover to be ~elected by half a period.
This ensures on the one hand that the arrival delay signal appears in sufficient time to enable the next zero crossover that serves for the measurement to be selected with cer-talnty and on the other hand that late determination of commencement of the signal is permissible within wider limit~
than hitherto because the arrival delay tlme is automQtlcally shortened correspondingly. Thls also permlts one to use simpler readlly available circuit elements because the regu-lating clrcuit compensates the errors caused thereby.
It is also advantageous lf the regulating means i also act on the reference delay means and change the reference delay time in the same sense as the arrival delay tlme. Thls enables further correctlons to be made automatically wlthout the need for recalibrating the instrument and ~nsures the ref-erence delay time coincides with the leading edge of the next positive-going signal followlng the zero cross~ng.
In an apparatus wherein in the arrlval delay means -; the received ultrasonic signal is rectified, at least the first portion of the envelope of the rectified ultrasonic signal is transformed to a substantially linear rising signal and the latter is fed to a threshold detector which .:
causes the arrival delay signal to be emitted when the ' 105~:i491 threshold value ls reached, lt is preferred that the phase detector deliver e~rly slgnals when the arrival delay slgnal arrives too early and late signals when it arrives too late, that the early signals of one slgn and the late slgnals of opposlte sign can be fed to an lntegrator, and that a control voltage derivable at the output of the integrator serves to change the arrival delay time. When the phase posltion of the arrival delay slgnal coincides accurately wlth the zero croæsover of the other polarity, early and late signals occur alternately so that the integrator dellvers a constant control voltage. If the early æignalæ or the late signals predominate, the control voltage decreases or rises, respectlvely.
In particular, the phase detector can co~prlse a r~fllp-flop of which the preparatory or data input has the pulse traln fed to lt, the stage or clock input haæ the arrlval delay signal fed to lt, one output delivers the early 8 lgnals and the other output delivers the late signals.
It is of particular advantage if the control volt-age is feedable to the one input and the envelope to the other input of a differential amplifier producing the linesr rising slgnal. If the difference between the control voltage and the envelope increaæes, the threshold value is reached earlier and if the difference decreases the threshold value is reached later. The control voltage could instead exert in~luence in a different manner, for example by altering the threshold value itself.
In a preferred embodiment the reference delay means include a monostable multi-vibrator which is triggered by the reference signal and which compriseæ an RC element determining the trigger period, the condenser charglng voltage of the RC
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element being governed by the control voltage, and also in-clude a fllp-~lop whlch is resettable after each measurement and which is set by the multi-vlbrator at the end o~ each trlgger perlod and thcn dellvers the time comparison signal.
The leading edge of the time comparison signal serves ror the accurate determinatlon of the end of the referenee delay time. It iB a permanent binary signal which terminates only on resetting.
Further~ on reaching the threshold value, the threshold generator may del~ver a threshold signal which sets a fllp-flop that is resettable after each measurement and delivers the arrival delay signal. The arrival delay signal is therefore also a permanent binary slgnal which terminates only upon re~etting the flip-~lop and the leading edge of which accurately indicates the end o~ the arrival delay time.
e zero cross-over detector pre~erably comprise a D-~lip-flop which 18 resettable after each measurement, has the arrlval delay signal fcd to its preparatory input and the rectangular 8 lgnal to lts stage input and delivers the zero passage slenal at one output. The zero pa~sage 8ignal is therefore a permanent blnary signal which terminates on resetting the flip-flop and the leadlng edge o~ which , ... .
accurately glves the lnstant o~ the zero passage.
In an advantageous embodiment, the arrival ti~e detector comprises a D-flip-flop ~hich has the time comparison ~, sig~al fed to it~ preparatory input and the zero pa~sage signal ~ed to its stage input, and delivers an early measured :`
signal at its one output and a late measured signal at its other output depending on whether the zero crossover signal occurs before or a~ter the time comparison signal. m e early ~, !, ~056~91 or late measured signals can than be evaluated in the usual way for measuring and indicatlng purposes, for example to ada]pt the frequency of the time generator oscillator to the actual transit tlme.
Further, indicatlng means may be provided comprising two incandescent diodes each energized by an inverter con-trolled by the early or late slgnals, respectively. On correct functioning of the regulating circuit, these incan-descent diodes should light up alternately.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in more detail with reference to the example shown in the drawing, wherein:
Figure 1 is a block circuit diagram of an ultrasonic measuring apparatus comprising the apparatus according to the inventlon;
Figure 2 is a simplifled repreRentation of the cir-cuitry of one embodiment of the apparatus;
Figure 3 shows the time course of the transmission signal, ultrasonic signals, counting slgnals and reference signal, and Figure 4 shows the time course of various signals occurring in the apparatus.
According to FIG. 1, a channel 1 contains an ultra-sonic measuring path 2 which is limited by two ultrasonic transducers 3 and 4 and diæposed obliquely to the flow direc-tion 5 of the medium flowing through the channel 1. Trans-mission means 6 deliver an energizing signal S7 to the trans-ducer 3 through the line 7, the transducers thereupon deliver-ing an ultrasonic signal at the transducer's resonant fre-quency, for example 1 MHz through the medium in the channel 1.
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At the end of the transit time, this signal is received by the tranRducer 4 and converted to an electrlc ul*rasonic signal S8 which i~ ~ed through a line 8 to receiver means 9.
m e llnes 7 and 8 are interchangcable by a swi~ch 10 80 that the transducers 3 and 4 can alternately serve aR ultrasonic transmltter and as ultrasonic receiver. In the recelving ~eans the ultrasonic signal S8 is ampllfled and then pro-cessed ~urther in two channels.
m e first channel comprises an amplifier 11, in the output line 12 Or which there occurs a rectangular signal or pulse train S12 having the frequency of the ultrasonic signal S8. In the second channel there are arrival delay means 13, at the output 14 of which an arrival delay signal S14 occurs at the end of an arrival delay time. In a phase detector 15 the arrival delay signal S14 is compared with the ad~oining traillng edge Or an impulse of the rectangular signal S12.
The phase detector emlts early signals S16 or late signals S17 depending on whether the arrival delay signal S14 occurred earlier or later than the trailing edge of the impulse of the rectangular Rignal S12. Regulating means 18 are controlled in dependence on this, the regulating means delivering an output signal Sl9 to the arrival delay means 13 so that the arrival delay time ls shortened or extended until the arrival delay signal S14 accurately coincides with the trailing edge.
This determines a defined zero pas5age with the trailing edge of thc rectangular sig~al S12.
;The arrival delay signal S14 is further fed to zero ;~;cross-over detector 20 which are also fed by the rectangular slgnal S12. A zero cro~sover signal S21 occurs at the output 21 when the first rising flank or leading edge of the .:
-. - g _ , ' '' ~`'' : , . . . . . . ... .
rectangular 8 ignal S12 appears after occurrence o~ the arrival delay signal S14. Thls determines a deflned zero passage.
The zero passage signal S21 is compared with a time comparison ~lgnal S23 ln an arrival tlme detector 22. An early measured signal S24 is cmitted lf the zero passage signal S21 occur~ earlier than the time comparison signal S23 and a late measured signal S25 is emitted if it occurs later. As will be evident from the Applicant~' copending appllcation No. 257 785 flled July 26J 1976 entitled "Apparatus for the ultra~onic measurement of the flow velocity of fluent media", integration of all early measured signals of one sign and all late mea~ured signals of the opposite sign ln a voltage level generator 26 can give a main signal S27 which is a direct measurement for the sonlc velocity c. In a sccond signal level generator 28 the early and latç mea6urcd signal~ are evaluated wlth regard to the up~tream signals S29 and downstream signals S30 which indicate the transmission direction. By lntegrating all downstream early measured signals of one sign and all upstream early measured signals o~ the opposite sign, an auxiliary sienal S31 is obtained which is a measurement for the flow velocity v. The late m~asured signals or the early and late measured signals can be processed in a similar manner.
The main slgnal S27 is fed directly to a summing circuit 32 but the auxiliary signal S31 is fed with alter-nately positive and negative sign through a switch 33 which is dependent on the transmission direction. Consequently control signals S35 and S36 occur alternately at the output of the sum~ing circuit, the control signals -ln~luencing a ~ voltage-controlled oscillator 37 in such a way that it - 30 delivers at its output 38 train~ of impulses S38 with a ,~
,~
105~i45~1 frequency fl on downstream measurement and a lower frequency f2 on upstream measurement. These trains of impulses are fed to a counter 39 which, after counting 256 impulses by way of example, delivers a reference signal S40, a resetting signal S41 a little later, then a transmission direction changing signal S42 and, simultaneously with commencement of counting, a transmission signal S43 to the transmission means 6. The reference signal S40 is fed to reference delay means 44 in which, on arrival of the reference signal S40, a reference delay time is started; at the end of the reference delay time the time comparison signal S23 is emitted. In addition, the control signal Sl9 is fed through the input 45 and with the aid of this the reference delay time is variable. The trans-mis810n directlon changing signal S42 is fed to a direction generator 46 which switches over the switches 10 and 33 and feeds the corresponding downstream and upstream signals to the - signal level generator 28.
FIG. 2 3hows an embodiment for the equipment 9, 11, 13J 15, 18, 20, 22 and 44 of FIG. 1. The receiver means 9 comprises in the final stage an amplifier 47 of which the in-verting input has the electric ultrasonic signal S8 fed to it.
In this amplifier, the gain can be regulated. By means of a circuit (not shown), regulation is effected by applying a regulating voltage to a terminal 48 in such a way that the amplitude of an envelope curve signal S49 occurring at the output 49 of an amplifier 50 remains constant. The output of this amplifier 47 can have interfering frequencies, which do not correspond to the ultrasonic frequency, removed from it by an LC filter circuit 51. m e signal values thus obtained are so amplified and clipped in the amplifier 11 that the ':
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rectangular signal S12 appears in the line 12. The ~mplified ultrasonic signal is additionally fed to two field effect transistors 52 and 53 for the purpose of full wave rectifica-tion so that a rectified ultrasonic signal S54 appears at their output 54. This rectified signal is smoothed in the amplifier 50, which serves as low-pass filter, so that the envelope curve S49 appears at the output 59.
The envelope S49 is fed to a differentiator 55 (which in a preferred embodiment may be a ramp amplifier whose slew rate is limited). The differentiator delivers a signal S56 at its output 56 with a constant slope determined by the slew rate of ramp amplifier as long as the rise time of the input envelope S49 exceeds the slew rate of the amplifier.
This output signal S56 is compared in a threshold value de-tector 57 with a fixed threshold value supplied through the input 58 by a voltage divider 58'. On reaching this threshold value, a signal S59 is applied to the clock input C of a D-flip-~lop 60 which is set to emit the arrival delay signal S14 at its output Q until resetting is effected by the re-~0 setting signal S41.
The arrival delay signal S14 is fed to the stage orclock input of a D-flip-flop 61, of which the preparatory in-put D is fed with the rectangular signal S12. Consequently, early signal S16 appears at the output Q or late 8 ignal S17 at the output Q, which are gated with the arrival delay signal ~ S14 in NAND elements 62 or 63 and therefore can be fed to an integrator 64 as impulses of substantially constant charge.
The early signals are fed to the inverting and the late signals to the non-inverting input of the integrator 64. If the arrival delay signal S14 does not accurately coincide with ..
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105f~49~
the trailing edge of an impulse of the rectangular signal S12, the number of early or late slgnals predominates and the size of the control voltage Sl9 changes at the output of the integrator 64. This output voltage is fed to the non-inverting input of the ramp amplifier 55, as a result of ~hlch the output voltage S56 is displaced upwardly or downwardly parallel to ltself. Thls changes the point of lntersectlon with the threshold value and thus the instant of the threshold value signal S59 and of the arrival delay signal S14 until the last-mentioned signal again coincides with the falling flank of the rectangular slgnal S12.
The thus regulated arrival delay signal S14 is fed to the preparatory input D of the D-flip-flop 65 serving as zero crossover detector to the stage input C of which the rectangular signal S12 is fed. Consequently, during the next zero crossover, i.e. at the leading edge of the next lmpulse in the rectangular signal S12, the zero crossover signal S21 occurs at the output Q and remain~ until the out-put condition of the flip-flop 65 is reset by the resetting signal S41.
The control voltage Sl9 acts through a voltage divider 66 on an RC element 67 of a monostable multi-vibrator 68 which is triggered by the re~erence signal S40 and, after a period determined by the RC element 67, returns to its orlglnal state. During the triggered period, which also ~erves as a reference delay time, a signal S69 occurs at the output Q of the multi-vibrator 68. This slgnal is fed to the setting input C of a further flip-flop 70 whLch then emits ~; the time comparison signal S23 at its output Q until reset by the resetting signal S41.
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~OSf~491 A D-~lip-flop 71 serves as an arrival tl~e de-tector 22; the time comparison signal S23 is fed to its preparatory input D and the zero passage signal S21 is fed to its stage input C. The leading edge of the two signals thereby serve as ti~e measurlng points. Depending on the phase position of these two leading edges, an early measured signal S24 occurs at the output ~ or the late measured signal S25 occurs at the output Q.
The early tracking signal S16 is fed through an inverter 72 and the late tracking signal S17 through an in-verter 73 to a respective incandescent diode 74 or 75, which have a common, current limiting resistor 76. When the arrival delay signal S14 tracks the trailing edge of an impulse of the rectangular signal S12, as is desired, the diodes 74 and 75 light up alternately.
FIGS 3 and 4 show various signals with respect to time. When the transm~ssion signal S43 (first line) is emitted, the transducer 3 produces an ultrasonic signal S3 which, after a transit time tz, is sensed by the transducer 4 and received as an electric ultrasonic signal S8. Simultaneously with emission of the transmission signal S43, the counter 39 starts to count the impulses S38 delivered by the oscillator 37.
After 256 or some other predetermined number of impulses, the reference signal S40 i8 delivered. This corresponds to an expected transit time te which decreases with rising frequency of the pulse train S38 and increases with falling frequency.
The expected transit time te is delayed until after the actual transit time tz in the regulating circuit of the apparatus so that the sonic velocity and flow velocity are accurately formed by the main signal S27 and auxiliary signal 105~4~1 S31, respectively. It wlll al80 be evident that the ultra-sonic signal S8 starts with a smaller amplitude, for which reason the initial portion of the slgnal ls not particularly useful for determinlng the actual transit time tz.
FIG. 4 first of all shows an enlarged representation of the ultrasonic slgnal S8. By means of rectlflcation one obtains the rectified signal S54 and by smoothing one obtains the enveloplng curve S49. In addltion, ampliflcation and clipping o~ the ultra~onlc signal S8 results in the rectangular 8 ignal S12.
The envelope curve S49 produces the output signal S56 in the ramp amplifier 55. m læ signal is compared with the constant threshold value S58. AR soon as the threshold value has been reached, the fllp-flop 60 is triggered and ; emits the arrival delay signal S14. The regulatlon carried out by the phase detector 15 and the regulatlng means 18 ensureR that the arrival delay time ta that is thus determined flnishes at the instant at which zero passage a occur~ with the tralling edge of the rectangular signal Sl2. If it is -;
; 20 determined in the phase detector 15 that the arrival delay time ta i8 too short, the output signal S56 ls displaced downwardly with the aid of the control voltage Sl9, whereby ~ the delay time tais lncreased. If the delay time ta is too -- long, the output signal S56 is raised, whereby the delay tlme is shortened. The next following positlve-golng zero cross-over b of the rectangular slgnal S12 ls determined in the zero crossover detector 20 which generates the zero crossover signal S21. With a finally regulated arrival delay time ta~ this occurs precisely half a perlod p/2 of the ultra-sonic ~ignal 8 after occurrence of the arrlval delay signal :
. .
105~491 S14. One thereby obtains a precisely defined delay time, even if commencement of the signal of the ultrasonic signal S8 cannot be very accurately determined.
The reference signal S40 is emitted at ~he expected instant of arrlval which, in the regulated condition, coincides with the actual instant of arrival. With the aid of the reference delag signal S69, a reference delay time tb is added in the reference delay means 44 and at the end of this the time comparison signal S23 appears. The leading edge of the zero crossover signal S21 is compared in phase with the leading edge of this time comparison signal S23 and appropriately evaluated as being early or late with respect thereto such that the time positions of the reference pulse may be ad~usted to track the zero crossover point.
The voltage controlled oscillator 37 may be of conventional design or alternatively may be an integrated circuit chip such as the ICL 8038 The frequency divider 39 may al80 be of conventional design or alternatively may be a series of discrete logic components such as integrated cir-cuits 7474. The element 46 may be a bistable element such as a flip-flop. The summing circuit 32 may be an operational amplifler such as a 301A with the input switching circuitry 33 being an integrated circuit elements CA 4016. The re-maining circuit elements are all described in greater detail in FIG. 2 and may be operational amplifiers. In particular, the amplifier 47 may be an integrated circuit component MC 1590, the amplifier 11 may be an integrated circuit such as MC 1414L, the amplifier 50 may be an inteKrated circuit such as 301A, the differential ramp circuit 55 may be the integrated circuit HA 2605, and the threshold detector 57 may _ 16 -:'' :',, : ~ . . - .
.. ....
lOS649~
be an integrated circuit MC 1414L, while the elements 60, 61, 65 and 71 may be logic elements of the 7400 series.
The NAND gates 62 and 63 may in like manner be of the 7400 ~er:ies, whereAs the amplifier 64 may be 301A, the monostable vib:rator 68 may be of the 7400 series and the flip-flop 70 may be of the 7400 series.
~' .' . . , :,
BACKGROUND OF THE INVENTION
This invention relates to app~ratus for determln-in~s the arrival time of alternating slgnals and, more particularly, to apparatus for determlning the arrival tlme of an ultrasonic signal.
From German Patent 2,322,749 and U. S. Patent 3,780,577 devices are known for the ultrasonic measurement of the flow velocity of fluent media and the sonic velocity in fluent media, in which ultrasonic signals are alternately transmitted upstream and downstream along a measuring path which is provided with two ultrasonic transducers and has at least one component extending in the flow direction. At the instant of transmission, the transducer on the transmission side ls momentarily energized and a time generator ls simultaneously actuated whlch dellvers a reference signal after the expected transit time. The time generator may include a voltage-controlled oscillator which i~ operated at a frequency fl during downstream measurement and with a frequency f2 during upstream mea~urement. A series-connected counter counts a predetermined number of output impulses after the instant of transmission. If the expected transit time is shorter than the actual transit time, the frequency of the oscillator is reduced by means of regulating circuit; if the expected transit time is longer than the actual transit time, the frequency of the oscillator is increased by means ; of the regulating circuit. By reason of this adaption, the oscillator frequencies correspond to the reciprocal values of the downstream and upstream transit times and can be ~valuated to obtain the flow velocity and the sonic velocity.
If the transducer on the transmission side in such an apparatus .,, ~
,~' ~ 0 5 is energized at the instant of transmis~lon, it will no~
lmmediately emlt the high frequency ultr~sonic signal9 which may for example have a fre~uency of 1 MHz, at maxlmum amplitude; the amplitude rather lncreases gradually. As a result, the end o~ the transit tlme, that is to say the commencement of the ultrasonic signal on the receiver side, can only be determined by the ~act that the transducer on the receiver slde receives an ultrasonlc osclllat10n which is only llttle different from zero. This does not permit accurate measurement. In the known cases, therefore, the actual instant of comparison has been delayed with reference to the commencement of the signal. This occurs on the re-ceiver side with the aid of arrival delay means by which the received ultrasonic signal i~ rectified, at least the first portion of the envelope of the rectified ultrasonlc signal i8 converted to a substantially llnear rising signal, and the latter is fed to a threshold value detector which, on reach-ing the threshold value, delivers an arrival delay signal that ~ is delayed relatively to the actual arrival. In a second 20 channel the received ultrasonic signal is amplified and clipped so that a rectangular signal of the same phase is obtained. The zero crossover of this rectangular signal wlth rising or positive-golng leading edge following the arrival delay signal is utilized as a corrected arrival signal.
Simultaneously, in the reference delay means a reference de-lay time was added at the instant of the actual reference ~ signal, the re~erence delay time being constant, as is the ;~ arrival delay time, but somewhat larger than same. At the end o~ this reference delay time a time comparison signal is delivered as a corrected reference signal which is compared , . . . .
lOS~:;491 with the aforementioned zero crossover. It iR immaterlal whether on the recelver side the commencement of the arrivlng ultrasonic signal is determined very accurately.
Thls 18 because a sllghtly retarded determination of the co~encement of the slgnal merely displaces the arrival de-lay time and thus the arrlval delay signal but not the selected zero crossover that i8 used for the measurement.
Thls results ln a very high measuring accuracy.
However, dlfflcultles arise when the commencement of the arrlving ultrasonlc slgnal is determined so late that the arrival delay signal appears immediately prior to the selected zero crossover. In that case lt can happen that the next zero crossover is instead used for the measurement and the measuring result iA in error. One was therefore compelled to u~e very accurately operatlng components on the receiver side for permitti~g determination of commencement of the slgnal as rapldly as possible, preferably stlll within the flrst half period.
The lnventlon is based on the ob~ect of providing - 20 an lmproved apparatus of the aforementloned klnd in whlch ;
accurate determination of the commencement time 18 possible without placing such high requlrements as hltherto on the accurate determination of the commencement of the arrivlng ultrasonlc signal.
SUMMARY OE THE INVENTION
This ob~ect is ~ul~illed in accordance wlth the invention by a phase detector which determines the phase position of the arrival delay signal with reference to a zero crossover of the trailing edge of one of the pulses in a pulse train derived from the received signal, and by ~OSf~491 regulating means which act on the arrival delay means andJ
in dependence on the phase position, change the arrival de-lay time in the sense of displacing the arrival delay signal tow~ards the last-mentioned zero crossover.
In thls construction, the arrlval delay time is no longer constant but variable. By a regulating circuit it is passed after the zero crossover of the pulse traln which precedes the zero crossover to be ~elected by half a period.
This ensures on the one hand that the arrival delay signal appears in sufficient time to enable the next zero crossover that serves for the measurement to be selected with cer-talnty and on the other hand that late determination of commencement of the signal is permissible within wider limit~
than hitherto because the arrival delay tlme is automQtlcally shortened correspondingly. Thls also permlts one to use simpler readlly available circuit elements because the regu-lating clrcuit compensates the errors caused thereby.
It is also advantageous lf the regulating means i also act on the reference delay means and change the reference delay time in the same sense as the arrival delay tlme. Thls enables further correctlons to be made automatically wlthout the need for recalibrating the instrument and ~nsures the ref-erence delay time coincides with the leading edge of the next positive-going signal followlng the zero cross~ng.
In an apparatus wherein in the arrlval delay means -; the received ultrasonic signal is rectified, at least the first portion of the envelope of the rectified ultrasonic signal is transformed to a substantially linear rising signal and the latter is fed to a threshold detector which .:
causes the arrival delay signal to be emitted when the ' 105~:i491 threshold value ls reached, lt is preferred that the phase detector deliver e~rly slgnals when the arrival delay slgnal arrives too early and late signals when it arrives too late, that the early signals of one slgn and the late slgnals of opposlte sign can be fed to an lntegrator, and that a control voltage derivable at the output of the integrator serves to change the arrival delay time. When the phase posltion of the arrival delay slgnal coincides accurately wlth the zero croæsover of the other polarity, early and late signals occur alternately so that the integrator dellvers a constant control voltage. If the early æignalæ or the late signals predominate, the control voltage decreases or rises, respectlvely.
In particular, the phase detector can co~prlse a r~fllp-flop of which the preparatory or data input has the pulse traln fed to lt, the stage or clock input haæ the arrlval delay signal fed to lt, one output delivers the early 8 lgnals and the other output delivers the late signals.
It is of particular advantage if the control volt-age is feedable to the one input and the envelope to the other input of a differential amplifier producing the linesr rising slgnal. If the difference between the control voltage and the envelope increaæes, the threshold value is reached earlier and if the difference decreases the threshold value is reached later. The control voltage could instead exert in~luence in a different manner, for example by altering the threshold value itself.
In a preferred embodiment the reference delay means include a monostable multi-vibrator which is triggered by the reference signal and which compriseæ an RC element determining the trigger period, the condenser charglng voltage of the RC
~05~4~ :
element being governed by the control voltage, and also in-clude a fllp-~lop whlch is resettable after each measurement and which is set by the multi-vlbrator at the end o~ each trlgger perlod and thcn dellvers the time comparison signal.
The leading edge of the time comparison signal serves ror the accurate determinatlon of the end of the referenee delay time. It iB a permanent binary signal which terminates only on resetting.
Further~ on reaching the threshold value, the threshold generator may del~ver a threshold signal which sets a fllp-flop that is resettable after each measurement and delivers the arrival delay signal. The arrival delay signal is therefore also a permanent binary slgnal which terminates only upon re~etting the flip-~lop and the leading edge of which accurately indicates the end o~ the arrival delay time.
e zero cross-over detector pre~erably comprise a D-~lip-flop which 18 resettable after each measurement, has the arrlval delay signal fcd to its preparatory input and the rectangular 8 lgnal to lts stage input and delivers the zero passage slenal at one output. The zero pa~sage 8ignal is therefore a permanent blnary signal which terminates on resetting the flip-flop and the leadlng edge o~ which , ... .
accurately glves the lnstant o~ the zero passage.
In an advantageous embodiment, the arrival ti~e detector comprises a D-flip-flop ~hich has the time comparison ~, sig~al fed to it~ preparatory input and the zero pa~sage signal ~ed to its stage input, and delivers an early measured :`
signal at its one output and a late measured signal at its other output depending on whether the zero crossover signal occurs before or a~ter the time comparison signal. m e early ~, !, ~056~91 or late measured signals can than be evaluated in the usual way for measuring and indicatlng purposes, for example to ada]pt the frequency of the time generator oscillator to the actual transit tlme.
Further, indicatlng means may be provided comprising two incandescent diodes each energized by an inverter con-trolled by the early or late slgnals, respectively. On correct functioning of the regulating circuit, these incan-descent diodes should light up alternately.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in more detail with reference to the example shown in the drawing, wherein:
Figure 1 is a block circuit diagram of an ultrasonic measuring apparatus comprising the apparatus according to the inventlon;
Figure 2 is a simplifled repreRentation of the cir-cuitry of one embodiment of the apparatus;
Figure 3 shows the time course of the transmission signal, ultrasonic signals, counting slgnals and reference signal, and Figure 4 shows the time course of various signals occurring in the apparatus.
According to FIG. 1, a channel 1 contains an ultra-sonic measuring path 2 which is limited by two ultrasonic transducers 3 and 4 and diæposed obliquely to the flow direc-tion 5 of the medium flowing through the channel 1. Trans-mission means 6 deliver an energizing signal S7 to the trans-ducer 3 through the line 7, the transducers thereupon deliver-ing an ultrasonic signal at the transducer's resonant fre-quency, for example 1 MHz through the medium in the channel 1.
lOS~;4~
At the end of the transit time, this signal is received by the tranRducer 4 and converted to an electrlc ul*rasonic signal S8 which i~ ~ed through a line 8 to receiver means 9.
m e llnes 7 and 8 are interchangcable by a swi~ch 10 80 that the transducers 3 and 4 can alternately serve aR ultrasonic transmltter and as ultrasonic receiver. In the recelving ~eans the ultrasonic signal S8 is ampllfled and then pro-cessed ~urther in two channels.
m e first channel comprises an amplifier 11, in the output line 12 Or which there occurs a rectangular signal or pulse train S12 having the frequency of the ultrasonic signal S8. In the second channel there are arrival delay means 13, at the output 14 of which an arrival delay signal S14 occurs at the end of an arrival delay time. In a phase detector 15 the arrival delay signal S14 is compared with the ad~oining traillng edge Or an impulse of the rectangular signal S12.
The phase detector emlts early signals S16 or late signals S17 depending on whether the arrival delay signal S14 occurred earlier or later than the trailing edge of the impulse of the rectangular Rignal S12. Regulating means 18 are controlled in dependence on this, the regulating means delivering an output signal Sl9 to the arrival delay means 13 so that the arrival delay time ls shortened or extended until the arrival delay signal S14 accurately coincides with the trailing edge.
This determines a defined zero pas5age with the trailing edge of thc rectangular sig~al S12.
;The arrival delay signal S14 is further fed to zero ;~;cross-over detector 20 which are also fed by the rectangular slgnal S12. A zero cro~sover signal S21 occurs at the output 21 when the first rising flank or leading edge of the .:
-. - g _ , ' '' ~`'' : , . . . . . . ... .
rectangular 8 ignal S12 appears after occurrence o~ the arrival delay signal S14. Thls determines a deflned zero passage.
The zero passage signal S21 is compared with a time comparison ~lgnal S23 ln an arrival tlme detector 22. An early measured signal S24 is cmitted lf the zero passage signal S21 occur~ earlier than the time comparison signal S23 and a late measured signal S25 is emitted if it occurs later. As will be evident from the Applicant~' copending appllcation No. 257 785 flled July 26J 1976 entitled "Apparatus for the ultra~onic measurement of the flow velocity of fluent media", integration of all early measured signals of one sign and all late mea~ured signals of the opposite sign ln a voltage level generator 26 can give a main signal S27 which is a direct measurement for the sonlc velocity c. In a sccond signal level generator 28 the early and latç mea6urcd signal~ are evaluated wlth regard to the up~tream signals S29 and downstream signals S30 which indicate the transmission direction. By lntegrating all downstream early measured signals of one sign and all upstream early measured signals o~ the opposite sign, an auxiliary sienal S31 is obtained which is a measurement for the flow velocity v. The late m~asured signals or the early and late measured signals can be processed in a similar manner.
The main slgnal S27 is fed directly to a summing circuit 32 but the auxiliary signal S31 is fed with alter-nately positive and negative sign through a switch 33 which is dependent on the transmission direction. Consequently control signals S35 and S36 occur alternately at the output of the sum~ing circuit, the control signals -ln~luencing a ~ voltage-controlled oscillator 37 in such a way that it - 30 delivers at its output 38 train~ of impulses S38 with a ,~
,~
105~i45~1 frequency fl on downstream measurement and a lower frequency f2 on upstream measurement. These trains of impulses are fed to a counter 39 which, after counting 256 impulses by way of example, delivers a reference signal S40, a resetting signal S41 a little later, then a transmission direction changing signal S42 and, simultaneously with commencement of counting, a transmission signal S43 to the transmission means 6. The reference signal S40 is fed to reference delay means 44 in which, on arrival of the reference signal S40, a reference delay time is started; at the end of the reference delay time the time comparison signal S23 is emitted. In addition, the control signal Sl9 is fed through the input 45 and with the aid of this the reference delay time is variable. The trans-mis810n directlon changing signal S42 is fed to a direction generator 46 which switches over the switches 10 and 33 and feeds the corresponding downstream and upstream signals to the - signal level generator 28.
FIG. 2 3hows an embodiment for the equipment 9, 11, 13J 15, 18, 20, 22 and 44 of FIG. 1. The receiver means 9 comprises in the final stage an amplifier 47 of which the in-verting input has the electric ultrasonic signal S8 fed to it.
In this amplifier, the gain can be regulated. By means of a circuit (not shown), regulation is effected by applying a regulating voltage to a terminal 48 in such a way that the amplitude of an envelope curve signal S49 occurring at the output 49 of an amplifier 50 remains constant. The output of this amplifier 47 can have interfering frequencies, which do not correspond to the ultrasonic frequency, removed from it by an LC filter circuit 51. m e signal values thus obtained are so amplified and clipped in the amplifier 11 that the ':
~0564~
rectangular signal S12 appears in the line 12. The ~mplified ultrasonic signal is additionally fed to two field effect transistors 52 and 53 for the purpose of full wave rectifica-tion so that a rectified ultrasonic signal S54 appears at their output 54. This rectified signal is smoothed in the amplifier 50, which serves as low-pass filter, so that the envelope curve S49 appears at the output 59.
The envelope S49 is fed to a differentiator 55 (which in a preferred embodiment may be a ramp amplifier whose slew rate is limited). The differentiator delivers a signal S56 at its output 56 with a constant slope determined by the slew rate of ramp amplifier as long as the rise time of the input envelope S49 exceeds the slew rate of the amplifier.
This output signal S56 is compared in a threshold value de-tector 57 with a fixed threshold value supplied through the input 58 by a voltage divider 58'. On reaching this threshold value, a signal S59 is applied to the clock input C of a D-flip-~lop 60 which is set to emit the arrival delay signal S14 at its output Q until resetting is effected by the re-~0 setting signal S41.
The arrival delay signal S14 is fed to the stage orclock input of a D-flip-flop 61, of which the preparatory in-put D is fed with the rectangular signal S12. Consequently, early signal S16 appears at the output Q or late 8 ignal S17 at the output Q, which are gated with the arrival delay signal ~ S14 in NAND elements 62 or 63 and therefore can be fed to an integrator 64 as impulses of substantially constant charge.
The early signals are fed to the inverting and the late signals to the non-inverting input of the integrator 64. If the arrival delay signal S14 does not accurately coincide with ..
.~
105f~49~
the trailing edge of an impulse of the rectangular signal S12, the number of early or late slgnals predominates and the size of the control voltage Sl9 changes at the output of the integrator 64. This output voltage is fed to the non-inverting input of the ramp amplifier 55, as a result of ~hlch the output voltage S56 is displaced upwardly or downwardly parallel to ltself. Thls changes the point of lntersectlon with the threshold value and thus the instant of the threshold value signal S59 and of the arrival delay signal S14 until the last-mentioned signal again coincides with the falling flank of the rectangular slgnal S12.
The thus regulated arrival delay signal S14 is fed to the preparatory input D of the D-flip-flop 65 serving as zero crossover detector to the stage input C of which the rectangular signal S12 is fed. Consequently, during the next zero crossover, i.e. at the leading edge of the next lmpulse in the rectangular signal S12, the zero crossover signal S21 occurs at the output Q and remain~ until the out-put condition of the flip-flop 65 is reset by the resetting signal S41.
The control voltage Sl9 acts through a voltage divider 66 on an RC element 67 of a monostable multi-vibrator 68 which is triggered by the re~erence signal S40 and, after a period determined by the RC element 67, returns to its orlglnal state. During the triggered period, which also ~erves as a reference delay time, a signal S69 occurs at the output Q of the multi-vibrator 68. This slgnal is fed to the setting input C of a further flip-flop 70 whLch then emits ~; the time comparison signal S23 at its output Q until reset by the resetting signal S41.
. ,'~
'~
~OSf~491 A D-~lip-flop 71 serves as an arrival tl~e de-tector 22; the time comparison signal S23 is fed to its preparatory input D and the zero passage signal S21 is fed to its stage input C. The leading edge of the two signals thereby serve as ti~e measurlng points. Depending on the phase position of these two leading edges, an early measured signal S24 occurs at the output ~ or the late measured signal S25 occurs at the output Q.
The early tracking signal S16 is fed through an inverter 72 and the late tracking signal S17 through an in-verter 73 to a respective incandescent diode 74 or 75, which have a common, current limiting resistor 76. When the arrival delay signal S14 tracks the trailing edge of an impulse of the rectangular signal S12, as is desired, the diodes 74 and 75 light up alternately.
FIGS 3 and 4 show various signals with respect to time. When the transm~ssion signal S43 (first line) is emitted, the transducer 3 produces an ultrasonic signal S3 which, after a transit time tz, is sensed by the transducer 4 and received as an electric ultrasonic signal S8. Simultaneously with emission of the transmission signal S43, the counter 39 starts to count the impulses S38 delivered by the oscillator 37.
After 256 or some other predetermined number of impulses, the reference signal S40 i8 delivered. This corresponds to an expected transit time te which decreases with rising frequency of the pulse train S38 and increases with falling frequency.
The expected transit time te is delayed until after the actual transit time tz in the regulating circuit of the apparatus so that the sonic velocity and flow velocity are accurately formed by the main signal S27 and auxiliary signal 105~4~1 S31, respectively. It wlll al80 be evident that the ultra-sonic signal S8 starts with a smaller amplitude, for which reason the initial portion of the slgnal ls not particularly useful for determinlng the actual transit time tz.
FIG. 4 first of all shows an enlarged representation of the ultrasonic slgnal S8. By means of rectlflcation one obtains the rectified signal S54 and by smoothing one obtains the enveloplng curve S49. In addltion, ampliflcation and clipping o~ the ultra~onlc signal S8 results in the rectangular 8 ignal S12.
The envelope curve S49 produces the output signal S56 in the ramp amplifier 55. m læ signal is compared with the constant threshold value S58. AR soon as the threshold value has been reached, the fllp-flop 60 is triggered and ; emits the arrival delay signal S14. The regulatlon carried out by the phase detector 15 and the regulatlng means 18 ensureR that the arrival delay time ta that is thus determined flnishes at the instant at which zero passage a occur~ with the tralling edge of the rectangular signal Sl2. If it is -;
; 20 determined in the phase detector 15 that the arrival delay time ta i8 too short, the output signal S56 ls displaced downwardly with the aid of the control voltage Sl9, whereby ~ the delay time tais lncreased. If the delay time ta is too -- long, the output signal S56 is raised, whereby the delay tlme is shortened. The next following positlve-golng zero cross-over b of the rectangular slgnal S12 ls determined in the zero crossover detector 20 which generates the zero crossover signal S21. With a finally regulated arrival delay time ta~ this occurs precisely half a perlod p/2 of the ultra-sonic ~ignal 8 after occurrence of the arrlval delay signal :
. .
105~491 S14. One thereby obtains a precisely defined delay time, even if commencement of the signal of the ultrasonic signal S8 cannot be very accurately determined.
The reference signal S40 is emitted at ~he expected instant of arrlval which, in the regulated condition, coincides with the actual instant of arrival. With the aid of the reference delag signal S69, a reference delay time tb is added in the reference delay means 44 and at the end of this the time comparison signal S23 appears. The leading edge of the zero crossover signal S21 is compared in phase with the leading edge of this time comparison signal S23 and appropriately evaluated as being early or late with respect thereto such that the time positions of the reference pulse may be ad~usted to track the zero crossover point.
The voltage controlled oscillator 37 may be of conventional design or alternatively may be an integrated circuit chip such as the ICL 8038 The frequency divider 39 may al80 be of conventional design or alternatively may be a series of discrete logic components such as integrated cir-cuits 7474. The element 46 may be a bistable element such as a flip-flop. The summing circuit 32 may be an operational amplifler such as a 301A with the input switching circuitry 33 being an integrated circuit elements CA 4016. The re-maining circuit elements are all described in greater detail in FIG. 2 and may be operational amplifiers. In particular, the amplifier 47 may be an integrated circuit component MC 1590, the amplifier 11 may be an integrated circuit such as MC 1414L, the amplifier 50 may be an inteKrated circuit such as 301A, the differential ramp circuit 55 may be the integrated circuit HA 2605, and the threshold detector 57 may _ 16 -:'' :',, : ~ . . - .
.. ....
lOS649~
be an integrated circuit MC 1414L, while the elements 60, 61, 65 and 71 may be logic elements of the 7400 series.
The NAND gates 62 and 63 may in like manner be of the 7400 ~er:ies, whereAs the amplifier 64 may be 301A, the monostable vib:rator 68 may be of the 7400 series and the flip-flop 70 may be of the 7400 series.
~' .' . . , :,
Claims (15)
1. Apparatus for ascertaining the time of arrival of an alternating signal comprising:
arrival delay means responsive to the commence-ment of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, timing means for generating a reference signal corresponding to the expected time of arrival of said alternating signal, and a time of arrival detector responsive to said reference signal and to said time signal for ascertaining said time of arrival and controlling said timing means in accordance therewith, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjusting the timing of said arrival delay signal to correlate in time with said second sense zero crossing, whereby said arrival delay signal always immediately precedes said first zero crossing.
arrival delay means responsive to the commence-ment of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, timing means for generating a reference signal corresponding to the expected time of arrival of said alternating signal, and a time of arrival detector responsive to said reference signal and to said time signal for ascertaining said time of arrival and controlling said timing means in accordance therewith, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjusting the timing of said arrival delay signal to correlate in time with said second sense zero crossing, whereby said arrival delay signal always immediately precedes said first zero crossing.
2. Apparatus according to Claim 1 wherein said regulating means also varies the timing of said reference signal in the same sense as the arrival delay signal.
3. Apparatus according to Claim 2 wherein said regulating means includes a phase detector which compares the phase of said arrival delay signal with that of said second sense zero crossings to provide early signals in one polarity when the arrival delay signal arrives too early and late signals of another polarity opposite said one polarity when the arrival delay signal arrives too late, and an integrator responsive to said early and late signals for providing a control signal for adjusting said arrival delay signal timing.
4. Apparatus according to Claim 1 wherein said regulating means includes a phase detector which compares the phase of said arrival delay signal with that of said second sense zero crossings to provide early signals in one polarity when the arrival delay signal arrives too early and late signals of another polarity opposite said one polarity when the arrival delay signal arrives too late, and an integrator responsive to said early and late signals for providing a control signal for adjusting said arrival delay signal timing.
5. The apparatus according to Claim 4 which also includes means for rectifying the received alternating signal, means for converting the rectified signal into a substantially linear rising signal, a threshold detector for ascertaining when said rising signal achieves a predetermined threshold value ther-by to generate said arrival delay signal.
6. The apparatus according to Claim 5 wherein said phase detector comprises a D-flip-flop having a preparatory input connected to receive said alternating signals and a stage input connected to receive said arrival delay signal, said flip-flop having one output adapted to provide said early signals and the other output adapted to provide said late signals.
7. Apparatus according to Claim 6 which includes a differential amplifier having one input connected to re-ceive said control input voltage control signal and the other output connected to receive said envelope signal thereby to provide said linear rising signal.
8. Apparatus according to Claim 3 wherein said reference delay means includes a monostable multi-vibrator adapted to be triggered by said reference signal and which includes a RC element which controls its trigger, and said control means being connected to vary the charging voltage of said RC element thereby to vary said trigger.
9. Apparatus according to Claim 5 wherein said zero crossover detected comprises a D-flip-flop which is resettable after each measurement J and includes a prepara-tory input connected to receive said arrival delay signal and a stage input connected to receive said alternating signals and output adapted to provide for generating said time signals.
10. Apparatus according to Claim 9 which includes a second flip-flop connected to receive said arrival delay signal and to store the same, said flip-flop being resettable after each measurement.
11. Apparatus according to Claim 10 wherein said zero crossover detector includes a D-flip-flop which is resettable after each measurement, and has a preparatory input connected to receive said arrival delay signal and a stage input connected to receive said alternating signals and an output for providing said time signal.
12, Apparatus according to Claim 10 wherein said time of arrival detector includes a D-flip-flop having a preparatory input connected to receive said delay reference signal in a stage input connected to receive said time signal and a pair of output adapted to provide said early signal at one output and a late signal at its other output depending on whether the time signal occurs before or after said delay reference signal.
13. Apparatus according to Claim 10 which also includes an indicating means comprising two incandescent diodes each energized by an invertor controlled by the early or late signals respectively.
14. Apparatus for ascertaining the time of arrival of an alternating signal comprising:
arrival delay means responsive to the commencement of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, timing means for generating a reference signal corresponding to the expected time of arrival of said alternating signal, and a time of arrival detector responsive to said reference signal and to said time signal for ascertaining said time of arrival and controlling said timing means in accordance therewith, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjust-ing the timing of said reference signal to correlate in time with said first sense zero crossing.
arrival delay means responsive to the commencement of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, timing means for generating a reference signal corresponding to the expected time of arrival of said alternating signal, and a time of arrival detector responsive to said reference signal and to said time signal for ascertaining said time of arrival and controlling said timing means in accordance therewith, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjust-ing the timing of said reference signal to correlate in time with said first sense zero crossing.
15. Apparatus for ascertaining the time of arrival of an alternating signal comprising:
arrival delay means responsive to the commencement of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjust-ing the timing of said arrival delay signal to correlate in time with said second sense zero crossing, whereby said arrival delay signal always immediately precedes said first zero crossing.
arrival delay means responsive to the commencement of said signal for generating an arrival delay signal, a zero crossover detector responsive to the zero crossing of said alternating signal in a first sense after said delay signal for generating a time signal, regulating means responsive to said arrival delay signal and to the preceding zero crossing of said alternating signal in a second sense opposite said first sense for adjust-ing the timing of said arrival delay signal to correlate in time with said second sense zero crossing, whereby said arrival delay signal always immediately precedes said first zero crossing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA257,742A CA1056491A (en) | 1976-07-26 | 1976-07-26 | Apparatus for determining the arrival time of alternating signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA257,742A CA1056491A (en) | 1976-07-26 | 1976-07-26 | Apparatus for determining the arrival time of alternating signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1056491A true CA1056491A (en) | 1979-06-12 |
Family
ID=4106504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA257,742A Expired CA1056491A (en) | 1976-07-26 | 1976-07-26 | Apparatus for determining the arrival time of alternating signals |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1056491A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109584546A (en) * | 2018-07-04 | 2019-04-05 | 东南大学 | It is a kind of quickly-regular public traffic shares lane and dispatches a car the determination method of flow threshold |
-
1976
- 1976-07-26 CA CA257,742A patent/CA1056491A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109584546A (en) * | 2018-07-04 | 2019-04-05 | 东南大学 | It is a kind of quickly-regular public traffic shares lane and dispatches a car the determination method of flow threshold |
| CN109584546B (en) * | 2018-07-04 | 2021-06-01 | 东南大学 | Method for determining departure flow threshold of quick-conventional bus sharing lane |
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