CA1051122A - Power transistor having improved second breakdown capability - Google Patents
Power transistor having improved second breakdown capabilityInfo
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- CA1051122A CA1051122A CA267,943A CA267943A CA1051122A CA 1051122 A CA1051122 A CA 1051122A CA 267943 A CA267943 A CA 267943A CA 1051122 A CA1051122 A CA 1051122A
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- emitter
- base
- portions
- finger
- power transistor
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Abstract
POWER TRANSISTOR HAVING IMPROVED
SECOND BREAKDOWN CAPABILITY
Abstract of the Disclosure A high voltage power transistor of the type that includes emitter, base and collector regions of alternate conductivity types and PN junctions at the interface of the emitter and base regions, and at the interface of the base and collector regions. The improvement being an emitter region having at least a plurality of spaced elongated finger-like portions;
a means in the base region to lower the base resistance in the transverse direction, this means located centrally beneath the finger-like portions of the emitter and comprised either of regions of low resistivity located centrally and beneath each of the finger-like portions, or regions of increased base thickness in the vertical direction also located centrally beneath each of the finger-like portions of the emitter.
SECOND BREAKDOWN CAPABILITY
Abstract of the Disclosure A high voltage power transistor of the type that includes emitter, base and collector regions of alternate conductivity types and PN junctions at the interface of the emitter and base regions, and at the interface of the base and collector regions. The improvement being an emitter region having at least a plurality of spaced elongated finger-like portions;
a means in the base region to lower the base resistance in the transverse direction, this means located centrally beneath the finger-like portions of the emitter and comprised either of regions of low resistivity located centrally and beneath each of the finger-like portions, or regions of increased base thickness in the vertical direction also located centrally beneath each of the finger-like portions of the emitter.
Description
19 ~ackground_of the Inventlon The present invention relates to tran5istors 21 required to handle relatively large amounts of power, 22 More particularly, the invention relaLes to a high 23 voltage power transistor in which the second breakdown 24 capability is increased, .
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1 High power transistors usua11y include an emitter region havin~ a relatively large area so that the rower ;s distr;buted over the device to keep the power per unit area within safe limits.
It has previously been found that in a power transistor having a relatively large area emitter, injection of emitter current occurs mainly along the periphery of the emitter. To minimi~e this "current crowding", it has become the practice to define the emitter region so that it has as large a per-iphery as possible in relation to area.
A number of different con~igurations have been adapted to secure relatively large emitter periphery. One of these is an emitter that has a star shape or similar shapes which include a plurality of con-~olutions extending radially outwardly from a hub portion. Another is a multiplicity of separate emitter sites all connected in parallel to function as a composite emitter. A more prevalent configuration i5 one in which the base region and the emitter region are generally of comb-shape with a web portion and interdigitated fingers. The emitter may be a double comb with web portions back to back.
The use of such configurations as described above has greatly 2Q improved the effective use of emitter area. However, in general, when tbe transistor is "on", some current crowding occurs near the emitter periphery.
- , DLM/Tl ~ `
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~L~35~ 2 1 On the other hand, when the transistor is turned from the l'on"
cond;tion to the "off" condit;on, part;cularly when used with a high inductive load, the e~itter-collector current crowdi~g occurs near the center of the emitter fingers and the web. The direc-tion of the base current is the reverse of each other in these aforedescribed cases and the voltage drop caused by the transYerSe base current flowing throu~h the base resistance would be respon-sible for current crowding at the stated transistor regions. A
transistor can become destroyed by the second breakdown when the current density exceeds a certain limit while the collector-to-emitter voltage also is relatively high.
ObJect of the Invention An object of the present invention is to provide an improved power transistor having elongated emitter fingers that has ;mproved second breakdown capability.
A further object of this invention is to provide an improved power transistor having elongated em;tter port;ons wherein the base reg;on underlying the elGngated port;ons (fingers) and the web por-tion has a lower resistance which operates to increase the second breakdo~n capability.
Summary of the Invention The present invention comprises a power transîstor of the type that includes emitter, base and FI~-75-053 3 _ ~L~ L~LZ 2 1 collector regions of alternate conductivity types, and PN ~unctions at the interface of the emitter and base regions, and the interface of the base and collector regions, the improvement being an emitter reaion having at least a plurality of elongated finger portions which materially increases the emitter periphery-to-area ratio~ and a means in the base region underlying the finger portions of the emitter to lower the base resistance, in the transverse direction, under the central regions of the emitter finger porticns, this lower base resistance operating to increase the second breakdown capability of the transistor.
Brief Description of the Drawings FIGURE 1 is a perspecti~e view in broken sect;on illustrating a .
preferred specific embodiment of the power transistor of the inven-tion.
FIGURE 2 is an elevational view in broken section showing the internal structure of an embodiment of the invention.
FIGURE 2A is an impurity concentration profile taken on line 2A
in FIGURE 2 of a preferred specific embodiment of the invention.
FIGURE 3 is an elevational view in broken section illustrating another preferred specific embodiment of the invention.
' FI~-75-053 4 _ ~i "..~, ~5~1ZZ
1 FIGURE 3A is an impurity profile taken on line 3A of FIGURE
3 that depicts the impurity concentrations in the varicus regions oF the device of FIGURE 3.
Description of the Preferred Embodiments A typical power transistor constructed in accordance with the present invention has an emitter region 12, a base region 14, a lightly doped collector region 16, and a heavily doped collector region 18. Regions 12, 14 and 16 have alternate conductivity types as for example PNP or NPN, as is well known in the art. Guard rings 20 can be provided, if necessary or desirable, for increasing the base-collector breakdown voltage. The power transistor 10 of the invention is generally a discrete transistor although if desired it may be incorporated in a body alon~ with other transistors or elec-tronic elements. The current capability of a bi-polar transistor of the type illustrated in FIGURE 1 is directly related to the effec-tive emitter area. In a switching application of a conventional struc-ture without a finger-like configuration, when used For high voltage, high current capability3 only a very small portion of emitter area i~ effective. This is the result of current crowding which occurs ~.
near the emitter periphery during the "on" condition. ~As is known in the art, the base current which flows transversely in the active ba~e area causes the portion of the emitter-base junction near the emitter F19-75-Q53 - 5 _ . ~ .
~as~22 1 periphery to be more forward-biased than the portions near the center of the emitter. Consequently, the current flowing from the emitter toward the collector will flow in the emitter-base junc-tion regions that are more forward-biased, namely along the edges.
One well known way of improving the current capability of a transis-tor is to increase the periphery of the emitter. This can be ac-complished quite effectively by designing the emitter into a comb-like configuration having elongated fingers extending from a central web. This emitter configuration is illustrated in FIGURE 1. This emitter configuration reduces the transverse voltage drap across the base resistance underneath each emitter finger and the web portion and therefore reduces current crowding. The effective emitter area thus theoretically approaches the actual emitter area. The improve-ment in current capability provided by this configuration ls actually somewhat limited, however, since the introduction of a large number of narrow emitter fingers means that a considerable portion of the transistor chip area is wastefully occupied by the bàse fingers. Thus, for a given transistor chip area, the emitter area is reduced once again limiting thereby the current capability of the transistor. In view of the foregoing conditions, a structure compris;ng an optimum number of emitter fingers, each with an optimum width7 is needed which will maximize . . .
Fl9-75-053 ~Sl~Z~: ~
1 the effective emitter area for a given transistor area. However, when the width of the emitter fingers is optimally designed large enough so as to maximize the effective emitter area, another impor- ;
tant problem re~ains viz., the high likelihood of cecond breakdown when the transistor is turned "off", particularly when coupled to an induct;ve load. When the transistor is turned "off", the center portion of the emitter-base junction becomes, during transition ~rom "on" to "off", more fsrward-biased than the edge portion. The directicn of the base current is reversed when the transistor is 1~ turned off. In traversing the base region, this reverse base current creates a voltage drop whichg in turn, forms the aforementioned difference in emitter-base junction bias. As a consequence, the emitter-to-collector current in the transistor is now concentrated at the center portion of the fingers and web of the emitter. The poten-tial is large for destroying the transistor during the switching transition from "on" to "off" due to the simultaneous presence of the high current density at the center of emitter fingers and the web and the relatiYely high voltage imposed across the emitter and col-lector, especially when an inductive load is coupled to the transistor.
In this invention, a structure is provided which lowers the base resistance near the central regions under FI.9-75-Q53 - 7 -DLMlT6 ~LO S~L~L~2 1 the emitter fingers and web. This results in a more even distribution of current from the emitter to the collector during the switching transition from "on" to "off", since a greater portion of the emitter fingers and web is used for current flow. A first embodiment of the power transistor of the invention for achieving the decreased base resistance near the cent,ral regions under the emitter fingers and web is illustrated in FIGURES 1 and 2. A region 22 of a sheet resistance lower than the intrinsic base region 11 is provided which is located centrally and beneath each of the finger-like portions and the web portion of the .
emitter 12. The region 22 is doped with the same type of impurity as ~ ' intrinsic base region 11. In practice, the entire base region 14 embodi-es the same type oF impurity. In general, the sheet resistance of intrinsic or dumbell portion 11 of base region 14 exceeds the sheet resistance of region 22 of low resistivity by a factor in the range of 4 to 10. The impurity concentration in the various regions of the device is shown in impurity profile in FIGURE 2A. Profile 13 depicts the im- , purjt~y concentration of the emitter 12; profile 15 depicts the impurity :
concentration of region 22, and profile 17 of the base region 14. The .
concentration of the N- portion 16 of the collector and the N~ portion 18 of the collector is indicated by profile 24. In general, the thick- ,"
ness of emitter 12 is in the range FI~-75-053 - 8 -~L~)5~2~
1 o~ 4 to 12 microns, more preferabl~ 9 to ll microns. The surface concentration of the emitter is in the range of 2 x lOl9 to l x 102l, more preferably 6 x lOl9 to 2 x 102 atoms/cc. A typical emitter finger will be from 2 to lO mils in width with a length of 20 to 50 mils, more preferably with a width from 3 to 5 mils and a length of 30 to 40 mils. The extrinsic portion of base region 14 will have a thick-ness in the range of 8 to 25 microns, more preferably from 18 to 22 microns. The surface concentration of the base region 14 is in the range of 5 x 1017 to 1 x lOl9, more preferably l x 10l8 to 4 x 1018 atoms/cc. The N- portion 16 of the collector has a thickness in the range of 30 to 120 microns, more preferably 60 to 100 microns. The concentration in the N- collector region 16 which is preferably an epitaxial layer is in the range of I x 1014 to l x 1015 atoms/cc (with a resistivity in the range of 50 to 4 ohm cm., respectively), more preferably with an impurity concentration on the order of 1.5 x 1014 atoms/cc with a sheet resistivity on the order of 30 ohm cm. The N+
portion 18 of the collector has a thickness from 8 to 24 mils with an impurity concentration in the range of 5 x 1018 to l x 102 atoms/cc with a resistivity in the range of 0.01 to 0.001 ohm cm. More pre-~erably, the N+ portion 18 of the collector has a thickness in therange of 16 to 18 mils, with a concentration in the range of 2 x lOl9 to 4 x lOl9 atoms/cc and a resistivity on the order of FI9-75-053 ~ _ DL~/T8 10511~Z
1 .002 ohm cm. ~hen the transistor is a discrete device, the chip size will normally range from 120 by 120 mils square to 300 by 300 mils square, more preferably 180 mils by 180 mils to 240 by 240 mils square. The crystalline orientation of the device can be any suit able type as for example the ~ 100 7 or ';111~ orientation as de-fined by the Miller Indices. Power transistors utilizing the struc-ture of this invention are normally designed to have an amperage capa-city of 1 to 30 amps, more preferably 8 to 15 amps, and handle voltages in the range of 100 to 1200 volts, more preferably 300~to 700 volts.
The current gain-bandwidth frequency fT will be in the range of 0.5 to 50 MHz, more preferably 1 to 10 MHz. The ratio oF the width of the emitter finger 12 to the width of the base region 22 of low resis-tivity is preferably in the range of 3 to 5, more preferably on the order of 4.
Referring now to FIGURES 3 and 3A, there is depicted another pre-ferred specific embodiment of the power transistor of the invention.
In this embodiment, the intrinsic base region is increased in thick-ness below the center portion of emitter fingers and also the web portion. As indicated, below the center portion of emitter 12, there ~o is provided a depressed PN junction between the collector region and the base region. The ratio of the ~idth of the emitter finger 12 to the width of the base region 26 is in the range of 3 to 5, more DLMlT9 ~ O S ~ ~ 2 Z
1 preferably on the order of ~. In FIGURE 3A, there is depicted the various impurity concentrations of the regions of the device shown in FIGURE 3. Profile 27 indicates the impurity concentration of the region 26 wherein the thickness of the intrinsic base region 11 is increased beneath emitter finyers 12. By virtue of the profile 27, the resistance of the intrinsic base in the transverse direction is decreased beneath the central regions of the finger-like portions and the web portion of the emitter. This effectively reduces the cur-rent crowding in the central regions of the finger-like portions and the web portions of the em;tter 12 during the interval that the transistor is switched from "on" to the "off" condition. The ratio of the distance from the lower side of emitter to the lowest point of the base, which includes region 26, to the thickness of the in-trinsic base 11 jR. the distance bet~een the emitter and the flat PN
junction interface between the base and collector is in the range of 1.5 to 2, more preferably on the order of 1.8. The various impurity concentrations and other ratios of the embodiment of FIGURE 3 are similar to that disclosed with respect to the embodiment of FIGURE 2.
As is conventional, a passivating layer 28 of SiO2 or other dielectric materials or combinations is provided on the surface of the device, and openings made to contact the various regions of the device. As il-lustrated in FTGURES 2 and 3~ emitter DLMlTl O
.. . .
1 metallurgy fingers 30 make ohmic contact to emitter fingers 12 and base contacts 32 make contact to the base region 14. Contact is made to the N+ collector region 18 by providing a metal layer 34 on the underside of the device.
The devices of the invention as shown in FIGURES 1 and 2 can be fabricated by any suitable technique. In general, the starting material is a ~ 100 ~ silicon wafer doped with an N+ impurity having a resistivity of 0.002 ohm cm. An epitaxial silicon layer is then grown on the N~ wafer, with a thickness on the order of 100 microns -doped with an N- impurity with a resistivity on the order of 30 ohm cm. The surface of the epitaxial layer is then oxidized to form ap-proximately 5,000 Angstroms of silicon dioxide. The oxide layer is then etched, using photolithographic and subtractive etching techniques to define the base region 14. A P-type impurity is dif-fused through the etched window in the oxide layer, preferably the impurity being boron. The opening is then subsequently reoxidized.
The heat cycle for reoxidation also serves the function of driving in the impurity. The reoxidized surface is then etched, using photo-lithographic and subtractive etching technology to define the outline of the base regions of lower resistivity 22. This configuration is a generally comb-like configuration or other finger-like structure.
A p-type dopant is diffused into ,'~ ' ' . ' FI~-75-053 - 12 -DLM~Tl 1 - : ~ :~ , .
1~51~Z2 l the openings at a concentration significantly higher than the diffusion used to form base ~egion 14. The surface is then re-oxidized. The heat cycle for reoxidation also serves to drive in the P impurities in regions 14 and 22. ~n opening defining the emitter region 12 is then made in the overlying oxide layer using photolithographic and subtractive etching technology and a suitable N-type impurity diffused into the s~!bstrate to form the emitter region 12. The N-type impurity is preferably phos-phorous. The surface is subsequently reoxidized and contact open-ings made in the oxide. A layer of metallurgy as for examplealuminum is then deposited on the front and back sides of the silicon wafer and subsequently etched on the front side to form the base and emitter metallurgy systems. The back side metal serves as the collector metallurgy system.
The device of the invention as illustrated in FIGURE 3 can be conveniently ~abricated starting with an N+ silicon wafer having a resistivity on the order of 0.002 ohm cm. A silicon epitaxial layer is grown on the wafer which layer has a thickness on the order of 90 microns and a resistivity on the order of 30 ohm cm. The surface is oxidized and subsequently etched to form the configura-tion for forming the regions 26 underlying the emitter fingers. A
P-type impurity is then deposited through the exposed areas, as defined by the mask. The FI9-75-053 _ 13 "
' - . '' . .,:
- ~ . .
~S~L~22 1 silicon dioxide on the surface is then removed and additional epi-taxial silicon layer is deposited with a thickness on the order of 10 microns and a resistivity of 30 ohm cm. The surface is then reoxidized and an area removed to define the base region 14. A P-type impurity is diffused through the mask having a surface concentra-tion on the order of 8 x 1018 atoms/cc. The surface is reoxidized and etched to define the emitter con~isuration. An N-type impurity is diffused through the mask and the surface again reoxidized. Suit-able contact windows are made, metallization deposited and the indivi-dual discrete devices separated.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
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.. : . ' ''
: ~ ~ . , . . : . ~
~ --\
lOSl~
1 High power transistors usua11y include an emitter region havin~ a relatively large area so that the rower ;s distr;buted over the device to keep the power per unit area within safe limits.
It has previously been found that in a power transistor having a relatively large area emitter, injection of emitter current occurs mainly along the periphery of the emitter. To minimi~e this "current crowding", it has become the practice to define the emitter region so that it has as large a per-iphery as possible in relation to area.
A number of different con~igurations have been adapted to secure relatively large emitter periphery. One of these is an emitter that has a star shape or similar shapes which include a plurality of con-~olutions extending radially outwardly from a hub portion. Another is a multiplicity of separate emitter sites all connected in parallel to function as a composite emitter. A more prevalent configuration i5 one in which the base region and the emitter region are generally of comb-shape with a web portion and interdigitated fingers. The emitter may be a double comb with web portions back to back.
The use of such configurations as described above has greatly 2Q improved the effective use of emitter area. However, in general, when tbe transistor is "on", some current crowding occurs near the emitter periphery.
- , DLM/Tl ~ `
.. .
~..
~L~35~ 2 1 On the other hand, when the transistor is turned from the l'on"
cond;tion to the "off" condit;on, part;cularly when used with a high inductive load, the e~itter-collector current crowdi~g occurs near the center of the emitter fingers and the web. The direc-tion of the base current is the reverse of each other in these aforedescribed cases and the voltage drop caused by the transYerSe base current flowing throu~h the base resistance would be respon-sible for current crowding at the stated transistor regions. A
transistor can become destroyed by the second breakdown when the current density exceeds a certain limit while the collector-to-emitter voltage also is relatively high.
ObJect of the Invention An object of the present invention is to provide an improved power transistor having elongated emitter fingers that has ;mproved second breakdown capability.
A further object of this invention is to provide an improved power transistor having elongated em;tter port;ons wherein the base reg;on underlying the elGngated port;ons (fingers) and the web por-tion has a lower resistance which operates to increase the second breakdo~n capability.
Summary of the Invention The present invention comprises a power transîstor of the type that includes emitter, base and FI~-75-053 3 _ ~L~ L~LZ 2 1 collector regions of alternate conductivity types, and PN ~unctions at the interface of the emitter and base regions, and the interface of the base and collector regions, the improvement being an emitter reaion having at least a plurality of elongated finger portions which materially increases the emitter periphery-to-area ratio~ and a means in the base region underlying the finger portions of the emitter to lower the base resistance, in the transverse direction, under the central regions of the emitter finger porticns, this lower base resistance operating to increase the second breakdown capability of the transistor.
Brief Description of the Drawings FIGURE 1 is a perspecti~e view in broken sect;on illustrating a .
preferred specific embodiment of the power transistor of the inven-tion.
FIGURE 2 is an elevational view in broken section showing the internal structure of an embodiment of the invention.
FIGURE 2A is an impurity concentration profile taken on line 2A
in FIGURE 2 of a preferred specific embodiment of the invention.
FIGURE 3 is an elevational view in broken section illustrating another preferred specific embodiment of the invention.
' FI~-75-053 4 _ ~i "..~, ~5~1ZZ
1 FIGURE 3A is an impurity profile taken on line 3A of FIGURE
3 that depicts the impurity concentrations in the varicus regions oF the device of FIGURE 3.
Description of the Preferred Embodiments A typical power transistor constructed in accordance with the present invention has an emitter region 12, a base region 14, a lightly doped collector region 16, and a heavily doped collector region 18. Regions 12, 14 and 16 have alternate conductivity types as for example PNP or NPN, as is well known in the art. Guard rings 20 can be provided, if necessary or desirable, for increasing the base-collector breakdown voltage. The power transistor 10 of the invention is generally a discrete transistor although if desired it may be incorporated in a body alon~ with other transistors or elec-tronic elements. The current capability of a bi-polar transistor of the type illustrated in FIGURE 1 is directly related to the effec-tive emitter area. In a switching application of a conventional struc-ture without a finger-like configuration, when used For high voltage, high current capability3 only a very small portion of emitter area i~ effective. This is the result of current crowding which occurs ~.
near the emitter periphery during the "on" condition. ~As is known in the art, the base current which flows transversely in the active ba~e area causes the portion of the emitter-base junction near the emitter F19-75-Q53 - 5 _ . ~ .
~as~22 1 periphery to be more forward-biased than the portions near the center of the emitter. Consequently, the current flowing from the emitter toward the collector will flow in the emitter-base junc-tion regions that are more forward-biased, namely along the edges.
One well known way of improving the current capability of a transis-tor is to increase the periphery of the emitter. This can be ac-complished quite effectively by designing the emitter into a comb-like configuration having elongated fingers extending from a central web. This emitter configuration is illustrated in FIGURE 1. This emitter configuration reduces the transverse voltage drap across the base resistance underneath each emitter finger and the web portion and therefore reduces current crowding. The effective emitter area thus theoretically approaches the actual emitter area. The improve-ment in current capability provided by this configuration ls actually somewhat limited, however, since the introduction of a large number of narrow emitter fingers means that a considerable portion of the transistor chip area is wastefully occupied by the bàse fingers. Thus, for a given transistor chip area, the emitter area is reduced once again limiting thereby the current capability of the transistor. In view of the foregoing conditions, a structure compris;ng an optimum number of emitter fingers, each with an optimum width7 is needed which will maximize . . .
Fl9-75-053 ~Sl~Z~: ~
1 the effective emitter area for a given transistor area. However, when the width of the emitter fingers is optimally designed large enough so as to maximize the effective emitter area, another impor- ;
tant problem re~ains viz., the high likelihood of cecond breakdown when the transistor is turned "off", particularly when coupled to an induct;ve load. When the transistor is turned "off", the center portion of the emitter-base junction becomes, during transition ~rom "on" to "off", more fsrward-biased than the edge portion. The directicn of the base current is reversed when the transistor is 1~ turned off. In traversing the base region, this reverse base current creates a voltage drop whichg in turn, forms the aforementioned difference in emitter-base junction bias. As a consequence, the emitter-to-collector current in the transistor is now concentrated at the center portion of the fingers and web of the emitter. The poten-tial is large for destroying the transistor during the switching transition from "on" to "off" due to the simultaneous presence of the high current density at the center of emitter fingers and the web and the relatiYely high voltage imposed across the emitter and col-lector, especially when an inductive load is coupled to the transistor.
In this invention, a structure is provided which lowers the base resistance near the central regions under FI.9-75-Q53 - 7 -DLMlT6 ~LO S~L~L~2 1 the emitter fingers and web. This results in a more even distribution of current from the emitter to the collector during the switching transition from "on" to "off", since a greater portion of the emitter fingers and web is used for current flow. A first embodiment of the power transistor of the invention for achieving the decreased base resistance near the cent,ral regions under the emitter fingers and web is illustrated in FIGURES 1 and 2. A region 22 of a sheet resistance lower than the intrinsic base region 11 is provided which is located centrally and beneath each of the finger-like portions and the web portion of the .
emitter 12. The region 22 is doped with the same type of impurity as ~ ' intrinsic base region 11. In practice, the entire base region 14 embodi-es the same type oF impurity. In general, the sheet resistance of intrinsic or dumbell portion 11 of base region 14 exceeds the sheet resistance of region 22 of low resistivity by a factor in the range of 4 to 10. The impurity concentration in the various regions of the device is shown in impurity profile in FIGURE 2A. Profile 13 depicts the im- , purjt~y concentration of the emitter 12; profile 15 depicts the impurity :
concentration of region 22, and profile 17 of the base region 14. The .
concentration of the N- portion 16 of the collector and the N~ portion 18 of the collector is indicated by profile 24. In general, the thick- ,"
ness of emitter 12 is in the range FI~-75-053 - 8 -~L~)5~2~
1 o~ 4 to 12 microns, more preferabl~ 9 to ll microns. The surface concentration of the emitter is in the range of 2 x lOl9 to l x 102l, more preferably 6 x lOl9 to 2 x 102 atoms/cc. A typical emitter finger will be from 2 to lO mils in width with a length of 20 to 50 mils, more preferably with a width from 3 to 5 mils and a length of 30 to 40 mils. The extrinsic portion of base region 14 will have a thick-ness in the range of 8 to 25 microns, more preferably from 18 to 22 microns. The surface concentration of the base region 14 is in the range of 5 x 1017 to 1 x lOl9, more preferably l x 10l8 to 4 x 1018 atoms/cc. The N- portion 16 of the collector has a thickness in the range of 30 to 120 microns, more preferably 60 to 100 microns. The concentration in the N- collector region 16 which is preferably an epitaxial layer is in the range of I x 1014 to l x 1015 atoms/cc (with a resistivity in the range of 50 to 4 ohm cm., respectively), more preferably with an impurity concentration on the order of 1.5 x 1014 atoms/cc with a sheet resistivity on the order of 30 ohm cm. The N+
portion 18 of the collector has a thickness from 8 to 24 mils with an impurity concentration in the range of 5 x 1018 to l x 102 atoms/cc with a resistivity in the range of 0.01 to 0.001 ohm cm. More pre-~erably, the N+ portion 18 of the collector has a thickness in therange of 16 to 18 mils, with a concentration in the range of 2 x lOl9 to 4 x lOl9 atoms/cc and a resistivity on the order of FI9-75-053 ~ _ DL~/T8 10511~Z
1 .002 ohm cm. ~hen the transistor is a discrete device, the chip size will normally range from 120 by 120 mils square to 300 by 300 mils square, more preferably 180 mils by 180 mils to 240 by 240 mils square. The crystalline orientation of the device can be any suit able type as for example the ~ 100 7 or ';111~ orientation as de-fined by the Miller Indices. Power transistors utilizing the struc-ture of this invention are normally designed to have an amperage capa-city of 1 to 30 amps, more preferably 8 to 15 amps, and handle voltages in the range of 100 to 1200 volts, more preferably 300~to 700 volts.
The current gain-bandwidth frequency fT will be in the range of 0.5 to 50 MHz, more preferably 1 to 10 MHz. The ratio oF the width of the emitter finger 12 to the width of the base region 22 of low resis-tivity is preferably in the range of 3 to 5, more preferably on the order of 4.
Referring now to FIGURES 3 and 3A, there is depicted another pre-ferred specific embodiment of the power transistor of the invention.
In this embodiment, the intrinsic base region is increased in thick-ness below the center portion of emitter fingers and also the web portion. As indicated, below the center portion of emitter 12, there ~o is provided a depressed PN junction between the collector region and the base region. The ratio of the ~idth of the emitter finger 12 to the width of the base region 26 is in the range of 3 to 5, more DLMlT9 ~ O S ~ ~ 2 Z
1 preferably on the order of ~. In FIGURE 3A, there is depicted the various impurity concentrations of the regions of the device shown in FIGURE 3. Profile 27 indicates the impurity concentration of the region 26 wherein the thickness of the intrinsic base region 11 is increased beneath emitter finyers 12. By virtue of the profile 27, the resistance of the intrinsic base in the transverse direction is decreased beneath the central regions of the finger-like portions and the web portion of the emitter. This effectively reduces the cur-rent crowding in the central regions of the finger-like portions and the web portions of the em;tter 12 during the interval that the transistor is switched from "on" to the "off" condition. The ratio of the distance from the lower side of emitter to the lowest point of the base, which includes region 26, to the thickness of the in-trinsic base 11 jR. the distance bet~een the emitter and the flat PN
junction interface between the base and collector is in the range of 1.5 to 2, more preferably on the order of 1.8. The various impurity concentrations and other ratios of the embodiment of FIGURE 3 are similar to that disclosed with respect to the embodiment of FIGURE 2.
As is conventional, a passivating layer 28 of SiO2 or other dielectric materials or combinations is provided on the surface of the device, and openings made to contact the various regions of the device. As il-lustrated in FTGURES 2 and 3~ emitter DLMlTl O
.. . .
1 metallurgy fingers 30 make ohmic contact to emitter fingers 12 and base contacts 32 make contact to the base region 14. Contact is made to the N+ collector region 18 by providing a metal layer 34 on the underside of the device.
The devices of the invention as shown in FIGURES 1 and 2 can be fabricated by any suitable technique. In general, the starting material is a ~ 100 ~ silicon wafer doped with an N+ impurity having a resistivity of 0.002 ohm cm. An epitaxial silicon layer is then grown on the N~ wafer, with a thickness on the order of 100 microns -doped with an N- impurity with a resistivity on the order of 30 ohm cm. The surface of the epitaxial layer is then oxidized to form ap-proximately 5,000 Angstroms of silicon dioxide. The oxide layer is then etched, using photolithographic and subtractive etching techniques to define the base region 14. A P-type impurity is dif-fused through the etched window in the oxide layer, preferably the impurity being boron. The opening is then subsequently reoxidized.
The heat cycle for reoxidation also serves the function of driving in the impurity. The reoxidized surface is then etched, using photo-lithographic and subtractive etching technology to define the outline of the base regions of lower resistivity 22. This configuration is a generally comb-like configuration or other finger-like structure.
A p-type dopant is diffused into ,'~ ' ' . ' FI~-75-053 - 12 -DLM~Tl 1 - : ~ :~ , .
1~51~Z2 l the openings at a concentration significantly higher than the diffusion used to form base ~egion 14. The surface is then re-oxidized. The heat cycle for reoxidation also serves to drive in the P impurities in regions 14 and 22. ~n opening defining the emitter region 12 is then made in the overlying oxide layer using photolithographic and subtractive etching technology and a suitable N-type impurity diffused into the s~!bstrate to form the emitter region 12. The N-type impurity is preferably phos-phorous. The surface is subsequently reoxidized and contact open-ings made in the oxide. A layer of metallurgy as for examplealuminum is then deposited on the front and back sides of the silicon wafer and subsequently etched on the front side to form the base and emitter metallurgy systems. The back side metal serves as the collector metallurgy system.
The device of the invention as illustrated in FIGURE 3 can be conveniently ~abricated starting with an N+ silicon wafer having a resistivity on the order of 0.002 ohm cm. A silicon epitaxial layer is grown on the wafer which layer has a thickness on the order of 90 microns and a resistivity on the order of 30 ohm cm. The surface is oxidized and subsequently etched to form the configura-tion for forming the regions 26 underlying the emitter fingers. A
P-type impurity is then deposited through the exposed areas, as defined by the mask. The FI9-75-053 _ 13 "
' - . '' . .,:
- ~ . .
~S~L~22 1 silicon dioxide on the surface is then removed and additional epi-taxial silicon layer is deposited with a thickness on the order of 10 microns and a resistivity of 30 ohm cm. The surface is then reoxidized and an area removed to define the base region 14. A P-type impurity is diffused through the mask having a surface concentra-tion on the order of 8 x 1018 atoms/cc. The surface is reoxidized and etched to define the emitter con~isuration. An N-type impurity is diffused through the mask and the surface again reoxidized. Suit-able contact windows are made, metallization deposited and the indivi-dual discrete devices separated.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
D~M/T13 .
.. : . ' ''
Claims (13)
1. In a power transistor of the type that includes emitter, base and collector regions of alternate conductivity types, and PN junctions at the interface of the emitter and base regions, and at the interface of the base and collector regions, the improve-ment comprising:
said emitter region having at least a plurality of elongated finger-like portions, means electrically joining said finger-like portions, said emitter region located within and surrounded by said base region, a means in said base region to lower the base resistance in the transverse direction, said means located beneath central re-gions of said finger-like portions.
said emitter region having at least a plurality of elongated finger-like portions, means electrically joining said finger-like portions, said emitter region located within and surrounded by said base region, a means in said base region to lower the base resistance in the transverse direction, said means located beneath central re-gions of said finger-like portions.
2. The power transistor of Claim 1 wherein said means electri-cally joining said finger-like portions is a diffused region form-ing a web portion joining said finger-like portions.
3. The power transistor of Claim 1 wherein said means to lower the base resistance is comprised of regions of low resistivity lo-cated centrally and beneath each of said finger-like portions of said emitter and said web portion of said emitter.
4. The power transistor of Claim 3 wherein the ratio of the sheet resistance of said intrinsic base region to the sheet re-sistance of said regions of low resistivity is in the range of 4 to 10.
5. The power transistor of Claim 3 wherein the ratio of the width of said finger-like portions and said web portion of said emitter to the width of said regions of low resistivity beneath said finger-like portions and said web portion of said emitter, re-spectively, is in the range of 3 to 5.
6. The power transistor of Claim 3 wherein the ratio of the width of said finger-like portions and said web portions of said emitter to the width of said regions of low resistivity beneath said finger-like portions and said web portion of said emitter, re-spectively, is on the order of 4.
7. The power transistor of Claim 6 wherein the conductivity type of said emitter is N, said base is P, and said collector is N.
8. The power transistor of Claim 1 wherein said means to lower base resistance is comprised of base regions of increased thick-ness and increased impurity concentration in a vertical direction located centrally and beneath each of said finger-like portions of said emitter.
9. The power transistor of Claim 8 wherein the ratio of the width of said finger-like portions of said emitter to the width of said regions of increased base thickness is in the range of 3 to 5.
10. The power transistor of Claim 8 wherein the ratio of the thick-ness in the vertical direction of said regions of increased base thickness to the base regions below the emitter in other than the central portion of the fingers is in the range of 1.5 to 2.
11. The power transistor of Claim 8 wherein the conductivity type of said emitter is N, said base is P, and said collector is N.
12. The power transistor of Claim 3 wherein said emitter has a thickness in the vertical direction in the range of 4 to 12 microns, said finger-like portions have a width in the range of 2-10 mils, said web portion has a width in the range of 10-30 mils, and a surface impurity concentration in the range of 2 x 1019 to 1 x 1021 atoms/cc.
13. The power transistor of Claim 8 wherein said emitter has a thickness in the vertical direction in the range of 4 to 12 microns, said finger-like portions have a width in the range of 2-10 mils, said web portion has a width in the range of 10-30 mils, and a surface impurity concentration in the range of 2 x 1019 to 1 x 1021 atoms/cc.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US64322075A | 1975-12-22 | 1975-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1051122A true CA1051122A (en) | 1979-03-20 |
Family
ID=24579882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA267,943A Expired CA1051122A (en) | 1975-12-22 | 1976-12-15 | Power transistor having improved second breakdown capability |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1051122A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4296336A (en) * | 1979-01-22 | 1981-10-20 | General Semiconductor Co., Inc. | Switching circuit and method for avoiding secondary breakdown |
-
1976
- 1976-12-15 CA CA267,943A patent/CA1051122A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4296336A (en) * | 1979-01-22 | 1981-10-20 | General Semiconductor Co., Inc. | Switching circuit and method for avoiding secondary breakdown |
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