CA1048651A - Synchronous binary multiply using non-threshold logic - Google Patents

Synchronous binary multiply using non-threshold logic

Info

Publication number
CA1048651A
CA1048651A CA75219014A CA219014A CA1048651A CA 1048651 A CA1048651 A CA 1048651A CA 75219014 A CA75219014 A CA 75219014A CA 219014 A CA219014 A CA 219014A CA 1048651 A CA1048651 A CA 1048651A
Authority
CA
Canada
Prior art keywords
multiplier
emitters
transistors
gates
invention according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA75219014A
Other languages
English (en)
French (fr)
Other versions
CA219014S (en
Inventor
James L. Buie
George W. Mciver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Space and Mission Systems Corp
Original Assignee
TRW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Application granted granted Critical
Publication of CA1048651A publication Critical patent/CA1048651A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
CA75219014A 1974-02-11 1975-01-30 Synchronous binary multiply using non-threshold logic Expired CA1048651A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US441099A US3900724A (en) 1974-02-11 1974-02-11 Asynchronous binary multiplier using non-threshold logic

Publications (1)

Publication Number Publication Date
CA1048651A true CA1048651A (en) 1979-02-13

Family

ID=23751505

Family Applications (1)

Application Number Title Priority Date Filing Date
CA75219014A Expired CA1048651A (en) 1974-02-11 1975-01-30 Synchronous binary multiply using non-threshold logic

Country Status (8)

Country Link
US (1) US3900724A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS50115940A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1048651A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2505653B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2260828B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1496935A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IL (1) IL46581A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL7501418A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215418A (en) * 1978-06-30 1980-07-29 Trw Inc. Integrated digital multiplier circuit using current mode logic
NL7809398A (nl) * 1978-09-15 1980-03-18 Philips Nv Vermenigvuldiginrichting voor binaire getallen in twee-complement notatie.
US4302819A (en) * 1979-10-22 1981-11-24 Hewlett-Packard Company Fault tolerant monolithic multiplier
US4369500A (en) * 1980-10-20 1983-01-18 Motorola Inc. High speed NXM bit digital, repeated addition type multiplying circuit
ES509061A0 (es) 1981-02-02 1983-06-16 Rca Corp Perfeccionamientos introducidos en una instalacion de tratamiento de senales de television digitales.
DE3267489D1 (en) * 1982-02-18 1986-01-02 Itt Ind Gmbh Deutsche Digital parallel calculating circuit for positive and negative binary numbers
FR2524175A1 (fr) * 1982-03-25 1983-09-30 Labo Cent Telecommunicat Structure de multiplieur rapide en circuit integre mos
US4616330A (en) * 1983-08-25 1986-10-07 Honeywell Inc. Pipelined multiply-accumulate unit
US4748583A (en) * 1984-09-17 1988-05-31 Siemens Aktiengesellschaft Cell-structured digital multiplier of semi-systolic construction
US4887233A (en) * 1986-03-31 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Pipeline arithmetic adder and multiplier
US4768161A (en) * 1986-11-14 1988-08-30 International Business Machines Corporation Digital binary array multipliers using inverting full adders
JP2672956B2 (ja) * 1988-01-25 1997-11-05 沖電気工業株式会社 並列乗算器
US5283755A (en) * 1993-04-14 1994-02-01 International Business Machines Corporation Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration
GB2290156A (en) * 1994-06-01 1995-12-13 Augustine Kamugisha Tibazarwa Bit-focused multiplier
KR0152911B1 (ko) 1994-09-10 1998-10-15 문정환 병렬승산기
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US6230257B1 (en) 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
FR2789192B1 (fr) * 1999-02-02 2001-04-20 Thomson Csf Additionneur chainable rapide a retenue anticipee
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
CN112783472B (zh) * 2019-11-05 2023-12-12 何群 多值逻辑宽位高速加法器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3506817A (en) * 1967-02-24 1970-04-14 Rca Corp Binary arithmetic circuits employing threshold gates in which both the sum and carry are obtained in one gate delay interval
US3602705A (en) * 1970-03-25 1971-08-31 Westinghouse Electric Corp Binary full adder circuit
JPS5013068B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1970-07-31 1975-05-16
US3752971A (en) * 1971-10-18 1973-08-14 Hughes Aircraft Co Expandable sum of cross product multiplier/adder module
US3795880A (en) * 1972-06-19 1974-03-05 Ibm Partial product array multiplier

Also Published As

Publication number Publication date
GB1496935A (en) 1978-01-05
DE2505653B2 (de) 1979-03-01
IL46581A (en) 1976-09-30
IL46581A0 (en) 1975-04-25
NL7501418A (nl) 1975-08-13
FR2260828A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1975-09-05
DE2505653A1 (de) 1975-08-14
US3900724A (en) 1975-08-19
JPS50115940A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1975-09-10
FR2260828B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1980-04-18

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