NL7501418A - Vermenigvuldiger met hoge dichtheidsgraad. - Google Patents

Vermenigvuldiger met hoge dichtheidsgraad.

Info

Publication number
NL7501418A
NL7501418A NL7501418A NL7501418A NL7501418A NL 7501418 A NL7501418 A NL 7501418A NL 7501418 A NL7501418 A NL 7501418A NL 7501418 A NL7501418 A NL 7501418A NL 7501418 A NL7501418 A NL 7501418A
Authority
NL
Netherlands
Prior art keywords
multipliers
density
density multipliers
Prior art date
Application number
NL7501418A
Other languages
English (en)
Original Assignee
Trw Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trw Inc filed Critical Trw Inc
Publication of NL7501418A publication Critical patent/NL7501418A/nl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0772—Vertical bipolar transistor in combination with resistors only

Landscapes

  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
NL7501418A 1974-02-11 1975-02-06 Vermenigvuldiger met hoge dichtheidsgraad. NL7501418A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US441099A US3900724A (en) 1974-02-11 1974-02-11 Asynchronous binary multiplier using non-threshold logic

Publications (1)

Publication Number Publication Date
NL7501418A true NL7501418A (nl) 1975-08-13

Family

ID=23751505

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7501418A NL7501418A (nl) 1974-02-11 1975-02-06 Vermenigvuldiger met hoge dichtheidsgraad.

Country Status (8)

Country Link
US (1) US3900724A (nl)
JP (1) JPS50115940A (nl)
CA (1) CA1048651A (nl)
DE (1) DE2505653B2 (nl)
FR (1) FR2260828B1 (nl)
GB (1) GB1496935A (nl)
IL (1) IL46581A (nl)
NL (1) NL7501418A (nl)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215418A (en) * 1978-06-30 1980-07-29 Trw Inc. Integrated digital multiplier circuit using current mode logic
NL7809398A (nl) * 1978-09-15 1980-03-18 Philips Nv Vermenigvuldiginrichting voor binaire getallen in twee-complement notatie.
US4302819A (en) * 1979-10-22 1981-11-24 Hewlett-Packard Company Fault tolerant monolithic multiplier
US4369500A (en) * 1980-10-20 1983-01-18 Motorola Inc. High speed NXM bit digital, repeated addition type multiplying circuit
ES8308464A1 (es) 1981-02-02 1983-06-16 Rca Corp Perfeccionamientos introducidos en una instalacion de tratamiento de senales de television digitales.
DE3267489D1 (en) * 1982-02-18 1986-01-02 Itt Ind Gmbh Deutsche Digital parallel calculating circuit for positive and negative binary numbers
FR2524175A1 (fr) * 1982-03-25 1983-09-30 Labo Cent Telecommunicat Structure de multiplieur rapide en circuit integre mos
US4616330A (en) * 1983-08-25 1986-10-07 Honeywell Inc. Pipelined multiply-accumulate unit
US4748583A (en) * 1984-09-17 1988-05-31 Siemens Aktiengesellschaft Cell-structured digital multiplier of semi-systolic construction
US4887233A (en) * 1986-03-31 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Pipeline arithmetic adder and multiplier
US4768161A (en) * 1986-11-14 1988-08-30 International Business Machines Corporation Digital binary array multipliers using inverting full adders
JP2672956B2 (ja) * 1988-01-25 1997-11-05 沖電気工業株式会社 並列乗算器
US5283755A (en) * 1993-04-14 1994-02-01 International Business Machines Corporation Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration
GB2290156A (en) * 1994-06-01 1995-12-13 Augustine Kamugisha Tibazarwa Bit-focused multiplier
KR0152911B1 (ko) 1994-09-10 1998-10-15 문정환 병렬승산기
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6230257B1 (en) 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
FR2789192B1 (fr) * 1999-02-02 2001-04-20 Thomson Csf Additionneur chainable rapide a retenue anticipee
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
CN112783472B (zh) * 2019-11-05 2023-12-12 何群 多值逻辑宽位高速加法器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3506817A (en) * 1967-02-24 1970-04-14 Rca Corp Binary arithmetic circuits employing threshold gates in which both the sum and carry are obtained in one gate delay interval
US3602705A (en) * 1970-03-25 1971-08-31 Westinghouse Electric Corp Binary full adder circuit
JPS5013068B1 (nl) * 1970-07-31 1975-05-16
US3752971A (en) * 1971-10-18 1973-08-14 Hughes Aircraft Co Expandable sum of cross product multiplier/adder module
US3795880A (en) * 1972-06-19 1974-03-05 Ibm Partial product array multiplier

Also Published As

Publication number Publication date
IL46581A0 (en) 1975-04-25
CA1048651A (en) 1979-02-13
JPS50115940A (nl) 1975-09-10
IL46581A (en) 1976-09-30
GB1496935A (en) 1978-01-05
US3900724A (en) 1975-08-19
FR2260828B1 (nl) 1980-04-18
DE2505653B2 (de) 1979-03-01
DE2505653A1 (de) 1975-08-14
FR2260828A1 (nl) 1975-09-05

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Legal Events

Date Code Title Description
BV The patent application has lapsed