CA1040745A - Semiconductor switching device having unusual shorted emitter configuration - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A PNPN switching device is provided with an array of metallic shunts for shorting the emitter junction at a plurality of discrete locations which are distributed over substantially the whole area of the emitter in a predeter-mined pattern of substantially uniform density except in the vicinity of the turn-on line where the density is appreci-ably increased.

Description

- llCU-4073 1040~45 This invention relates generally to solid-state electric current switches of the multi-layer semiconductor type, and more particularly it relates to a high power silicon controlled rectifier (known generally as a thyristor or SCR) having improved ability to withstand non-repetitive peak re-verse voltage.
Typically a power thyristor comprises a thin, broad area disc-like body having four distinct layers of semi-conductor material (preferably silicon), with contiguous layers being of different conductivity types to form three back-to-back PN (rectifying) junctions in series. To the outer surfaces of the respective end layers of the silicon body a pair of main current-carrying metallic contacts or electrodes (anode and cathode) are conductively joined in low-resistance ohmic contact therewith, and the body is normally eguipped with at least one control contact or electrode ~gate) for i triggering conduction between these main electrodes. To complete the device the silicon body is sealed in an insulating housing, and it can be externally connected to associated elec-tric power and control circuits by means of its main and control electrodes.
A thyristor that is connected in series with a load impedance and a source of voltage will ordinarily block appreciable current flow between its anode and cathode when-ever the applied voltage is reversely poled (i.e., anode potential negative with respect to cathode) and also when forward voltage is applied in the absence of a control signal.
To turn on the thyristor, a small gate current of suitable magnitude and duration is supplied to its control electrode while the main electrodes are forward biased (anode potential positive with respect to cathode), whereupon the device ab-ruptly switches from a high resistance off state to a very ., .
. ~ .

llCU-4073 104V7~5 low resistance, forward conducting state. Once triggered in this manner, the thyristor will continue to conduct until load current is subsequently reduced below a given holding level, whereupon the device reverts to its blocking (turned off) state.
; During the turn on process, the rate at which anode current rises is known as the inrush current slope, or di/dt.
To increase the di/dt ability of a high power thyristor, it is a known practice in the art to use a so-called pilot or amplifying gate structure. In accordance with this practice, a relatively small auxiliary region of the N-type end layer of the silicon wafer (which layer is called the emitter) is disposed between the gate contact and the main emitter re-gion from which it is separated by a gap. The auxiliary region of the emitter is isolated from the cathode, and a metallic pilot contact on its outer surface extends to an adjacent surface of the P-type base layer which is exposed in the aforesaid gap. The auxiliary region i8 dimensioned and located in relation to the main region of the emitter 80 that the initial anode current that traverses the aux-iliary region when the thyristor is triggered constitutes a high energy turn on signal for the main portion of the de-vice. See reissue U.S. patent RE.27,440 - DeCecco et al-issued July 8, 1972. In high-current or high-frequency thy-ristors of this ~ind, the pilo~ contact is so arranged that the high energy turn on signal is uniformly distributed along an appreciable length of the adjacent border of the main emitter region, whereby this signal triggers a relatively large area of the main region. Since the main emitter region will start conducting anode current in the area triggered by the high energy turn on signal, this area is hereinafter referred to as the turn on line. See U.S. patent 3,577,046-Moyson - issued May 4, 1971 for further information regarding , llCU-4073 the theory and construction of amplifying gate thyristors.
When an off-state thyristor is subjected to rapidly rising forward bias voltage, it is prone to turn on in the dv/dt mode. To improve the dv/dt withstandability of all-diffused thyristors, it is a known practice in the art to use a ~shorted emitter~ construction. In accordance with this practice, the metallic electrode which serves as the cathode of the thyristor is also connected to the P-type base layer of the silicon wafer, thereby short circuiting the rectifying (PN) junction between this base layer and the contiguous N-type emitter. The primary function of shorting the emitter is to reduce its efficiency at low current levels. As a result of reduced emitter efficiency, the high-temperature forward blocking voltage capability of the thyristor is increased and the dv/dt rating is improved. The shorts also provide a path for the removal of stored carriers from the P-type base and increase the holding current of the device, thereby reducing the turn off time.
The basic shorted emitter construction, in which the cathode contact i8 extended beyond the compa~s of the emitter 80 as to provide an electroconductive path of low resistance across the peripheral edges of the emitter junction, is dis-closed in U.S. patent No. 3,476,993 - Aldrich et al - issued November 4, 1969. For very large area wafers, it i8 common practice to additionally provide an array of relatively ~mall channels or shunts for shorting the emitter junction at a plurality of discrete locations which are evenly spread over essentially the whole emitter area. See U.S. patent 3,634,739-Borchert, et al, issued January 11, 1972, for example. These low-resistance shunts can be of various shapet and sizes, and for any given size they can be distributed in any one of ~ a variety of different patterns and densities. In all cases ':
~ -3-_ llCU-4073 104, 0~45 it is important that the discrete shunts have a substantially uniform density (i.e., nearly equal spacings between adjacent shunts), because if any shunt were left out the temperature and dv/dt sensitivities of the emitter in that particular location would be undesirably increased, and the sweep out of the base during turn-off action would be undesirably impeded.
However, in order to prevent undesirable gate-cathode or pilot-cathode short circuits, it is also necessary to avoid shunt-ing the portion of the emitter junction through which trig-gering cu~rent must flow to turn the device on (or to give the metallic path across thi6 portion a relatively high re-sistance). According to one prior art teaching, U.S. patent 3,476,992 - Chu - issued November 4, 1969, certain advantages can be obtained by also eliminating the first row of discrete shunts near the edge of the emitter region adjacent to the ; gate.
One of the universal goals of designers and manu-facturer~ of thyristors i8 to increase the production yield of these devices. Yield is the ratio of the number of usable thyri~tors to the total number of thyristors that are pro-duced in a given period of time. If on evaluation after fab-rication a thyristor fails to pass certain tests, it may have to be derated or scrapped. For example, if when tested for forward voltage breakover a thyristor safely self fires at a voltage under the VBo level for which it was designed, it has to be assigned a voltage rating that is lower than desired. The result is similar if the thyristor undergoes an avalanche breakdown at a voltage below the reverse break-down voltage rating for which it was designed. On the other hand, a thyristor can be permanently damaged by voltage overstress if, on increasing the reverse voltage to a level within its theoretical breakdown rating, the reverse leakage -~ llCU-4073 ~040745 current were to increase to a destructively high level, and in this event the failed thyristor would have to be scrapped.
Failures of this type will of course undesirably reduce the yield.
It has now been found that high power thyristors with amplifying gate and shorted emitter structures c~n be made apparently more immune to reverse voltage overstress by utilizing an unusual arrangement of emitter shunts. This is surprising, because inæofar as I am presently aware no one has heretofore correlated the pattern of emitter shorts with the reverse bloc~ing performance of a thyristor. Accordingly, it is a general objective of this invention to provide a high power thyristor characterized by a novel configuration of emitter shunts and an improved resistance to failures due to roverse voltags overstress, In carrying out the invention in one form, a broad ~` area wafer of semiconductor material is provided with four layers of alternately P and N c onductivity types. A pair of main current carrying metallic electrodes joined to the opposite end layers of the semi~onductor wafer provide connections to an external electric circuit, and a source of ; gate current impinging on a predetermined one of the layers enables the device to be triggered from a relatively high impedance, nonconducting state to a low impedance forward conducting state. One of the end layers of the wafer, which layer is called the emitter, is provided with juxtaposed main and auxiliary regions, the latter being located between the former and the aforesaid source of gate current, and a metallic pilot contact is connected both to the auxiliary region of the emitter and to a surface of the adjoining base layer of the wafer. Turn-on of the portion of the wafer under the - auxiliary emitter is controlled by the gate current, and the _5_ ~~ llCU-4073 i040~45 ; resulting current through the pilot contact provides a high energy triggering signal for the main portion of the wafer.
Main current will start flowing in the main region of the emitter along a turn-on line which effectively coincides with the border of this region closest to the pilot contact.
The main electrode which i8 associated with the emitter is disposed in ohmic contact not only with the main emitter region but also with a plurality of discrete areas of the contiguous base layer to thereby provide a plurality of metallic shunts across the emitter junction (i.e., the PN
junction formed between the main region of the emitter layer and the contiguous base layer). These metallic shunts are distributed over essentially the whole area of the main emitter region in a predetermined pattern of substantially uniform density except for those shunts in close proximity to the aforesaid turn-on line. The latter shunts are arranged in a row paralleling the turn-on line, and their density is appre-ciably higher than the density of the other shunts. Devices having a double-density row of shunts adjacent to the turn-on line have been found to be consistently superior in their ability to withstand reverse voltage overstresses.
The invention will be better understood and its various objects and advantages will be more fully appreciated from the following description taken in conjunction with the ac-companying drawings in which:
Fig. 1 is a schematic diagram of a prior art PNPN
semiconductor switching device including amplifying gate and shorted emitter features, which device is shown connected in ~ an electric circuit;
;~ 30 Figs. 2, 3, and 4 are plan views of prior art devices which respectively have annular, hexagonal, and interdigitated form~ of amplifying gates:

.
, llCU-4073 Fig. 5 is an enlarged plan view of one quadrant of a deviice æimilar to the one shown in Fig. 2 and having a pattern of emitter shorts which embodies a preferred form of the present invention; and Fig. 6 is an elevational view of the quadrant of the device shown in Fig. 5.
The PNPN semiconductor switching device shown schematically in Fig. 1 includes an asymmetrically conductive body 11 having four layers or zones 12, 13, 14, and 15 of semiconductor material arranged in succession between a pair of main current-carrying electrodes comprising metallic con-tacts 16 and 17. Contiguous layers of the semiconductor body are given different conductivity types 80 that their respective interface boundaries form three rectifying junc-tions Jl, J2, and J3 in series between the main eleetrodes 16 and 17. The N-type end layer 15 is herein referred to as the emitter layer, and the rectifying junction J3 that it forms with the contiguous P-type base layer 14 i~ herein re-ferred to as the emitter junction.
The main electrode 17 of the device 11 is disposed in broad area ohmic contaet with the outer face of the emitter 15 and extends in short-circuiting relation across the peri-pheral edge of the emitter junction J3 into ohmic contact with the base layer 14. This electrode serves as the cath-ode of the deviee 11, and the eompanion main electrode 16, which makes low-resistance ohmic contact with the outer face ~` of the P-type opposite end layer 12, serves as the anode.
By means of these main electrodes, the device 11 is connect-ed to an external electrie current cireuit comprising a load impedanee 18, a souree of voltage represented by the termin-, .
als l9a and l9b, and other eonventional eomponents (not shown) sueh as a series choke and a parallel snubber circuit which :;

:`

llCU-4073 ~04074S
ordinarily are associated with the deviee. Impinging on the P-type base layer 14 there is a eontrol electrode comprising a metallie eontaet 21, and a eontrolled souree 20 of gate eurrent i8 eonneeted between this eontaet and the cathode 17 in order to trigger the device when conduetion is desired.
As is shown in Fig. 1, the ~-type emitter layer 15 of the device 11 is divided into a main region A and a smaller auxillary region B which is laterly displaced with respect to the main region. The auxiliary emitter B is located between the gate contact 21 and the main emitter A, and it forms a reetifying junction J3' with a eontiguous region of the P-type base layer 14. A metallic pilot contact 22 overlies the outer faee of this auxiliary emitter in low-resistance ohmie eontaet therewith, and the pilot eontaet 22 also ex-tends aeross an edge of the junetion J3' into similar con-; taet with the expo~ed surface of another region of the base layer 14 loeated between the main and auxiliary regions A
and B of the emitter 15. However, the pilot contact 22 is not eonnected to the whole area of the surface of this base region, and between it and the main emitter junction J3 there is a gap or channel 23 which is free of contact with either the pilot contact 22 or the eathode 17. This is the above-refereneed amplifying gate arrangement.
To complete a commereially praetical thyristor, the device 11 should be enclosed in an hermetieally sealed insu-lating housing of any known design, with its respeetive main and eontrol eleetrodes 16, 17, and 21 being suitably eonneet-ed to eorresponding terminal members of the housing whieh ; members in turn are adapted to be eonnected to the illustra-ted external circuits by means of appropriate supporting and heat dissipating structure (not shown).
; In operation, the thyristor 11 is triggered from a ` -8-llCU-4073 relatively high impedance, non-conducting state to a low impe-dance conducting state by energizing its gate contact 21 with a relatively small gate signal when its main electrodes are forward biased. This turns on the device under the auxiliary region B of the emitter layer 15, whereupon main current will flow in a path which includes the auxiliary emitter B, the pilot contact 22, a portion of the ba~e layer 14 under the channel 23, and the region of the emitter junction J3 adja-cent to the pilot contact. Main current traversing the lat-; 10 ter junction constitutes a peremptory trigger signal of rela-tively high energy for a broad area of the main emitter re-gion A, and interelectrode current consequently starts flow-ing directly between the anode 16 and the cathode 17 along a predetermined turn-on line of the main emitter A. The turn-on line will effectively coincide with the border of the main emitter that i8 parallel and adjacent to the pilot contact.
By using the above-described structure, a high power thyristor capable of withstanding a peak voltage of at least 1,800 volts in its off state, of conducting an average for-ward current of more than 1,000 amperes in its on state, and of turning on with high di/dt ability can be controlled by a gate signal of the order of 100 milliamps and less than 5 volts.
The Fig~ 1 view of the thyristor lL is schematic and is not intended to be to scale. In practice the device will ordinarily comprise a very thin, broad area disc-like wafer of silicon whose outside diameter exceeds one inc~ and may approach two inches or more. The P layers 12 and 14 and the N layer 15 are formed in the originally N-type wafer by diffusion techniques well known to those skilled in the art.
The thicknesses or widths of all four layers are very small, typically 5.5, 10, 3.5, and 0.25 mils, respectively. The sheet ~ - llCU-4073 1040'745 resistance of the P-type base layer 14 at the emitter junc-tion J3 is the range of 300 to 3,000 ohms per square. The anode 16, the cathode 17, the gate contact 21, and the pilot contact 22 are thin layers of aluminum or the like. The anode 16 can be attached by an alloying process and is ordin-arily backed by a rugged substrate of tungsten (not shown).
The cathode 17 and the pilot contact 22, which are only about 0.5-mil thick, are applied by an evaporation technigue or other suitable process which avoids counter-doping the ~-type emitter layer lS.
Three different amplifying gate arrangements are illustrated in Figs. 2, 3, and 4. In the device 3hown in Fig.

2, the pilot contact 22 has an annular configuration, as does the auxiliary region of the emitter which it overlies. Pref-erably the gate contact 21 is }ocated in the center of the wafer where it is circumscribed by the auxiliary emitter, and the auxiliary emitter in turn is surrounded by the main emitt~r~region and its associated main electrode 17, both of which are annular in shape and concentric with the pilot contact 22. Consequently, as is depicted by the broken-line circle 24 in Fig. 2, the turn-on line of the main emitter effective-ly coincides with the inside perimeter thereof. With this arrangement the length of the turn-on line 24 is desirably long, for example nearly 1.5 inches in a wafer whose dia-meter is two inches.
The device shown in Fig. 3 i8 generally similar to the one shown in Fig. 2 except that its pilot contact 22 (and the underlying auxiliary emitter region) has a hexagonal shape. The turn-on line in this case is also hexagonal, as is indicated by the broken line 25, and its length is ap-proximately the same as in the Fig. 2 embodiment. For an even longer turn-on line, an interdigitated gate construction llCU-4073 1040'74~
can be used. This is illustrated by way of example in Fig.
4 where the pilot contact 22 is provided with a plurality of inteqrally formed metallic fingers 22a, 22b, 22c, and 22d extending outwardly from tne central annular portion of this contact. Distal portions of these fingers are connected to surfaces of the underlying base layer 14 respectively adja-cent to the opposing sides of four different segments or re-gions of the main emitter layer under the cathode 17. In this embodiment the turn-on line follows the outline of the fingers 22a, etc., as is indicated by the broken line 26.
Alternatively, the fingers could conform to the patterns dis-closed in the above-referenced Moyson patent, or they could have an involute geometry as taught in U.S. patent No.

3,609,476 - Storm - issued September 28, 1971.
In all of the cases described above, it is assumed that the cathode 17 of the device 11 not only contacts a per-ipheral area of the P-type baso layer 14 beyond the compas~
of the main region of the N-type emitter layer but also makes ohmic contact with a plurality of small discrete areas of the base layer spread over substantially the whole of the main emitter region, thereby providing a plurality of metallic ~hunts across the emitter junction J3. As is well known to persons skilled in the art, these separate emitter shunts are u~ually distributed in circular, hexagonal, square, or .
other suitable patterns so that all pairs of adjacent shunts are spaced nearly equally from each other, whereby their density is substantially uniform. The present invention departs from this prior art practice in that the ~hunt density of the row of shunts closest to the turn-on line is appreciably higher than the uniform shunt density in the major part of the emitter area. In a conventional pattern of shunts, where each of the individual shunt~ is a given size and where all llCU-4073 adjacent rows of shunts as well as adjacent shunts in each row are approximately equally spaced from one another, the nu~ber of shunts per unit length of each row of shunts will be a measure of their density, and by "appreciably higher"
density in the row adjacent to the turn-on line I mean that in this row the shun~ts (or the same given size) are spaced closer together so that their density exceeds by at least of the order of 25 per cent the density of the shunts in the other rows distributed over the major part of the emitter.
More details of a preferred embodiment of the invention have been shown in Figs. 5 and 6 which will now be described.
Fig. 5 is an enlarged plan view of one quarter of a thyristor which is provided with a center gate 21, an annular pilot contact 22, and an annular cathode 17 similar to the arrangement shown in Fig. 2. The dots 31 shown in the cath-ode 17 are intended to represent an array of discrete shunts which are distributed in concentric annular rows over the whole area of the main emitter lSA. These shunts are intro-duced by-t~j~niques well known to persons skilled in the art.
By way of example, after the N-type emitter layer 15 is superimposed on the P-type base layer 14 in the silicon wafer 11, it is temporarily covered by a film of masking material having a predetermined pattern of apertures or windows which ., expose a corresponding pattern of the surface of layer 15, and the wafer is then bathed in a suitable chemical etchant to remove channels of silicon to a controlled depth in these apertures. The pattern includes a desired array of small holes each of which, in the illustrated thyristor, is approxi-mately 3 mils in diameter and extends completely through the emitter layer to a depth of at least 0.5 mil. Later the mask is removed and a thin layer of aluminum is evaporated on the surface of the wafer to form the cathode 17. During this ~ 11 C~-4073 1040'745 step the aluminum will penetrate and fill the discrete holes which were etched away, and consequently, as is clearly shown in Fig. 6, each cathode penetration 31 separately shunts the rectifying junction J3.
The centers of the shunts 31 in adjacent rows are ra-dially æpaced apart by a predetermined distance (e.g., 16 mils), and in each row the centers of adjacent shunts are spaced apart by approximately the same distance (e.g., 16~ mils). Thus a substantially uniform shunt density of ap-proximately 60 shunts per inch is obtained over the major part of the emitter area.
In accordance with my invention, between the uniformly patterned shunts 31 and the turn-on line 24 of the main emitter 15A (which line subtends the inside perimeter of the annular cathode 17), an additional plurality of metallic shunts 32 are arranged in an annular row which is parallel to the turn-on line and characterized by a shunt density along its full length appreciably higher than the uniform density of the shunts 31. Preferably the density of the shunts 32 in this row is approximately twice the uniform density of the shunts 31, and the centerline of this row is radially spaced from the turn-on line by a distance X which . .`!
is substantially less than the distance separating the cen-ters of ad~acent shunts 31. In the illustrated thyristor the distance X is approximately 7 to 8 mils.
The provision of a higher density row of shunts 32 in proximity to the turn-on line 24 of course decreases the temperature and dv/dt sensitivities of the device in this region. In addition, it apparently improves the ability of .^
a thyristor to withstand voltage overstresses. No clear explanation for the latter result has been found in popular description6 of thyristor operation. Nevertheless, two -- llCU-4073 possible theories have been postulated to account for the improvement that was observed.
1. When a thyri~tor is reverse biased (anode potential negative with re~pect to cathode), the space-charge region associated with its blocking junction Jl is believed to hàve perturbed or distorted areas under the turn-on line of the emitter. This is because the portion of reverse leak-age current in the zone or region of the device subtending the gate and pilot contacts is forced to follow a lateral path between this zone and the zone under the cathode, and such lateral flow of current causes the leakage current in the N-type base layer 13 to have a lateral component. This lateral component distorts the space-charge region whose edge, being an equipotential line, must be perpendicular to the leakage current. The distorted area of the space-charge region extends closer to the center junction J2, and upon punching through to this junction it will precipitate a re-ver~e avalanche breakdown of the device. Increasing the shunt density in~proximity to the turn-on line provideR pre-ferred paths for the leakage current, thereby reducing the aforesaid lateral component and desirably reducing the dis-tortion of the space-charge region.
~ 2. Deterioration of the blocking ability of the rectify-;:
ing junction Jl when reverse biased may actually take place ;i during VBo firing if the device breaks over in the area of it~ gate contact. This can be explained by noting that when .
the device is fired in the VBo mode the capacitance of the blocking junctions discharges through an internal loop in the ;

silicon wafer which loop includes inductance and resistance.
The loop traverses an area of the junction Jl which was pre-viously forward biased by forward leakage current, and cur-rent in this area quickly oscillates to zero and reverses , llCU-4073 ~040745 direction. This area of Jl will soon clean out, whereupon there is generated across the junction a transient reverse voltage spike whose magnitude depends on the values of the junction capacitances and the inductance and the resistance in the internal loop. To help dampen this oscillation, it is desirable to increase the resistance of the internal loop.
One way to do this is to keep the conductivity in the bulk of the N-type base layer 13 as low as practical when saturated conduction begins, and this result can be obtained by reduc-ing the total excess Minority carriers in this layer. The relatively high shunt density in the first row of shunts ad-jacent to the turn-on line reduces the emitter ejection effi-ciency in this area and consequ~ntly has the desired effect of reducing the bulk conductivity in the corresponding region ~ of the N-type base layer. In most cases this region i8 part ; of the internal discharge loop because forward breakover of the device ordinarily occurs under the gate contact, thereby causing a high energy trigger signal to flow to the main emit-ter region 15A along the outboard edge of the trigger channel 23 in the base layer 14 as previously explained. Another benefit of increasing the emitter shunt density in proximity to the turn-on line is that it extends the switching time of the amplifying trigger action during VBo firing, thereby per-mitting the relatively high lateral resistance of the trigger channel itself to have more e~ffect on damping the internal discharge of the blocking junction capacitance.
An amplifying gate thyristor having an auxiliary emitter lSB of the relative dimensions shown in Figs. 5-6 is prone to be fired in the dv/dt mode at the auxiliary emitter junction J3'. To minimize this possibility, the pilot contact 22 is disposed in ohmic contact with a plurality of discrete areas of the base layer 14 under the auxiliary emitter layer llCU-4073 15B, whereby a plurality of metallic shunts 33 are provided across the junction J3' between the base and auxiliary emitter layers. As iæ shown in Fig. 5, the size and distribution pattern of the shunts 33 correspond to those of the shunts in the main auxiliary region 15A. More particularly, those shunts in the auxiliary emitter region that are closest to the edge of this region adjacent to the gate contact 21 (i.
e., the inside per~meter of the annular region 15B in the Fig. 5 embodiment) are arranged in a row paralleling that edge, and the shunt density in this inboard row is approxi-mately equal to the density of the shunts 32 in the first row of shunts in the main emitter layer 15A. Furthermore, the centers of the shunts in this inboard row are spaced from the edge of the auxiliary emitter region by a distance ap-proximately the same as the aforesaid distance X. By in-creasing the shunt density in the inboard row of the auxili-ary emitter its sensitivity to spurious gate current i~ de-sirably reduced.
While a preferred form of the invention has been ~, 20 shown and described by way of example, many modifications will occur to those skilled in the art. For example, all conducti-vity types and polarities shown in the drawings could be reversed. The thyristor could be provided with a side gate instead of (or in addition to) the center gate, in which case the turn-on line would effectively coincide with at least part of the outer perimeter of the main emitter region. Ei-ther visible or invisible light could be used as the gate current source. The invention could be embodied in a device having a planar type structure instead of the mesa type illus-trated in Fig. 6. Therefore the claims which conclude this specification are intended to cover all such modifications as fall within the true spirit and scope of the invention.

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An improved thyristor comprising:
(a) a semiconductor wafer having four layers of alternating conductivity type, the interface boundaries between adjacent layers forming three rectifying junctions;
(b) first and second metallic electrodes, respectively in ohmic contact with said first and fourth layers, for connecting the wafer to an external electric circuit; said first electrode also making contact with a plurality of discrete areas of said second layer thereby providing a plurality of metallic shunts across the recti-fying junction therebetween; and (c) means for triggering the tyristor from a relatively high impedance, non-conducting state to a low impedance state in which interelectrode current starts flowing along a pre-determined turn-on line of said first layer; wherein the improvement comprises:
(i) providing a first group of said shunts over substantially the whole area of the first layer in contact with said first electrode, said first group of shunts having substantially uniform spacing and density over said area; and (ii) providing a second group of said shunts across said rectifying junction in a row parallel to the turn-on line, between the turn-on line and the first group of shunts, the spacing between adjacent shunts of the second group being approximately one-half the spacing between adjacent shunts of the first group.

2. The device of claim 1 in which said turn on line is hexagonal.

3. The device of claim 1 in which said turn on line is circular.

4. The device of claim 3 in which said first group of metallic shunts are distributed in spaced annular rows which are concentric with said turn-on line, the centers of the shunts in adjacent rows being radially spaced by a predetermined distance and the centers of adjacent shunts in each of said annular rows being spaced apart by approx-imately said predetermined distance.

5. The device of claim 4 in which said row of second shunts is annular and the centers of said second group of shunts are radially spaced from said turn-on line by substantially less than said predetermined distance.

6. The device of claim 5 in which said first layer is annular and said circular turn-on line effectively coincides with the inside perimeter thereof.

7. The device of claim 1 in which said trig-gering means comprises a control electrode for connecting the second layer to a source of gate current, an auxiliary emitter layer having the same conductivity type as said first layer, said auxiliary emitter layer being laterally displaced with respect to said first layer between said control electrode and said electrode contacting the first layer, and a metallic pilot contact overlying said auxiliary emitter layer and an exposed surface of said second layer adjacent to said first layer.

8. The device of claim 7 in which said row of second shunts is spaced a predetermined distance from said turn-on line, and in which said pilot contact is in ohmic contact with a plurality of discrete areas of said second layer to thereby provide a plurality of metallic shunts across the recifying junction between said second layer and auxiliary emitter, those shunts in the auxiliary emitter that are closest to said control electrode being arranged in a row paralleling the edge of the auxiliary emitter that is adjacent to said control electrode and being spaced approximately said pre-determined distance from said edge, the spacing between adjacent shunts of said last-mentioned row being equal to the spacing of said row of second shunts in said first layer.