CA1038329A - Method of selectively depositing glass on semiconductor devices - Google Patents
Method of selectively depositing glass on semiconductor devicesInfo
- Publication number
- CA1038329A CA1038329A CA221,479A CA221479A CA1038329A CA 1038329 A CA1038329 A CA 1038329A CA 221479 A CA221479 A CA 221479A CA 1038329 A CA1038329 A CA 1038329A
- Authority
- CA
- Canada
- Prior art keywords
- glass
- insulating material
- areas
- coated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000151 deposition Methods 0.000 title claims abstract description 17
- 239000002245 particle Substances 0.000 claims abstract description 37
- 239000011810 insulating material Substances 0.000 claims abstract description 31
- 239000007788 liquid Substances 0.000 claims abstract description 31
- 239000000203 mixture Substances 0.000 claims abstract description 20
- 238000001035 drying Methods 0.000 claims abstract description 5
- 238000010304 firing Methods 0.000 claims abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 239000006185 dispersion Substances 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 239000003795 chemical substances by application Substances 0.000 claims description 18
- 229910052681 coesite Inorganic materials 0.000 claims description 17
- 229910052906 cristobalite Inorganic materials 0.000 claims description 17
- 229910052682 stishovite Inorganic materials 0.000 claims description 17
- 229910052905 tridymite Inorganic materials 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000007654 immersion Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000000843 powder Substances 0.000 description 9
- 238000003491 array Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- AJDIZQLSFPQPEY-UHFFFAOYSA-N 1,1,2-Trichlorotrifluoroethane Chemical compound FC(F)(Cl)C(F)(Cl)Cl AJDIZQLSFPQPEY-UHFFFAOYSA-N 0.000 description 6
- 239000000356 contaminant Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000011550 stock solution Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- CNPVJWYWYZMPDS-UHFFFAOYSA-N 2-methyldecane Chemical compound CCCCCCCCC(C)C CNPVJWYWYZMPDS-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- KZNICNPSHKQLFF-UHFFFAOYSA-N succinimide Chemical compound O=C1CCC(=O)N1 KZNICNPSHKQLFF-UHFFFAOYSA-N 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- PQUCIEFHOVEZAU-UHFFFAOYSA-N Diammonium sulfite Chemical compound [NH4+].[NH4+].[O-]S([O-])=O PQUCIEFHOVEZAU-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013019 agitation Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 150000008282 halocarbons Chemical class 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000003208 petroleum Substances 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229960002317 succinimide Drugs 0.000 description 1
- BDHFUVZGWQCTTF-UHFFFAOYSA-M sulfonate Chemical compound [O-]S(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-M 0.000 description 1
- 238000010345 tape casting Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- CHJMFFKHPHCQIJ-UHFFFAOYSA-L zinc;octanoate Chemical compound [Zn+2].CCCCCCCC([O-])=O.CCCCCCCC([O-])=O CHJMFFKHPHCQIJ-UHFFFAOYSA-L 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
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- H01L21/02145—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
METHOD OF SELECTIVELY DEPOSITING GLASS
ON SEMICONDUCTOR DEVICES
Abstract A method which comprises depositing a charge of a selected polarity on the areas coated with insulating material of a semiconductor device having areas of "bare"
semiconductor and areas coated with insulating material, immersing the charged device in a liquid composition comprising an insulating liquid and dispersed glass particles carrying a charge of selected polarity which is either the same as or opposite to the charge on the insulating material, such that glass particles deposit either on the semiconductor or on the insulating material, removing the glass-coated device from the liquid, drying and firing to fuse the glass particles on the device.
ON SEMICONDUCTOR DEVICES
Abstract A method which comprises depositing a charge of a selected polarity on the areas coated with insulating material of a semiconductor device having areas of "bare"
semiconductor and areas coated with insulating material, immersing the charged device in a liquid composition comprising an insulating liquid and dispersed glass particles carrying a charge of selected polarity which is either the same as or opposite to the charge on the insulating material, such that glass particles deposit either on the semiconductor or on the insulating material, removing the glass-coated device from the liquid, drying and firing to fuse the glass particles on the device.
Description
1038~29 , 1 Background of the Invention Although silicon dioxide has been generally used for passivating the exposed surfaces of silicon semiconductor devices, especially the exposed edges of PN junctions, additional protection has been found to be desirable in many cases. The additional protection is needed to give longer protection against atmospheric moisture and other contaminants, for example. It is also desirable, however, to achieve lower surface current leakage between regions of different conductivity types such as the base and collector regions of bipolar transistors.
Added protection against contaminants and decreased ; current leakage has been obtained by coating or encapsulating devices with various plastics and glasses. In the case of lS -coating or encapsulating with glass, which ls oiten required before encapsulation with plastic, it has been found most desirable to utilize dispersions of very small particle size glass in a carrier liquid to deposit coatings of glass particles on the device surfaces, and then to heat to a temperature just high enough to fuse the glass particles to form a continuous layer.
The glass which is used to passivate semiconductor devices must have a number of properties such as fusion temperature compatible with the semiconductor device, good adherence to the device surface, a temperature coefficient of expansion at least approximately matching that of the semiconductor, low porosity, and an absence of ingredients or contaminants that would adversely affect the electrical characteristics of the device.
A number of different methods have been used to _ 2 - `'-.
I deposit the glass particles. One of these methods is doctor blading a glass powder slurry over the surface of a semiconductor wafer having many devices built into it by well known diffusion techniques, and then evaporating the liquid. Another method is settling the glass particles out of a liquid dispersion onto the device surface.
The doctor blade method has several disadvantages.
It usually is a hand operation requiring much labor and only one side of the wafer can be done at a time. Since it involves mechanical scraping, much wafer breakage and other damage results. In addition, the method achieves selectivity only through utilizing certain surface topography, i.e., it is limited to deposition in recessed regions.
The settling method is time-consuming, wasteful of lS glass particles and is non-selective.
Another method which also has previously been used ls electrophoresis. In this method, the device (poled either positive or negative) is immersed in a dispersion of glass particles charged opposite to the device being coated and a current is passed through the dispersion. Glass can be deposited selectively only on the conductive parts of the device surface. Besides being unable to deposit glass selectively on insulating regions, another disadvantage of this method is that it is not satisfactory for depositing thick layers because of adherence problems. Further, to be selective, the process uses conductive liquids which are capable of dissolving more contaminants than non-conductive liquids do, and therefore these liquids are more likely to be sources of device contamination.
The present method is an improved, electrostatic 1~038329 1 method of depositing a glass coating on selected areas of a device having areas of "bare~ semiconductor and also areas coated with an insulating material. The method comprises depositing charges of selected polarity on the areas coated S with insulating material and then immersing the charged device in a liquid dispersion of glass particles which are charged either with the same polarity as or with polarity opposite to the charges on the insulating material. The glass particles deposit either on the "bare", uncoated areas or on the coated areas of the device depending upon polarity conditions chosên. The device is then removed from the liquid and, after drying, the glass particles are fused by ~iring. Relatively thick, adherent coatings of glass can be applied in a selective manner.
The Drawings FIGURE l is a cross section view through part of a semiconductor wafer having many transistors separated from each other by grooves;
FIGURES 2, 3 and 4 illustrate successive steps in applying one embodiment of the method of the invention to the wafer of FIGURE l;
FIGURES 5-8 illustrate steps in applying an alternative embodiment of the method to a semiconductor device wafer;
FIGURES 9-12 are section views of a different device and illustrate steps in coating the device by an embodiment of the methods of the invention;
FIGURE 13 is an end view of suitable charging apparatus for use in the present method, and FIGURE 14 is an elevation view of part of the I apparatus of FIGURE 13.
Description of Preferred Embodiments Although the present method lS applicable to making a number of different types of semiconductor devices, it will be illustrated, first, in connection with making a large number of bipolar transistors on a single semiconductor crystal slice or wafer.
As shown in FIGURE 1, a slice 2 of a single crystal semiconductor material, such as silicon, may have fabricated ; 10 therein by well known diffusion techniques or a combination o~ epitaxial growth and diffusion techniques, many transistors 4. Each transistor 4 has an emitter region 6 which may be of N conductivity type, for example, a base region 8 which may be of P conductivity type, and a collector region 10, which may be of N conductivity type. A layer 12 of an insulating material covers the top surface 14 of each transistor~
Another layer of insulating material 13 covers the bottom surface 15 of the slice. The emitter region 6 and base region 8 are separated by a PN junction 16. The base region 8 and the collector region 10 are separated by another PN
junction 18. Grooves 20 are provided in the form of a gridwork extending into the top surface 14 of the device array and below the PN junction 18 so that the grooves are on all 4 sides of each transistor 4. It is desirable to cover the exposed portions of the PN junctions with a dielectric material to reduce current leakage across the junctions and to prevent deterioration due to ambient or processing contaminants. It is much more economical to provide the necessary protective coating over the PN
junctions while the devices 4 are still a part of the 10383~9 1 original slicc 2 than it is to treat each individual device after it llaS been separated from the slice.
When grooves are etched into the silicon of a mesa type wafer, the SiO2 covering the wafer (if this is the insulating material) is first patterned into the groove geometry using standard lithographic techniques. Then the æilico1l is etched using the SiO2 as the pattern-de~ining mask. Bocause of etch undercutting, an overhanging shelf of SiO2 is formed. In depositing the glass by the method of the invention voids may be formed under the shelf which may lead to electrical degradation during further processing ~-steps. Thus, it is advantageous to remove this overhanging ; SiO2 before charging and glass deposition.
The removal may be accomplished in either of at least two u~ays. An oxide etch may be used by immersing the wafer long enough to remove the overhang. In this case a fraction of the thickness of the oxide on the mesa surface is removed, but this is not harmful. For example, a 3 min~lte etch in buffered HF solution purchased from the Transene Corporation was sufficient to remove a O.OOl" overhang while removing only about 3000 A o-f the original 12,000 A of Si02 on the mesa surface. Another procedure is to use ultrasonic energy to remove the overhang. For example, a Branson Model 41-4000 Ultrasonic Cleaner was used to remove the overhang in 30 seconds with water and with Freon TF in lO
seconds.
In accordance with one embodiment of the invention, the parts of the slice comprising "bare" silicon which are exposed within the grooves 20 are covered with a protective glass coating as follows. The slice 2 is placed in a corona 1 charging device which may consist of 2 parallel arrays of thin, vertically disposed wires held in an insulating frame.
The major surfaces of the slice should be carefully oriented so that they are parallel to the wire arrays. The wires may be 1.5 mil diameter tungsten wires spaced 0.5 inch apart.
The distance between the parallel arrays is such that when the semiconductor slice 2 is positioned between them, the wires typically are spaced 0.220 inch from the adjacent surfaces of the slice. The spacing of the wires from the surface to be charged can be used to vary the charge level on the slice, although it is usually desirable to charge the insulating region to saturation.
In order to achieve satisfactory charging results, it is desirable to use a charging apparatus that will permit lS accurate parallel and equidistant positioning of the surfaces of the wafer with respect to two sets of wires in the charging apparatus. A satisfactory charging apparatus is shown in FIGURES 13 and 14.
As illustrated in FIGURR 13, the charging apparatus 58 may comprise a base plate 60 having disposed thereon two frames 62 and 64 which may be made of an insulating material such as methylmethacrylate resin. The frames are accurately spaced on the base plate 60 so that they are facing each other. Each of the frames 62 and 64 has a pedestal member 2S 66 and 68 respectively, a panel 70 and 72, respectively, vertically mounted along one edge of the pedestal members 66 and 68, and a top plate 74 and 76, respectively, horizontally mounted on the tops of vertical panels 70 and 72 so that they extend parallel to the pedestal members 66 and 68.
10;~830 1 On each of the frames 62 and 64 is an array of wires 78 and 80, respectively. Each array consists of 9 wires spaced equidistant from each other and held under tensiOn in a vertical plane. One end of each wire in the arrays is attached to one of the pedestal members 66 and 68 adjacent its outer edge. The other end of each of the wires in the arrays 78 and 80 is attached to one end of tension spring 86. The other end of each tension spring 86 is attached to an adjusting screw 88. The adjusting screws 88 are threadedly mounted in buss bars 92 and 94 which are set into plastic blocks 82 and 84, respectively, which extend longitudinally along the outer edges of top plates 74 and 76, respectively.
The wires in the arrays 78 and 80 pass over the lS outer edges of top plates 74 and 76, respectively.
The buss bars 92 and 94 are connected to a high voltage source (not shown).
During the charging step, the wafer 2 is vertically held between the wire arrays 78 and 80 by a suspending means 20 96. The suspending means comprises 4 support posts 98, a pair of horizontal metal tracks 100 and 102j disposed parallel to and above the top plates 74 and 76, having smooth, sloping inner surfaces 104 and 106, respectively, and a wafer holder 108 (FIGURE 14).
The wafer holder 108 comprises a metal V-block 110 to the under side of which is fastened a pair of pivoted jaws 112 and 114. The jaw 112 has a grooved finger 116 at its lower end and the jaw 114 has similar spaced grooved fingers 118 and 120. The fingers 116, 118 and 120 are arranged to receive and hold vertical the wafer 2.
~ 8 --103~329 1 The V-block 110 has smooth sides which slope at an angle which is the same as the angle of the sloping surfaces 104 and 106 of the tracks 100 and 102. The V-block 110 is thus designed to ride in the tra~ks 100 and 102 and to make electrical contact therewith. The tracks are grounded.
During the charging step, the wafer holder is preferably moved back and forth along the tracks 100 and 102 at a speed of about 3 inches per second in order to charge the wafer s~.lrfaces uniformly.
A voltage of about 6200 volts negative is applied to the wires. Tlle-atmosphere is air or nitrogen but the relative humidity is controlled so that it is about 30% at 25 C if si~icon dioxide is the insulating material. The charging voltage preferably should be as high as possible without causing arcing since this has been found to give better edge definition of charge on the slice 2 and also provides a more uniform charge. The upper level of relative humidity permissible is a function of elapsed time between charging the surface of the slice and subsequent immersion in a glass dispersion. An elapsed time of one second has been used to advantage. If the time is very short, relative humidity may be higher since there will be less time for charge to leak away. Also, if the insulating material on which the charge is deposited is caused to be hydrophobic, 2S relative humidity can be higher. In fact, when using Waycoat SC 180 photoresist (Philip A. Hunt Chemical Corp.) for the insulatillg material, relative humidities of 65% and even higher can be used.
The wafer held in the wafer holder is thereby grounded by contact at the wafer edge and the slice is exposed g _ ~3~'. ' .
1 to the corona discharge for about 5 to 15 seconds. As indicated in FIGURE 2, this causes a layer 22 of negatively charged gaseous ions to deposit on the insulating layer 12 whlch is on the top surface 14 of the device array and a similar layer of ions 24 to deposit on the insulating layer 13 disposed on the bottom surface 15 of the slice 2.
The sign of the discharge may be either negative or positive depending on whether the glass particles to be deposited have a negative or positive charge in the liquid and whether the glass is to be deposited on the insulator layers 12 and 13, or on the "bare" exposed silicon. In the present example the corona charge is negative.
The gaseous ions 22 and 24 from the corona discharge arrive at the surfaces of the slice 2 and deposit on the surfaces of the lnsulating layers 12 and 13 (FIGURE
Added protection against contaminants and decreased ; current leakage has been obtained by coating or encapsulating devices with various plastics and glasses. In the case of lS -coating or encapsulating with glass, which ls oiten required before encapsulation with plastic, it has been found most desirable to utilize dispersions of very small particle size glass in a carrier liquid to deposit coatings of glass particles on the device surfaces, and then to heat to a temperature just high enough to fuse the glass particles to form a continuous layer.
The glass which is used to passivate semiconductor devices must have a number of properties such as fusion temperature compatible with the semiconductor device, good adherence to the device surface, a temperature coefficient of expansion at least approximately matching that of the semiconductor, low porosity, and an absence of ingredients or contaminants that would adversely affect the electrical characteristics of the device.
A number of different methods have been used to _ 2 - `'-.
I deposit the glass particles. One of these methods is doctor blading a glass powder slurry over the surface of a semiconductor wafer having many devices built into it by well known diffusion techniques, and then evaporating the liquid. Another method is settling the glass particles out of a liquid dispersion onto the device surface.
The doctor blade method has several disadvantages.
It usually is a hand operation requiring much labor and only one side of the wafer can be done at a time. Since it involves mechanical scraping, much wafer breakage and other damage results. In addition, the method achieves selectivity only through utilizing certain surface topography, i.e., it is limited to deposition in recessed regions.
The settling method is time-consuming, wasteful of lS glass particles and is non-selective.
Another method which also has previously been used ls electrophoresis. In this method, the device (poled either positive or negative) is immersed in a dispersion of glass particles charged opposite to the device being coated and a current is passed through the dispersion. Glass can be deposited selectively only on the conductive parts of the device surface. Besides being unable to deposit glass selectively on insulating regions, another disadvantage of this method is that it is not satisfactory for depositing thick layers because of adherence problems. Further, to be selective, the process uses conductive liquids which are capable of dissolving more contaminants than non-conductive liquids do, and therefore these liquids are more likely to be sources of device contamination.
The present method is an improved, electrostatic 1~038329 1 method of depositing a glass coating on selected areas of a device having areas of "bare~ semiconductor and also areas coated with an insulating material. The method comprises depositing charges of selected polarity on the areas coated S with insulating material and then immersing the charged device in a liquid dispersion of glass particles which are charged either with the same polarity as or with polarity opposite to the charges on the insulating material. The glass particles deposit either on the "bare", uncoated areas or on the coated areas of the device depending upon polarity conditions chosên. The device is then removed from the liquid and, after drying, the glass particles are fused by ~iring. Relatively thick, adherent coatings of glass can be applied in a selective manner.
The Drawings FIGURE l is a cross section view through part of a semiconductor wafer having many transistors separated from each other by grooves;
FIGURES 2, 3 and 4 illustrate successive steps in applying one embodiment of the method of the invention to the wafer of FIGURE l;
FIGURES 5-8 illustrate steps in applying an alternative embodiment of the method to a semiconductor device wafer;
FIGURES 9-12 are section views of a different device and illustrate steps in coating the device by an embodiment of the methods of the invention;
FIGURE 13 is an end view of suitable charging apparatus for use in the present method, and FIGURE 14 is an elevation view of part of the I apparatus of FIGURE 13.
Description of Preferred Embodiments Although the present method lS applicable to making a number of different types of semiconductor devices, it will be illustrated, first, in connection with making a large number of bipolar transistors on a single semiconductor crystal slice or wafer.
As shown in FIGURE 1, a slice 2 of a single crystal semiconductor material, such as silicon, may have fabricated ; 10 therein by well known diffusion techniques or a combination o~ epitaxial growth and diffusion techniques, many transistors 4. Each transistor 4 has an emitter region 6 which may be of N conductivity type, for example, a base region 8 which may be of P conductivity type, and a collector region 10, which may be of N conductivity type. A layer 12 of an insulating material covers the top surface 14 of each transistor~
Another layer of insulating material 13 covers the bottom surface 15 of the slice. The emitter region 6 and base region 8 are separated by a PN junction 16. The base region 8 and the collector region 10 are separated by another PN
junction 18. Grooves 20 are provided in the form of a gridwork extending into the top surface 14 of the device array and below the PN junction 18 so that the grooves are on all 4 sides of each transistor 4. It is desirable to cover the exposed portions of the PN junctions with a dielectric material to reduce current leakage across the junctions and to prevent deterioration due to ambient or processing contaminants. It is much more economical to provide the necessary protective coating over the PN
junctions while the devices 4 are still a part of the 10383~9 1 original slicc 2 than it is to treat each individual device after it llaS been separated from the slice.
When grooves are etched into the silicon of a mesa type wafer, the SiO2 covering the wafer (if this is the insulating material) is first patterned into the groove geometry using standard lithographic techniques. Then the æilico1l is etched using the SiO2 as the pattern-de~ining mask. Bocause of etch undercutting, an overhanging shelf of SiO2 is formed. In depositing the glass by the method of the invention voids may be formed under the shelf which may lead to electrical degradation during further processing ~-steps. Thus, it is advantageous to remove this overhanging ; SiO2 before charging and glass deposition.
The removal may be accomplished in either of at least two u~ays. An oxide etch may be used by immersing the wafer long enough to remove the overhang. In this case a fraction of the thickness of the oxide on the mesa surface is removed, but this is not harmful. For example, a 3 min~lte etch in buffered HF solution purchased from the Transene Corporation was sufficient to remove a O.OOl" overhang while removing only about 3000 A o-f the original 12,000 A of Si02 on the mesa surface. Another procedure is to use ultrasonic energy to remove the overhang. For example, a Branson Model 41-4000 Ultrasonic Cleaner was used to remove the overhang in 30 seconds with water and with Freon TF in lO
seconds.
In accordance with one embodiment of the invention, the parts of the slice comprising "bare" silicon which are exposed within the grooves 20 are covered with a protective glass coating as follows. The slice 2 is placed in a corona 1 charging device which may consist of 2 parallel arrays of thin, vertically disposed wires held in an insulating frame.
The major surfaces of the slice should be carefully oriented so that they are parallel to the wire arrays. The wires may be 1.5 mil diameter tungsten wires spaced 0.5 inch apart.
The distance between the parallel arrays is such that when the semiconductor slice 2 is positioned between them, the wires typically are spaced 0.220 inch from the adjacent surfaces of the slice. The spacing of the wires from the surface to be charged can be used to vary the charge level on the slice, although it is usually desirable to charge the insulating region to saturation.
In order to achieve satisfactory charging results, it is desirable to use a charging apparatus that will permit lS accurate parallel and equidistant positioning of the surfaces of the wafer with respect to two sets of wires in the charging apparatus. A satisfactory charging apparatus is shown in FIGURES 13 and 14.
As illustrated in FIGURR 13, the charging apparatus 58 may comprise a base plate 60 having disposed thereon two frames 62 and 64 which may be made of an insulating material such as methylmethacrylate resin. The frames are accurately spaced on the base plate 60 so that they are facing each other. Each of the frames 62 and 64 has a pedestal member 2S 66 and 68 respectively, a panel 70 and 72, respectively, vertically mounted along one edge of the pedestal members 66 and 68, and a top plate 74 and 76, respectively, horizontally mounted on the tops of vertical panels 70 and 72 so that they extend parallel to the pedestal members 66 and 68.
10;~830 1 On each of the frames 62 and 64 is an array of wires 78 and 80, respectively. Each array consists of 9 wires spaced equidistant from each other and held under tensiOn in a vertical plane. One end of each wire in the arrays is attached to one of the pedestal members 66 and 68 adjacent its outer edge. The other end of each of the wires in the arrays 78 and 80 is attached to one end of tension spring 86. The other end of each tension spring 86 is attached to an adjusting screw 88. The adjusting screws 88 are threadedly mounted in buss bars 92 and 94 which are set into plastic blocks 82 and 84, respectively, which extend longitudinally along the outer edges of top plates 74 and 76, respectively.
The wires in the arrays 78 and 80 pass over the lS outer edges of top plates 74 and 76, respectively.
The buss bars 92 and 94 are connected to a high voltage source (not shown).
During the charging step, the wafer 2 is vertically held between the wire arrays 78 and 80 by a suspending means 20 96. The suspending means comprises 4 support posts 98, a pair of horizontal metal tracks 100 and 102j disposed parallel to and above the top plates 74 and 76, having smooth, sloping inner surfaces 104 and 106, respectively, and a wafer holder 108 (FIGURE 14).
The wafer holder 108 comprises a metal V-block 110 to the under side of which is fastened a pair of pivoted jaws 112 and 114. The jaw 112 has a grooved finger 116 at its lower end and the jaw 114 has similar spaced grooved fingers 118 and 120. The fingers 116, 118 and 120 are arranged to receive and hold vertical the wafer 2.
~ 8 --103~329 1 The V-block 110 has smooth sides which slope at an angle which is the same as the angle of the sloping surfaces 104 and 106 of the tracks 100 and 102. The V-block 110 is thus designed to ride in the tra~ks 100 and 102 and to make electrical contact therewith. The tracks are grounded.
During the charging step, the wafer holder is preferably moved back and forth along the tracks 100 and 102 at a speed of about 3 inches per second in order to charge the wafer s~.lrfaces uniformly.
A voltage of about 6200 volts negative is applied to the wires. Tlle-atmosphere is air or nitrogen but the relative humidity is controlled so that it is about 30% at 25 C if si~icon dioxide is the insulating material. The charging voltage preferably should be as high as possible without causing arcing since this has been found to give better edge definition of charge on the slice 2 and also provides a more uniform charge. The upper level of relative humidity permissible is a function of elapsed time between charging the surface of the slice and subsequent immersion in a glass dispersion. An elapsed time of one second has been used to advantage. If the time is very short, relative humidity may be higher since there will be less time for charge to leak away. Also, if the insulating material on which the charge is deposited is caused to be hydrophobic, 2S relative humidity can be higher. In fact, when using Waycoat SC 180 photoresist (Philip A. Hunt Chemical Corp.) for the insulatillg material, relative humidities of 65% and even higher can be used.
The wafer held in the wafer holder is thereby grounded by contact at the wafer edge and the slice is exposed g _ ~3~'. ' .
1 to the corona discharge for about 5 to 15 seconds. As indicated in FIGURE 2, this causes a layer 22 of negatively charged gaseous ions to deposit on the insulating layer 12 whlch is on the top surface 14 of the device array and a similar layer of ions 24 to deposit on the insulating layer 13 disposed on the bottom surface 15 of the slice 2.
The sign of the discharge may be either negative or positive depending on whether the glass particles to be deposited have a negative or positive charge in the liquid and whether the glass is to be deposited on the insulator layers 12 and 13, or on the "bare" exposed silicon. In the present example the corona charge is negative.
The gaseous ions 22 and 24 from the corona discharge arrive at the surfaces of the slice 2 and deposit on the surfaces of the lnsulating layers 12 and 13 (FIGURE
2), The ions which deposit on the semiconducting surfaces are effectively neutralized, however, and do not form a surface charge on them. Although the "bare" silicon surfaces in the grooves 20 immediately acquire a very thin layer of oxide 26 having a thickness of about 20 angstroms when exposed to air, this layer 26 is so thin that it does not act like an insulating material toward the gaseous ions.
Therefore, a charged layer is not formed within the grooves 20. To hold a charge and also not be subject to having pinholes, the oxide should be at least about 1000 angstroms thick.
A suitable dispersion of glass particles is preferably prepared about a day prior to the charging step.
Some glasses suitable for passivating semiconductor devices 30 are No. 7723 of the Corning Glass Co., also IP 760 and . 10;~83Z9 1 IP 820 of the Innotech Co. Glass No. 77Z3 has the approximate composition: 30% PbO, 7% A12O3, 13% B2O3 and 50% SiO2. Glass IP 760 has the approximate composltion:
45.75% PbO, 2.65% A12O3, 1.60% ZnO, 10.75% B2O3 and 39.25%
SiO2. Glass IP 320 has the approximate composition: 50%
PbO, 10.1% A1203 and 39.9% SiO2. A11 percentages are by weiaht. As supplied, the IP glasses have about 75~ by weight of the glass below 12 ~ in size and about 25% below
Therefore, a charged layer is not formed within the grooves 20. To hold a charge and also not be subject to having pinholes, the oxide should be at least about 1000 angstroms thick.
A suitable dispersion of glass particles is preferably prepared about a day prior to the charging step.
Some glasses suitable for passivating semiconductor devices 30 are No. 7723 of the Corning Glass Co., also IP 760 and . 10;~83Z9 1 IP 820 of the Innotech Co. Glass No. 77Z3 has the approximate composition: 30% PbO, 7% A12O3, 13% B2O3 and 50% SiO2. Glass IP 760 has the approximate composltion:
45.75% PbO, 2.65% A12O3, 1.60% ZnO, 10.75% B2O3 and 39.25%
SiO2. Glass IP 320 has the approximate composition: 50%
PbO, 10.1% A1203 and 39.9% SiO2. A11 percentages are by weiaht. As supplied, the IP glasses have about 75~ by weight of the glass below 12 ~ in size and about 25% below
3 ~ in size.
The glass powder is dispersed in an insulating liquid containing a charging agent. A suitable insulating liquid is a halogenated hydrocarbon such as Genesolve D
(Allied Chemical Co.) or Freon TF (du Pont). Both of these are 1,1,2-trichloro-1,2,2-trifluorethane. another suitable 1S insulating liquid is Isopar G (Exxon Corp.). This is a mixture of liquid isopara$finic hydrocarbons and may also be termed a narrow-cut Isoparaffinic hydrocarbon fraction of . very high purity. Genesolve D and Freon TF are preferred . carrier liquids because they are denser than Isopar, evaporate rapidly, and are not flammable. When using Freo~
TF, the evaporation is so rapid that the wafer may be placed in the furnace at once. When using Isopar G it is .
necessary to allow the wafer to dry for several minutes before placing it in the furnace.
The charging agent may be a surfactant such as one ~ of those given in the Table below.
Table Sign of charge induced Surfactant on glass particles 1. Zirconium octoate 1- 2. Petroleum magnesium su].fonate~ (shifts to -. .after several days) 3. Petrolcum barium sulfonate - ~.
The glass powder is dispersed in an insulating liquid containing a charging agent. A suitable insulating liquid is a halogenated hydrocarbon such as Genesolve D
(Allied Chemical Co.) or Freon TF (du Pont). Both of these are 1,1,2-trichloro-1,2,2-trifluorethane. another suitable 1S insulating liquid is Isopar G (Exxon Corp.). This is a mixture of liquid isopara$finic hydrocarbons and may also be termed a narrow-cut Isoparaffinic hydrocarbon fraction of . very high purity. Genesolve D and Freon TF are preferred . carrier liquids because they are denser than Isopar, evaporate rapidly, and are not flammable. When using Freo~
TF, the evaporation is so rapid that the wafer may be placed in the furnace at once. When using Isopar G it is .
necessary to allow the wafer to dry for several minutes before placing it in the furnace.
The charging agent may be a surfactant such as one ~ of those given in the Table below.
Table Sign of charge induced Surfactant on glass particles 1. Zirconium octoate 1- 2. Petroleum magnesium su].fonate~ (shifts to -. .after several days) 3. Petrolcum barium sulfonate - ~.
4. Zinc octoate -
5. *OLO~ 1200 (Chevron, Inc.)
6. Pctroleum ammonium sulfonate +
7. N-alkylpiporizene monalkenyl +
succinimide
succinimide
8. RNHCH2CH2NH2 where R is polybutyl io radical *OLOA ].200 has the structural formula:
H O - H
/ I 1 ~1 I C - N R =- î ~
1S H - C - C H H H H H H - I - H n2 H O
with nitrogen 2.10% by weight and alkalinity value of 43.
With certain lots of IP 820 glass it has been found advantageous to use about 5 minutes of ultrasonic agitation with power input of 100 watts in the glass dispersion to break up agglomerates of fine particles. If this is not-done the agglomerates tend to give a bumpy appearance to the deposited glass, and, more seriously, sometimes stick to regions where no glass is desired.
. 25 For use in the following examples a stock solution is prepared by (1) dissolving 100 g OLOA1200 in 100:ml Freon TF and (2) adding 8 ml of this solution to 392 ml of Freon TF.
Example 1 To deposit IP 760 glass on power transistor wafers of the mesa structure, the mesa surfaces are given a double ~ 10383Z9 l coat of phot:oresist havillg a total thickness of 5 ~. Glass is to be deposited within the grooves as described above.
A mix-ture ol' glass powder is prepared by adding 7 ml of the stock solution to 450 ml of Freon, then adding 4 ~ of glass powder and shaking 2 minutes. This is permitted to stand for at least one day to stabilize it.
Deposition is carried out by charging the wafer with a negative corona and immersing in a Pyrex beaker containing the above mixture for 6 seconds. The contents of the beaker are stirred at moderate speed while the glass is depositing.
As shown in FIGURE 3, a layer of glass 28 deposits in the grooves 20 but not on the insulating ].ayers 12 and 13.
After the glass is deposited, volatile material (including photoresist) is burlJed off at about 525 C and the glass i8 then fused to form a layer 28' (FIGURE 4).
After fusing, the layer of glass 28' is about 40 ~ thick.
Example 2 In this example, IP820 glass is deposited on thyristor wafers (not shown) having a mesa structure.
Grooves are formed on both surfaces of the wafer so that there are mesa structures on both sides. The mesas are coated with about 1.2 ~ of SiO2.
A dispersion of glass powder is made up by adding lO ml of the stock solution to 400 ml of Freon, then adding 8 g of glass powder and shaking for 2 minutes.
After allowing the glass dispersion to stand for one day, deposition of the glass is carried out as in Example 1 except that the charged wafers are immersed in ~i ,, I the glass mixture for 10 seconds. After deposition, the volatile material is permitted to evaporate off and the glass is fused.
Samples made as in this example had excellent junction coverage with a layer of fused glass about 30 thick. Electrical tests of the collector-base junction showed breakdown voltage in excess of 1000 V, leakage currents o~ about 4 ~ A at room temperature and about 38 A at 100 C.
_xample 3 Sometimes it is desirable to passivate a semiconductor device with a glass that is selected because it has a temperature coefficient of expansion closely matching that of the semiconductor. Such a glass may contain boron and may require such a high fusion temperature that the doping pattern of the silicon may be affected. In such cases it is desirable to deposit the glass on a layer-of SiO2 instead of directly on the silicon, to shield the silicon from the doping effect of the glass.
In this example, (FIGURE 5) the wafer 2 has a coating 30 of 8000 A thickness of SiO2 present only in the grooves 20. This can be accomplished by conventional masking techniques. The wafer also (inherently, because of exposure to air) has a very thin coating of oxide 31 on the top mesa surface and a similar coating of oxide 33 on the bottom surface. The coated wafer is then subjected to a positive corona discharge in dry air (relative humidity 27%). This lays down a layer of positive gaseous ions 32 (FIGURE 6) on the SiO2 layer 30 within the grooves 20, No charge is deposited on the very thin oxide layers 31 and 33.
1 A mixture is made up of 4.5 ml of the above descri~ed stock solution of solvent and charging agent added to 300 ml of Freon. To this solution is added 9 g of Corning No~ 7723 glass powder and the mixture is shaken for 2 ~ninutes to disperse the powder.
The charged wafer is immersed in the above dispersion for 10 seconds which causes a layer of glass particles 34 to deposit only on the SiO2 layers 30 (FIGURE 7).
The wafer is removed from the dispersion, the residual volatila material is burned off and the glass is fused to form a layer 34' (FIGURE 8). Thickness of the fused layer is about 35 ~.
Example 4 In this example, a layer of glass is deposited in the grooves o$ a mesa type diode wafer to increase the breakdown voltage of the diodes.
As shown in FIGURE 9, a silicon diode wafer 36 has a P type lower layer 38 and an N type upper layer 40 separated by a PN junction 41. A gridwork of grooves 43 is formed in the wafer 36. The grooves extend into the P type layer 38.
A relatively thick layer 42 of SiO2 covers the . silicon in the grooves and the wafer is charged with a positive corona so that a layer of positively charged ions forms on the SiO2 surfaces as in Example 3. The to? mesa surfaces 46 acquire a very thin oxide layer 48 and the bottom surface 50 Oe the wafer acquires a very thin layer of oxide 52 but these thin layers do not act as charge storage layers. A dispersion made up by adding 10 ml of ~'~', , .
1 the stock solution of carrier and charging agent to 400 mlof Freon and then adding 6 g of IP760 glass powder and shaking for 2 minutes is used to deposit the glass.
The charged wafer is immersed in this dispersion for 6 seconds while the mixture is stirred. The wafer is then removed with a coating of glass particles 44 deposited only on the thick SiO2 surfaces 42. The volatile material is allowed to evaporate off and the glass is fused to form a layer 44' (FIGURE 10). The charging and glass deposition process is then repeated to deposit a second layer of glass particles 54 on top of the first layer of glass 44' (FIGURE
11) and this second layer is fused so that the two layers form a composite layer of glass 56 (FIGURE 12). In the glass dispersion which is used to deposit the second layer of glass particles, the glass particles carry a charge opposite to the charge on the first gla~s layer.
Breakdown voltages of up to 1700 V have been measured on these diodes at room temperature.
Dry nitrogen as well as dry air can be used as the ambient for the corona charging step and dry nitrogen is somewhat preferable since ozone production by the corona is much less and since slightly higher voltages can be used without arcing.
The quantity of charging agent used in the carrier liquid mixture should be just enough to develop the same sign of charge on every glass particle if the heaviest deposit of glass is desired. Adding more than the optimum amount introduces excess ions which decrease the amount of glass that can be deposited since the excess ions neutralize the charge on the insulating regions of the wafer. However, ~ 16 -10383~9 1 the quantity of charging agent used can be utilized to vary the thickness of the glass deposit.
In determining how much charging agent to use, a suitable glass dispersion is prepared, a small amount of charging agent is added and a slice with a pattern of charges is immersed in the dispersion. If the amount of charging agent is too small, glass will deposit on both charged insulating areas and uncharged areas. Another quantity of glass dispersion is then taken and a somewhat larger amount of charging agent is added. Again, a slice with a pattern of charges on it is dipped in the dispersion and the results noted. Charging agent is added in small incremental steps to fresh portions of dispersion until the glass deposits only on either the charged areas or on the uncharged areas, depending on charge polarities. Once the proper amount o~ charging agent has been found for a given weight of a certain glass in Freon it is possible to approximate the charging agent required for other quantities of glass by making a linear approximation.
Although silicon dioxide and photoresists have been mentioned in the examples as suitable insulating layer materials, other insulating materials conventionally used on semiconductor devices, such as silicon nitride, may al90 be used. If the insulating material is organic (as in Example l), it must be removed before fusion of the glass particles.
The method can also be used to simultaneously deposit glass particles on the insulator-coated areas of one side of a semiconductor slice (where the insulator is inorganic) and on the "bare" semiconductor areas on the opposite side of the slice. This can be done by depositing RCA 66975 ~ .
~0~329 l charges of opposite polarities on insulator-coated areas on the opposite sides and then immersing the slice in a glass dispersion.
.
_ _ -:
,, .
., .
~: :
~0 . .
.
:, 25 --1~ 2~ 3~ 4~ 5~ 6~ 7~ 8 ~ Reg~stexed Tr~demarks ~;
H O - H
/ I 1 ~1 I C - N R =- î ~
1S H - C - C H H H H H H - I - H n2 H O
with nitrogen 2.10% by weight and alkalinity value of 43.
With certain lots of IP 820 glass it has been found advantageous to use about 5 minutes of ultrasonic agitation with power input of 100 watts in the glass dispersion to break up agglomerates of fine particles. If this is not-done the agglomerates tend to give a bumpy appearance to the deposited glass, and, more seriously, sometimes stick to regions where no glass is desired.
. 25 For use in the following examples a stock solution is prepared by (1) dissolving 100 g OLOA1200 in 100:ml Freon TF and (2) adding 8 ml of this solution to 392 ml of Freon TF.
Example 1 To deposit IP 760 glass on power transistor wafers of the mesa structure, the mesa surfaces are given a double ~ 10383Z9 l coat of phot:oresist havillg a total thickness of 5 ~. Glass is to be deposited within the grooves as described above.
A mix-ture ol' glass powder is prepared by adding 7 ml of the stock solution to 450 ml of Freon, then adding 4 ~ of glass powder and shaking 2 minutes. This is permitted to stand for at least one day to stabilize it.
Deposition is carried out by charging the wafer with a negative corona and immersing in a Pyrex beaker containing the above mixture for 6 seconds. The contents of the beaker are stirred at moderate speed while the glass is depositing.
As shown in FIGURE 3, a layer of glass 28 deposits in the grooves 20 but not on the insulating ].ayers 12 and 13.
After the glass is deposited, volatile material (including photoresist) is burlJed off at about 525 C and the glass i8 then fused to form a layer 28' (FIGURE 4).
After fusing, the layer of glass 28' is about 40 ~ thick.
Example 2 In this example, IP820 glass is deposited on thyristor wafers (not shown) having a mesa structure.
Grooves are formed on both surfaces of the wafer so that there are mesa structures on both sides. The mesas are coated with about 1.2 ~ of SiO2.
A dispersion of glass powder is made up by adding lO ml of the stock solution to 400 ml of Freon, then adding 8 g of glass powder and shaking for 2 minutes.
After allowing the glass dispersion to stand for one day, deposition of the glass is carried out as in Example 1 except that the charged wafers are immersed in ~i ,, I the glass mixture for 10 seconds. After deposition, the volatile material is permitted to evaporate off and the glass is fused.
Samples made as in this example had excellent junction coverage with a layer of fused glass about 30 thick. Electrical tests of the collector-base junction showed breakdown voltage in excess of 1000 V, leakage currents o~ about 4 ~ A at room temperature and about 38 A at 100 C.
_xample 3 Sometimes it is desirable to passivate a semiconductor device with a glass that is selected because it has a temperature coefficient of expansion closely matching that of the semiconductor. Such a glass may contain boron and may require such a high fusion temperature that the doping pattern of the silicon may be affected. In such cases it is desirable to deposit the glass on a layer-of SiO2 instead of directly on the silicon, to shield the silicon from the doping effect of the glass.
In this example, (FIGURE 5) the wafer 2 has a coating 30 of 8000 A thickness of SiO2 present only in the grooves 20. This can be accomplished by conventional masking techniques. The wafer also (inherently, because of exposure to air) has a very thin coating of oxide 31 on the top mesa surface and a similar coating of oxide 33 on the bottom surface. The coated wafer is then subjected to a positive corona discharge in dry air (relative humidity 27%). This lays down a layer of positive gaseous ions 32 (FIGURE 6) on the SiO2 layer 30 within the grooves 20, No charge is deposited on the very thin oxide layers 31 and 33.
1 A mixture is made up of 4.5 ml of the above descri~ed stock solution of solvent and charging agent added to 300 ml of Freon. To this solution is added 9 g of Corning No~ 7723 glass powder and the mixture is shaken for 2 ~ninutes to disperse the powder.
The charged wafer is immersed in the above dispersion for 10 seconds which causes a layer of glass particles 34 to deposit only on the SiO2 layers 30 (FIGURE 7).
The wafer is removed from the dispersion, the residual volatila material is burned off and the glass is fused to form a layer 34' (FIGURE 8). Thickness of the fused layer is about 35 ~.
Example 4 In this example, a layer of glass is deposited in the grooves o$ a mesa type diode wafer to increase the breakdown voltage of the diodes.
As shown in FIGURE 9, a silicon diode wafer 36 has a P type lower layer 38 and an N type upper layer 40 separated by a PN junction 41. A gridwork of grooves 43 is formed in the wafer 36. The grooves extend into the P type layer 38.
A relatively thick layer 42 of SiO2 covers the . silicon in the grooves and the wafer is charged with a positive corona so that a layer of positively charged ions forms on the SiO2 surfaces as in Example 3. The to? mesa surfaces 46 acquire a very thin oxide layer 48 and the bottom surface 50 Oe the wafer acquires a very thin layer of oxide 52 but these thin layers do not act as charge storage layers. A dispersion made up by adding 10 ml of ~'~', , .
1 the stock solution of carrier and charging agent to 400 mlof Freon and then adding 6 g of IP760 glass powder and shaking for 2 minutes is used to deposit the glass.
The charged wafer is immersed in this dispersion for 6 seconds while the mixture is stirred. The wafer is then removed with a coating of glass particles 44 deposited only on the thick SiO2 surfaces 42. The volatile material is allowed to evaporate off and the glass is fused to form a layer 44' (FIGURE 10). The charging and glass deposition process is then repeated to deposit a second layer of glass particles 54 on top of the first layer of glass 44' (FIGURE
11) and this second layer is fused so that the two layers form a composite layer of glass 56 (FIGURE 12). In the glass dispersion which is used to deposit the second layer of glass particles, the glass particles carry a charge opposite to the charge on the first gla~s layer.
Breakdown voltages of up to 1700 V have been measured on these diodes at room temperature.
Dry nitrogen as well as dry air can be used as the ambient for the corona charging step and dry nitrogen is somewhat preferable since ozone production by the corona is much less and since slightly higher voltages can be used without arcing.
The quantity of charging agent used in the carrier liquid mixture should be just enough to develop the same sign of charge on every glass particle if the heaviest deposit of glass is desired. Adding more than the optimum amount introduces excess ions which decrease the amount of glass that can be deposited since the excess ions neutralize the charge on the insulating regions of the wafer. However, ~ 16 -10383~9 1 the quantity of charging agent used can be utilized to vary the thickness of the glass deposit.
In determining how much charging agent to use, a suitable glass dispersion is prepared, a small amount of charging agent is added and a slice with a pattern of charges is immersed in the dispersion. If the amount of charging agent is too small, glass will deposit on both charged insulating areas and uncharged areas. Another quantity of glass dispersion is then taken and a somewhat larger amount of charging agent is added. Again, a slice with a pattern of charges on it is dipped in the dispersion and the results noted. Charging agent is added in small incremental steps to fresh portions of dispersion until the glass deposits only on either the charged areas or on the uncharged areas, depending on charge polarities. Once the proper amount o~ charging agent has been found for a given weight of a certain glass in Freon it is possible to approximate the charging agent required for other quantities of glass by making a linear approximation.
Although silicon dioxide and photoresists have been mentioned in the examples as suitable insulating layer materials, other insulating materials conventionally used on semiconductor devices, such as silicon nitride, may al90 be used. If the insulating material is organic (as in Example l), it must be removed before fusion of the glass particles.
The method can also be used to simultaneously deposit glass particles on the insulator-coated areas of one side of a semiconductor slice (where the insulator is inorganic) and on the "bare" semiconductor areas on the opposite side of the slice. This can be done by depositing RCA 66975 ~ .
~0~329 l charges of opposite polarities on insulator-coated areas on the opposite sides and then immersing the slice in a glass dispersion.
.
_ _ -:
,, .
., .
~: :
~0 . .
.
:, 25 --1~ 2~ 3~ 4~ 5~ 6~ 7~ 8 ~ Reg~stexed Tr~demarks ~;
Claims (14)
- The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows l. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas, comprising:
depositing charges of a particular polarity on said insulating material, immersing the charged device in a liquid composition comprising an insulating carrier liquid and dispersed glass particles carrying a charge of particular polarity such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, drying and firing the coated device at a temperature high enough to fuse said glass. - 2. A method according to claim 1 in which said charges on said insulating material have the same sign as said charges on said glass particles so that said glass particles are deposited on said bare exposed areas of semiconductor.
- 3. A method according to claim 1 in which said semiconductor is silicon and said insulating material is silicon dioxide.
- 4. A method according to claim 2 in which said insulating material is a photoresist.
- 5. A method according to claim 1 in which said insulating material is silicon nitride.
- 6. A method according to claim 1 in which said insulating liquid is 1,1,2-trichloro-1,2,2-trifluoroethene.
- 7. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent is zirconium octoate.
- 8. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent has the structural formula:
where with nitrogen 2.10% by weight and alkalinity value of 43. - 9. A method according to claim 1 in which said glass comprises about: 30% PbO, 7% Al203, 13% B2O3 and 50% SiO2 by weight.
- 10. A method according to claim 1 in which the relative humidity of the ambient to which the device is exposed is controlled to a sufficiently low value to prevent discharging of the charged surface of said insulating material between charging and immersion in the liquid composition.
- 11. A method according to claim 10 in which said relative humidity is about 25 - 30%,
- 12. A method according to claim 1 in which said gaseous ions and said glass particles are charged with opposite polarities such that the glass particles deposit on the insulating material.
- 13. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with an insulating material, of a semiconductor device having both types of said areas, comprising:
subjecting said device to a gaseous corona discharge such that ions of a particular polarity deposit on said insulating material, immersing the charged device in a liquid composition comprising an insulating carrier liquid having suspended therein a dispersion of glass particles and an ionizable agent capable of imparting a net electrical charge of particular polarity to the glass particles, such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, and firing the coated device at a temperature high enough to fuse said glass. - 14. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas, comprising:
depositing charges of a particular polarity on said insulating material, immersing the charged device in a liquid composition comprising an insulating carrier liquid and dispersed glass particles carrying a charge of a particular polarity such that the glass particles deposit selectively on either said bare exposed areas of semiconductors or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, drying and firing the coated device at a temperature high enough to fuse said glass, cooling the glass-coated device, depositing charges of a particular polarity on the glass-coated surface, immersing the charged device in another glass dispersion in which the glass particles carry a charge having a polarity opposite to that on the glass coating first deposited, until a layer of glass particles deposits on said glass coating, removing the device from said dispersion, drying and firing the coated device a second time at a temperature high enough to fuse said glass.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US462492A US3895127A (en) | 1974-04-19 | 1974-04-19 | Method of selectively depositing glass on semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1038329A true CA1038329A (en) | 1978-09-12 |
Family
ID=23836608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA221,479A Expired CA1038329A (en) | 1974-04-19 | 1975-03-05 | Method of selectively depositing glass on semiconductor devices |
Country Status (13)
Country | Link |
---|---|
US (1) | US3895127A (en) |
JP (1) | JPS5760773B2 (en) |
BE (1) | BE826941A (en) |
BR (1) | BR7501335A (en) |
CA (1) | CA1038329A (en) |
DE (1) | DE2513945A1 (en) |
FR (1) | FR2268357B1 (en) |
GB (1) | GB1464682A (en) |
IN (1) | IN143919B (en) |
IT (1) | IT1044487B (en) |
NL (1) | NL7503711A (en) |
SE (1) | SE407427B (en) |
YU (1) | YU77175A (en) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7500492A (en) * | 1975-01-16 | 1976-07-20 | Philips Nv | PROCESS FOR THE MANUFACTURE OF SEMI-GUIDE DEVICES, IN WHICH A GLASS COVER IS APPLIED, AND SEMI-GUIDE DEVICES MANUFACTURED ACCORDING TO THIS PROCESS. |
JPS5393783A (en) * | 1977-01-26 | 1978-08-17 | Nec Home Electronics Ltd | Mesa type semiconductor device |
IN147578B (en) * | 1977-02-24 | 1980-04-19 | Rca Corp | |
IN147572B (en) * | 1977-02-24 | 1980-04-19 | Rca Corp | |
DE2739762C2 (en) * | 1977-09-03 | 1982-12-02 | SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg | Process for the passivation of semiconductor bodies |
US4218493A (en) * | 1977-12-02 | 1980-08-19 | The Continental Group, Inc. | Electrostatic repair coating |
US4235645A (en) * | 1978-12-15 | 1980-11-25 | Westinghouse Electric Corp. | Process for forming glass-sealed multichip semiconductor devices |
FR2466859A1 (en) * | 1979-10-05 | 1981-04-10 | Thomson Csf | SILICON NITRIDE MASKING AND GLAZING GLASSIVATION METHOD AND SEMICONDUCTOR COMPONENTS OBTAINED |
US4296370A (en) * | 1979-10-11 | 1981-10-20 | Rca Corporation | Method of detecting a thin insulating film over a conductor |
DE3138340A1 (en) * | 1981-09-26 | 1983-04-14 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Process for producing planar components |
US4551353A (en) * | 1981-12-30 | 1985-11-05 | Unitrode Corporation | Method for reducing leakage currents in semiconductor devices |
JPS58173745U (en) * | 1982-05-17 | 1983-11-19 | 国産電機株式会社 | Engine-driven generator rotation speed control device |
DE3373594D1 (en) * | 1982-12-22 | 1987-10-15 | Nec Corp | Method of producing electrostrictive effect element |
US5342563A (en) * | 1991-11-22 | 1994-08-30 | The Lubrizol Corporation | Methods of preparing sintered shapes and green bodies used therein |
US5268233A (en) * | 1991-11-22 | 1993-12-07 | The Lubrizol Corporation | Methods of preparing sintered shapes and green shapes used therein |
US6780491B1 (en) * | 1996-12-12 | 2004-08-24 | Micron Technology, Inc. | Microstructures including hydrophilic particles |
US6448190B1 (en) | 1999-05-21 | 2002-09-10 | Symetrix Corporation | Method and apparatus for fabrication of integrated circuit by selective deposition of precursor liquid |
US6613695B2 (en) * | 2000-11-24 | 2003-09-02 | Asm America, Inc. | Surface preparation prior to deposition |
US6960537B2 (en) * | 2001-10-02 | 2005-11-01 | Asm America, Inc. | Incorporation of nitrogen into high k dielectric film |
US20030118947A1 (en) * | 2001-12-04 | 2003-06-26 | Primaxx, Inc. | System and method for selective deposition of precursor material |
US6945121B2 (en) | 2002-12-04 | 2005-09-20 | Kimberly, Clark Worldwide, Inc. | Apparatus for simulating a dynamic force response |
US7598576B2 (en) * | 2005-06-29 | 2009-10-06 | Cree, Inc. | Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices |
US7855401B2 (en) * | 2005-06-29 | 2010-12-21 | Cree, Inc. | Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides |
US7525122B2 (en) * | 2005-06-29 | 2009-04-28 | Cree, Inc. | Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides |
US8557702B2 (en) | 2009-02-02 | 2013-10-15 | Asm America, Inc. | Plasma-enhanced atomic layers deposition of conductive material over dielectric layers |
US9812338B2 (en) | 2013-03-14 | 2017-11-07 | Cree, Inc. | Encapsulation of advanced devices using novel PECVD and ALD schemes |
US8994073B2 (en) | 2012-10-04 | 2015-03-31 | Cree, Inc. | Hydrogen mitigation schemes in the passivation of advanced devices |
US9991399B2 (en) | 2012-10-04 | 2018-06-05 | Cree, Inc. | Passivation structure for semiconductor devices |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2966429A (en) * | 1956-08-31 | 1960-12-27 | Gen Electric | Method of and apparatus for making printed circuits |
US3280019A (en) * | 1963-07-03 | 1966-10-18 | Ibm | Method of selectively coating semiconductor chips |
US3400000A (en) * | 1965-05-17 | 1968-09-03 | Du Pont | Surface modified electrostatic enamel powders and method |
US3629086A (en) * | 1969-12-12 | 1971-12-21 | Ford Motor Co | Anodic deposition of ceramic frit with cationic envelope |
US3642597A (en) * | 1970-03-20 | 1972-02-15 | Gen Electric | Semiconductor passivating process |
JPS5339442B2 (en) * | 1972-03-02 | 1978-10-21 | ||
JPS551703B2 (en) * | 1972-07-07 | 1980-01-16 |
-
1974
- 1974-04-19 US US462492A patent/US3895127A/en not_active Expired - Lifetime
-
1975
- 1975-02-10 IN IN232/CAL/75A patent/IN143919B/en unknown
- 1975-03-05 CA CA221,479A patent/CA1038329A/en not_active Expired
- 1975-03-05 SE SE7502450A patent/SE407427B/en unknown
- 1975-03-06 BR BR1730/75A patent/BR7501335A/en unknown
- 1975-03-25 FR FR7509253A patent/FR2268357B1/fr not_active Expired
- 1975-03-26 JP JP50037392A patent/JPS5760773B2/ja not_active Expired
- 1975-03-27 NL NL7503711A patent/NL7503711A/en not_active Application Discontinuation
- 1975-03-27 YU YU00771/75A patent/YU77175A/en unknown
- 1975-03-29 DE DE19752513945 patent/DE2513945A1/en not_active Withdrawn
- 1975-04-04 IT IT67867/75A patent/IT1044487B/en active
- 1975-04-10 GB GB1474375A patent/GB1464682A/en not_active Expired
- 1975-07-16 BE BE154554A patent/BE826941A/en unknown
Also Published As
Publication number | Publication date |
---|---|
YU77175A (en) | 1983-04-27 |
SE407427B (en) | 1979-03-26 |
US3895127A (en) | 1975-07-15 |
BR7501335A (en) | 1976-03-09 |
FR2268357B1 (en) | 1979-03-09 |
SE7502450L (en) | 1975-10-20 |
BE826941A (en) | 1975-07-16 |
GB1464682A (en) | 1977-02-16 |
DE2513945A1 (en) | 1975-10-30 |
FR2268357A1 (en) | 1975-11-14 |
IN143919B (en) | 1978-02-25 |
JPS5760773B2 (en) | 1982-12-21 |
NL7503711A (en) | 1975-10-21 |
IT1044487B (en) | 1980-03-20 |
JPS50137684A (en) | 1975-10-31 |
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