CA1038081A - Paper currency validator - Google Patents

Abstract

PAPER CURRENCY VALIDATOR

Abstract of the Disclosure: Bill-driving members move a bill past a sensing device and also into a position which is sensed by position-sensing means. A timing circuit will reverse that motor and cause those bill-driving members to move that bill back outwardly if that sensing device does not provide a proper signal, and if those position-sensing devices do not provide a proper signal, within a predetermined time.

Description

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PAPER CURRENCY VALIDATOR

SPE~IFICATION
This invention relates to improvements in paper currency validators. More parkicularly, this invention relates to improvements in paper currency validators wherein the movement of an authentic bill past a sensing device will develop signals having a predetermined frequency.
It is, therefore, an object of the present inven-tion to provide an improved paper currency validator which develops a predetermined frequency as an authentic bill is moved past a sensing element.
' 10 Prior paper currency validators, which moved bills through them at predetermined rates to develop signals of predetermined ~requencies, used synchronous motors to drive those bills; and they used adjustable components in the fre-quency-sensing circuits thereof to make the center frequen-cies of those frequency-sensing circuits match those predeter-mined frequencies. However, adjustable inductors are less stable and more expensive than fixed inductors of comparable quality, and adjustable capacitors are less stable and more expensive than fixed capacitors of comparable quality; and hence paper currency validators which use Erequencywsensing circuits that utilize adjustable components are less stable and more expensive than would be a paper currency validator which used a frequency sensing circuit that utilized fixed components. The present invention provides a paper currency ..

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validator which uses a frequency-sensing circuit that utilizes fixed components and thereby provides a very stable and inexpensive paper currency validator. It is, therefore, an object of the present invention to provide a paper currency validator which uses a frequency-sensing circuit that utilizes fixed components.
The paper currency validator of the present inven-tion is ablé to use a frequency-sensing circuit which uti-lizes fixed components because it utilizes an adjustable speed D.C. motor that has the speed thereof closely regu-lated. That adjustable speed D.C. motor is adjustecl to drive the vertical grid lines in the portralt back~round of a bill past the air gap of a magnetic head at a rate which will en~
able that magnetic head to develop signals which have a fre-quency that matches the frequency of the frequency-sensing circuit of that paper currency validator. The present in-vention thus makes the speed of the adjustable speed D.C.
motor thereof a function of the frequency of the frequency-sensing circuit thereof rather than vice versa; and/ in doing so, that paper currency validator makes it possible to use a much more stable but much less expensive frequency-sensing circuit, and also makes it possible to use a much smaller ; and much less expensive motor. It i5~ therefore, an object of the present invention to provide a paper currency validator with an adjustable speed D.C. motor which can move bills through that paper currency validator at a rate which is a function of the center frequency of a frequency-sensing cir-cuit that uses fixed components.

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The D.C. motor of the paper currency validator o~
the present invention causes bill-driving members to move a bill past a bill-actuated switch and then past a magnetic head; and a timing circuit will reverse that motor, to cause those bill-driving members to move that bill back outwardly of that paper currency validator, if that magnetic head does not coact with the frequency-sensing circuit to develop a validation signal. within a predetermined length of time.
In doing so, that timing circuit keeps the bill from moving so far inwardly of the paper currency validator that the bill-driving members would be unable to move that bill back out-wardly of that paper currenc~ validator. ~lso, in doing 90, that timing circui~ llmits tho l~ngth of time durin~ which that bill is adjacent that magnetic head, and thereby corres-pondingly reduces the likelihood that a person could manipu-late that bill and cause it to coact with that magnetic head to develop signals of the required frequency. It is, there-', fore, an object of the present invention to provide a paper currency validator wherein a motor causes bill-driving members to move a bill past a bill-actuated switch and then past a mag-netic head, and wherein a timing circuit will reverse that : motor, to cause those bill-driving members to move that bill back outwardly of that paper currency validator, if that mag-netic head does not coact with the frequency-sensin~ circuit ~: to develop a validation signal within a predetermined length of time.

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The motor of the paper currency validator of the present invention causes the bill-driving members thereof to move at a fixed rate of speed; and, once that motor has gotten those bill-dr~ving members up to that rate of speed, it will draw an approximately constant value of current.
That motor and those bill-driving members will resist any efforts of a person to retard or stop the movement of a bill inwardly of the paper currency validator; and, in doing so, that motor will draw increased values of current. A sub-circuit senses the value of the current drawn by the motor;and, if a person attempts to retard or halt the inward move-ment of a hill, that sub-circuit will respond to the conse-quent increase in the value o~ the motor current to inhibit the development of a validation signal. This means that if a person was able to retard or stop the inward movement of a bill, that person would not be able to effect the unauthor-ized vending of a product from the vending machine, to which the paper currency validator is connected, because the cur-rent-sensing sub-circuit would prevent the development of a validation signal. It is, therefore, an object of the present invention to provide a paper currency validator with a current-sensing sub-circuit which will respond to undue increases in the value of the motor current to inhibit the development of a validation signal.
The paper currency validator of the present inven-tion ~as a bill-actuated start switch, a bill-actuated se-quence switch and a bill-actuated exit switch; and those bill-actuated switches are normally connected to ~he rest of the circuitry of that paper currency validator.
However, as soon as a validation signal is developed, all of those bill-actuated switches are immediately isolated from the rest of that circuitry; and this is desirable, because it will keep any ~urkher closing or opening of any of those switches from affecting that circuitry. In this way, any undesirable effects on the operation of the rest of that circuitry, which are due to "contact bounce" or to the deliberate closing and open-ing of any of those switches, will be obviated. It i5 thereore, an object of the present invention to pro-vide a paper currency validator which has bill-actuated switches that are initially connected to the rest of the circuitry of that paper currency validator but which are immediately isolated from the res-t of that circuitry as soon as a validation signal is developed.
If a person inserts a short length of a bill into the paper currency validator of the present inven-tion, attaches a tape, thread or other "tail" to a bill,disconnects and then reconnects the line cord of the paper currency validator, or otherwise attempts to obtain an improper operation o that paper currency validator, the motor o that paper currency validator will reverse and thereby cause the bill-driving members to move any inserted bill or the like back outwardly o that paper currency validator. In addition, that paper currency ~L~3~
validator will automatically cancel any validation signal which was previously developed as the cropped bill or tail-equipped bill was moved inwardly of that paper currency validator. In this way, the present in-vention returns all cropped bills and tail-equipped bills -- so other persons can subsequently insert proper bills; and it also automatically cancels any validation signal which that cropped bill or tail-equipped bill might have developed. It is, therefore, an object of the present invention to provide a paper currency vali-dator which can return all cropped bills or tail-equipped bills ~y re~er~ing the motor thereof, and which will automatically cancel any validation signal which that cropped bill or tail-equipped bill might have developed.
The paper currency validator of the present in-vention disposes one magnetic head so it senses the ver-tical grid lines in one quadrant of the portrait back-ground of a bill and disposes a second magnetic head so it senses the vertical grid lines in the diagonally-displaced quadrant of that portrait background. In addi-tion, that paper currency validator will provide a vali-dation signal only if both of those magneti.c heads sim-ultaneously sense vertical grid lines of predetermined spacing within those diagonally displaced quadrants of the portrait background. By disposing the two magnetic heads so they must sense vertical grid lines in diagon-ally-displaced quadrants of the portrait background of ~3~

a bill, the paper currency validator of the present invention avoids the development of a validation sig-nal in the event a person inserts just the upper half, just the lower half, just the left-hand half, or just the right-hand half of a bill. By requiring the two magnetic heads to simultaneously sense vertical grid lines of predetermined spacing within the diagonally-displaced quadrants of the portrait background of each bill, the paper currency validator avoids the cost and space of the sub-circuit which would be needed to hold a first frequency-init.iaked signal until a seaond ~re-quenc~-initiated signal was dev~lop~d. Xt is, there-;~ fore, an object of the present invention to provide a paper currency validator which disposes one magnetic : head so it will sense vertical grid lines in one quad-rant of the portrait background of a bill, to mount a second magnetic head 50 it will sense vertical grid lines in the diagonally-displaced quadrant of that por-trait background, and to develop a validation signal only if those magnetic heads simultaneously sense vertical grid l.ines of pre-determined spacing within those dia-gonally-displaced quadrants.
The paper cu.rrency validator of the present invention disposes some bill-driving members thereof immediately outwardly of a magnetic head thereof, and provides a sub-circuit which will reverse the motor the.reof if the leadiny edge of any bill does not move a fLxad distance inwardly of that magnetic head within a predetermined length of time.
The bill-driving members are ~paced so close to that magnetic head that aven if no portion of that bill is able to pass by that magnetic head -- and hence substantially all portions of the length o that bill become wrinkled and crumpled up ad~acent that magnetic head, those bill-driving members will still be in engagement with the trailing edge o~ that bill.
The sub-circuit will promptly reverse the motor and cau~e the bill~d~iving members to move the bill ba~k outwardly o~ the paper currency validator --thereby clearing the paper currency validator 90 further bills can be accepted by it. That sub-circuit will reverse the motor and cause the bill-driving members to mave the bill back outwardly of the paper currency validator before those bill-driving members wo~ld have time to tear or otherwise degrade the bill.
It is, therefore, an ob~ect of the present invention ; to provide a paper currency validator which disposes some bill-driving member 9 thereof immediately out-wardly of a magnetic head thereof and whiah provides a sub-aircuit that will reverse the motor thereof ~if the leading edge of a bill doe~ not move a p.re-determined distance inwardly of ~hat magnetic head within a predetermined length o~ time.

',;~J'~ 0 This invention consists of a validator which c~mprises document-moving members that move a documant inwardly of that validator, a sensing device that responds to the inward move.ment of an authentic document relative thereto by the document~moving members to develop a signal, position-sensing means that respond to a document and that senses whan the document-moving members move a document inwardly to a predetermined position within the paper currency validator, a timing cirauit that responds ~o the sensing by th~ po~ition-sensing means o~ khe inward movement o~ a document to initiate a time period o~
predeterm~ned duration, and mean~ to reverse the direction of movement of those document-moving members and thereby move that document outwardly of the validator if the sensing device does not develop the signal ~efore the end of that time period.
This invention consists of the validator of the immediately preceding paragraph wherein the po~ition-sensing means senses the inward movement of the leading edge of the document and wherein the sensing device senses a portion of the document which i9 located rearwardly of the leading edge o~ that document.

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This invention con~is~s of the validator o the second immediately-preceding paragraph wherein the timing circuit includes a capacitor which experiences a given change in the charge therein during th~ tlme period, and wherein an opposita change in the charge in that capacitor occurs, when the sensing device develops the signal, to keep the means rom reversing the direction of movement of the document-moving members.
Thi~ invention consi~t~ oE the validator o~ the thlrd imm~diately-preacding parag~aph Wh~x~ln the t~ming circuit includes a capaaitor which experiences a given change in the charge therein during the time pe.riod, wherein an opposite change in the charge in said capacitor occurs, when tha sensing device develops the signal, to keep the means from reversing the direction of movement of the document-moving member~, wherein the means includes a control element with a threshold level, and wherein the means includes a Zener device that requires the voltage across the capaciitor to exceed the thrashold level of the control element by a fixad amount be~ore the aontrol element can be actuated.

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This invention con~ists of a validator which comprises document-moving membe~ that move a document inwardly of the validator, a sensing device that re~ponds to the inward movement of an authentic document relative thereto by the document-moving members to develop a signal, position-sensing means that responds to a document and that senses when the document moving members move a document inwardly to a predetermined position within the paper currency validator, a timing circuit that responds to khe ~ensing by the position-sensing means o~ the i~ward movement of a document to initia~e a ~ime period o~ predetermined duration~ and means ~o rever~e the direction of movement of the document-moving members and thereby move the document outwardly of the validator if the sensing device does not develop the 9 ignal before the end of the time pariod, an output circuit, a switch that normally can initiate operation o the sensing device and thereby normally enable thP output circuit to develop an output 9 ignal, and a circuit that responds to the development of the first signal to efectively i301ate the ~witch from the sensing device.

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Thi~ invention consi~ts of the validator of the immediately-precediny paragraph wherein an electric motor can provide relative movement between the document and the sensing device, wherein the switch can normally initiate opera~ion of the electric motor, and wherein the responsive circuit effectively isolates the switch rom the electric motor whereby it effectively isolates the switch from the sensing device.
This invention consists o a validator which comprlses document-moving members that move a documenk inwardly of the validator, a ~en~ing device that responds to the inward movement of an authentic document relative thereto by the document-moving member to develop a signal, position-sensing means that respoAds to a doaument and that senses when the document-moving members move a document inwardly to a predetermined position within the paper currency validato~, a timing circuit that responds to the sensing by the position-sensing : means of the inward movement of a document to imiti-ate a time period of predetermined duration, means to reverse the direction o~ movement of the document-moving members and thereby move the document outwardly of the validator if the sensi~g device does not davelop the ~ignal before the end of the time period, . ~;( ~ -lOD-103B~l the document-moving members being adap~ed to move the document inwardly beyond the sensing device, and fuxther means to determine whether the document-moving members have moved the document inwardly beyond the sensing device, the reversing mean~
reversing the direction of movement Oe the document-moving members if the further means determines that the document-moving members hav~ not moved the document inwardly beyond the sensing deviae, the document-moving members providing gripping forces immediately outwardly o~ th~ sensing device to enable the doaume~t-gripplng member~ to ~e ~n regL~ter ~th and to grip the trailing portion of a document which had the majo~ portion of the length thereo~ wrin~led and crumpled up against the sensing device while the document-moving members were moving the document toward the sensing device.
This invention consists of the validator of the imm~diately-preceding paragraph wherein the further means includ:~s a bill-actuated sensing member that senses the inward movement of the leading ~: edge of the document.

10E.

This invention cons ists of the validator of the second immediately-preceding paragraph whe~ein the timing circuit will cause the reversing means to reverse the direction of movement of the document-moving members if the further means does not, within a pre-set len~th o time, determine that the document-moving members have moved the document inwardly beyond the sensing device.
~ his invention consists o~ the validator of the third immediately-preceding paragraph wherein the document-moviny members are pulley-driven belts, and wherein at least one pulley ~or each belt is dls~
posed immediately outwardly o the sensing device.
This invention consists of the validator o the ourth immediately-preceding paragraph wherein the sensing device must directly engage the document as it senses the document, and wherein the leading edge of the document must force its way between the sensing device and a pressure-applying element which is in register with the sensing device.
This invention consi~ts of a validator which compri~es document-moving members that move a document inwardly o~ the validatorJ a sensin~ device that respond~ to the inward movement of an authentic document relative thereto by the document-moving members to develop a signal, ~ lOF

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position-sensing mQans that responds to a doaument and that sense when the document-moving members move a document inwardly to a predetermined position within the paper currency validator, a timing circuit that responds to the sensing by the position-sensing means of the inward movement of a document to initi-ake a time period of predetermined duration, means to reverse the direction of movement o~ the document-moving members and thereby move the document out-wardly of the validator if the sensing deviae does not deve~op the signal before the end of the time period, urther poslkion-sensing means that sen~e~
when the doaumenk ~ moved urther inward~y to a second p~edetermined posit~on within ~he paper currency validator, the sensing device being located inter-mediate the irst and the further position-s~nsing means and responding to the inward movement of a authentic document relative thereto by the document-moving members to develop a signal, the reversing means 2Q reversing the direction of movement of the document-moving members and thereby moving the document out-wardly of the validator i~ the further position-sensing means does not sense the inward movement o the document baore the end o the time period.

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This invention consists of a validator which compr ises document-moving members that move a document inwardly of the validator, a sensing device that responds to the inward movement of an authentic document relative thereto by the document-moving members to develop a ~ignal having a given frequency, position-sensing means that responds to a document and that senses when the document-moving members move a document inwardly to a predetermined position within the paper currency validator, a timing circuit that responds to the ~ensing by the position-senslng means o the inward movement Oe a document to lnltiate a time period o predetermined duration, means to reverse the direction of movement of the document-moving members and thereby move the document out-wardly of the validator if the sensing device does not develop the signal before the end of the time period and a frequen~y-sensing circuit which has the e~sential elements thereof fixed in nature rather than adjustable in nature, whereby the requency-sensing circuit has greater stability and is les~ expansive than a comparable frequency-sensing circuit which has the ess&ntial elements thereoE adjustable in nature, the essential elements of the reguency-sensing circuit helping establi~h and maintain a pre-determined aenter frequency for the requency-sensing circuit, and a driving means ~or the document-moving members that has a speed-adjusting sub-circuit which lOH.

permits the rate of the relative movement to be adjusted to cause the given frequency of the signal to be sufficiently close to the.predetermined center fre~uency to enable the frequency-sensing circuit to respond to the signal.
This invention consist~ of the validator of the immediately-preceding paragraph wherein the driving means includes an adjustable speed D.C.
motor and a feedback loop that keeps the adjusted speed of the D.C. motor substantially constant.
Thls invention consists of khe validator of the second immediately-p.receding paragraph wherein the driving means includes an adjustable sp~ed ~.C.
motor and an amplitude-responsive control circuit which is part o a feedback loop that keeps the adjusted speed of the D.C. motor ~ubstantially constant, and wherein a feedback generator ~upplies feedback to the amplitude-responsive con~rol circuit which has an amplitude that varies wikh the ~peed of the D.C.
motor.
This invention consists of ~he validator of the third immediately-preceding paragraph wherein the driving means includes an adjustable speed D.C.
motor and an amplitude-responsive control cirauit which is part of a feedback loop that keeps the adjusted speea of the D.C. motor substantially constant, wherein a ~eedback generator supplies feedback to the .
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amplitude-responsive control circuit which has an amplitude that varies with the speed o~ the DoC, motor, wherein the speed-adjusting sub-aircuit includes an adjustable impedance to adjust thc effective value of the feedback~ and wherein the speed-adjusting sub-circuit develops a reference and compares the ef~ective value of the feedback with the reference to produce an error signal which is proportional to any variation between the actual speed and the desired speed o the D.C. motor.
This invenkion consists o the validator of the æourth immediatel~-preceding paragraph~ n oneo~
essential element~ o~ the ~re~uenay-ssnslng circuit i9 a fixed value inductor, wherein another of the essential elements o the frequency-~ensing circuit i~ a ixed value capacitor, and wherein the ~ixed value inductor and the ixed value capacitor are components o a tuned circuit.
Other and further objects and advantages of the present invention should become apparent from an examination of the drawing and accompanying description.

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In the drawing and accompanying description a preferred embodiment of the present invention is shown and describ~d but it is to be understood that the drawing and accompanying description are for the pur-pose of illustration only and do not limit the inven-tion and that the invention will be defined by the append-ed claims.
Brief Description of the Drawing: In the drawing, Fiy. 1 is a perspective view of one preferred embodiment o paper currency validator that is made in accordance with the principles and teachings of the pre-sent invention, E'ig. 2 is a partially-broken elevational view of the front of the paper currency validator of Fig. 1, Fig. 3 is an elevational view of the rear of the paper currency validator of Fig. 1, Fig. 4 is a sectional view through the paper currency validator of Fig. 1, and it is taken along the plane indicated by the line 4-4 in Fig~ 2, Fig. 5 is another sectional view through the paper currency validator of Fig. 1, and it is taken along the plane indicated by the line 5-5 in Fig. 2, Fig. 6 is a bottom view of the cover and asso-ciated parts of the paper currency validator of Fig. 1, and it is taken along the plane indicated by the line 6-6 in Fig. 3, E'ig. 7 is a partially broken-away, plan view of the paper currency validator of Fig. 1 with the ~3~
cover and associated parts removed, and it is taken along the plane indicated by the line 7-7 in Fig. 5, Fig. 8 is a bottom view of a portion of the paper currency ~alidator of Fig. l, and it is taken along the plane indicated by the line 8-8 in Fig. 5, Fig. 9 is a sectional view through one o the pressure rollers, and is an end elevational view of one of the magnetic heads, o the paper currency validator of Fig. 1, and it is taken along the plane indicated by the line 9-9 in Fig. 10, Fig. 10 is a side elevational view of the mag-netic head and of the pressure roller shown in Fig. 9, The diagram at the right of Fig. lO shows the manner in which Figs. 11, 12 and 13 can be associated either with Fig. 14 or with Fig. 15, Fig. ll is a schematic diagram of part of the overall circuitry of the said one preferred embodiment of paper currency validator, Fig. 12 is a schematic diagram of another part of that overall circuitry, Fig. 13 is a schematic diagram of a further part of that overall circuitry, Fig. 14 is a schematic diagram o the remain-ing part of that overall circui~ry, and Fig. 15 is a schematic diagram o a sub-cir-cuit which can be substituted for the sub~circuit shown in Fig. 14.

-Description of the Preferred Embodiment:
Referring to the drawing in detail, the numeral 30 generally d~notes one preferred embodiment of paper currency validator that is made in accordance with the principles and teachings of the present invention.
The numeral 32 denotes a platform which extends out-wardly from khe front of the paper currency validator 30; and that plat~orm will receive the leading edge of each bill which is to be tested by that paper currency validator. Flanges 34 and 36, of generally triangular configurationl extend upwardly from the sides o~ the plat-form 327 and that plat~or~ has an upwardly-inclined inner end 38 which merges into a platen 40 o~ rectangular con-figuration as shown by Figs. 4 and 5. An elongated ~lange 42 extends downwardly rom each of the elongated sides of the platen 40; and the numeral 44 denotes ears which ex-tend laterally outwardly from the front ends of the flanges 42. The numeral 45 denotes the trailing edge of the platen 40; and, as indicated by Figs. 4 and 5, that tra~ing edge inclines downwardly and then terminates in a vertically-directed lip. As indicated by Fig. 7, the platen 40 has three rectangular slots 46, 48 and 50 in alignment with each other adjacent one side thereof; and that platen has rectangular slots 56, 58 and 60 in align-ment with each other adjacent the opposite side thereof.
The slot 56 is in register with the slot 46, the slot 58 is in register with the slot 48, and the slot 60 is 1~3~
in register with the slot 50; and the rear ends of the slots 50 and 60 are cut away, as shown by Fig. 7. The platen 40 also has a narrow elongated slot 52 therein which has semi-circular ends; and ~hat slot is located between the slots 46 and 56 but is closer to the slot 46 than it is to the slot 56. A similar slot, not shown, also is located between the slots 46 and 56, but it is closer to the slot 56 than it is to the slot 96. The numeral 54 denotes a slot in the platen 40 which is adjacent the trailing edge 4S of that platen; and that slot is closer to the slot 60 than it is to the slot 50.
The platen 40 has two additional slots, not shown; and one of those slot~ accommodates the upper por~ion of a roller 102 while the other of those s~ots accommodates the upper portion of a roller 114. Those rollers are in-dicated by solid lines in Fig. 5 and by dotted lines in Fig. 7.
The numeral 62 denotes a headed pin which has the shank thereof fixedly secured to the left-hand flange ~:
42 of the platen 40, as the paper currency validator is viewed in Fig. 2. As shown by Figs. 4, 5 and 7, that pin is adjacent the front of that paper currency validator.
The numeral 64 denotes an elongated pivot which extends between, and which is supported by openings in, the down-wardly-directed flanges 42 on the platen 40; and that pivot is disposed inwardly of the headed pin 62. The : numeral 66 denotes a headed pin which can be identical to 14.

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the headed pin 62, and that headed pin has the shank thereof fixedly secured to the left-hand flange 42 of the platen 40. The headed pin 66 is close to the rear of the paper currency validator, as shown by Figs. 4 and 5. A headed pin 68 has the shank thereof secured to the right-hand flange 42 of the platen 40, as the paper currency validator is viewed in Fig. 2; and that headed pin is in register with the headed pin 62. A
further headed pin, not shown, is secured to that right-hand flange; and that headed pin is in register with the headed pin 66.
The numeral 70 denotes a leaf-type spring whiah is bent so the right-hand end thereof inalines upwardly and to the right in Fig. 4 to bear against the under sur-face of the platen 40. That spring also is bent to have a downwardly-opening saddle, to have an elongated portion which inclines upwardly and to the left in Fig. 7 from that saddle, and to have a bifurcated left-hand end with fingers that define an upwardly-opening saddle. The num-erals 72, 74,76 and 78 denote springs which can be iden-tical to the spring 70; and, as indicated by Figs. 4 and 5, the spring 72 is adjacent the front of the platen 40 and the spring 74 is adjacent the trailing edge 45 of that platen. The spring 76 i9 in register with the spring 72, as indicated by Fig. 2: and the spring 78 is in reg-ister with the spring 74, as indicated by Fig. 3. A
further spring, not shown, i9 in register with the spring 15.

70. The downwardly-opening saddles of the springs 72, 74 and 76 telescope down over, and are supported by, the headed pins 62, 66 and 68, respectively; and the down-wardly-opening saddles of the spring 70 and of its coun-terpart telescope down over, and are supported by, the opposite ends of the pivot 64, while the downwardly-opening saddle of the spring 78 telescopes down over, and is supported by, the counterpart of headed pin 66.
A short pivot 80 is supported by the upwardly-opening saddle which is defined by the fingers at the bifurcated end of the spring 72; and that pivot rotat-ahly supports a roller 82. ~ similar pi~ot 8~ i~ support-; ed by the upwardly-op~ning saddle wh~ch .~s defined by the fingers at the biurcated end of the spring 70; and that pivot rotatably supports a roller 86. Another similar pivot 88 is supported by the upwardly-opening saddle which is defined by the fingers at the bifurcated end of the spring 74; and that pivot rota~ably supports a roller 90.
The nu~eral 92 denotes a roller which is rotatably mount-ed on a pivot, not shown, that is supported by the up-wardly-opening saddle which is defined by the fingers at the bifurcated end of the spring 76. The numeral 93 denotes a roller which is in register with the roller 86 and which is held by a ~hort pivot, not shown, that is supported by the upwardly-opening saddle which is de-fined by the fingers at the bifurcated end of the sprin~, not shown, which is the co~mterpart of the spring 70.

16.

The numeral 94 denotes a short pivot which is held by the upwardly-opening saddle which is defined by the fingers at the bifurcated end o~ the spring 78, as shown by Fig. 3; and a roller 96 is rotatably mounted on that pivot. As shown by Fig. 7, the upper portions of the rollers 82, 86 and 90 are disposed~ respectively, within the slots 46, 48 and 50 in the platen 40; and the upper portions of the rollers 92, 93 and 96 are disposed, respectively, within the slots 56, 58 and 60 in that platen. As indicated by Fig. ~, the springs 70, 72, 74, 76 and 78 and the spring, not shown, which i9 the coun-terpart of spring 70 urge the ~olle~s 86, ~2, 90, 92, 96 and 93, respectively, upwardly relative to the platen 40.
However, those springs can yield to permit those rollers to be moved downwardly.
The numeral 98 denotes an arm which has a hub that encircles the pivot 64, as indicated by Fig. 8, A
pivot 100 is fixedly secured to the outer end of the arm 100, and that pivot rotatably supports the roller 102.
~ 20 As shown by Fig. 9, the opening through that roller has ;~ a frusto-conical portion 104 and a frusto-conical por-tion 106. Those frusto-conical portions enable the rol-ler 102 to tilt relative to the axi~ o~ the pi~ot 100;
and a C-washer 103 holds that roller against accidental separation from that pivot. The numeral 110 denotes an arm which has a hub that also encircles the sha~t 6~;
and, as indicated by Fig. 8, the hubs of the arms 98 and 1~3~
100 confront each other and space those arms apart.
pivot 112 is fixedly secured to the outer end of the arm 110; and that pivot rotatably supports the roller 114. The opening through the roller 114 is defined by two frusto-conical portions in the same manner in which the opening through the roller 102 is defined by two frusto-conical portions. A C-washer 108 is mounted on the pivot 112, and it prevents accidental separation of the roller 114 from that pivot. A torsion spring 116 encircles the hubs of the arms 98 and 110; and one end ; of that torsion spring is hooked through an opening in the arm 98, while the other end of that torslon ~pring is hooked throu~h an opening in the arm 110. That tor-sion spring urges both the roller 102 and the roller 114 upwardly relative to the openings, not shown, which are provided in the platen 40 in register with those rollers.
However, that torsion spring can yield to permit those rollers to be moved downwardly relative to that platen.
The numeral 118 denotes an upper platen which normally is disposed in parallel relation with, and in -~
close proximity to, the platen 40. The platen 118 has downwardly-directed flanges 120 at its sides thereof; and each of those flanges has a downwardly-opening slot 122 adjacent the forward end thereof. Those slots are dimen-sioned and disposed to accommodate the outwardly-extend-ing ears 44 at the front ends of the flanges 42 on the lower platen 40. The numeral 124 denotes the semi-~ - \

cylindrical leading edge of the platen 118; and that semi-cylindrical leading edge is disposed forwardly of the upwardly~inclined rear portion 38 of the platform 32, as indicated by Figs. 4 and 5. That semi-cylindri-cal leading edge will coact with the upwardly-inclined rear portion 38 of the platform 32 to provide a desired smoothing and flattening out of any longitudinally-extending wrinkles, creases or folds in bills which are introduced into the paper currency validator 30. The platen 118 has an upwardly-inclined trailing edge 126, as indicated by Figs. 3-5.
An elongated slot 128 which has semi-circular ends is provided in the platcn 118 adjacent one side of that platen; and that slot overlies the rollers 82, 86 and 90. That slot extends from a point which is slightly outward of the roller 82 to a point which is slightly in-ward of the roller 90. A similar elongated slot 130 is provided in the upper platen 118 adjacent the opposite side of that platen; and that slot overlies the rollers 92, 93 and 96. The slot 130 extends from a point which is sli~htly outward of the roller 92 to a point which is slightly inward of the roller 96. The numeral 132 de-notes a narrow elongated slot in the platen 118 which has the same configuration as the slot 52 in the platen 40;
a~d those slots will be in vertical registry whenever those platens are in the positions shown by Figs. 4 and 5.
The numeral 134 denotes a slot in the platen 118 which is 19 .

identical to the slot 132; and that slot will be in vertical registry with the slot in the platen 40 which is identical to the slot 52 but which is closer to the slot 56 than it is to the slot 46. The numeral 136 denotes a slot which is generally in registry with the slot 54 in the platen 40; and that slot is closer to the slot 130 than it is to the slot 128. Two additional slots, nok shown, are provided in the platen 118; and one of those slots is in register with the roller 102, while the other of those slots is in register with the roller 114. Those two additional slots are shorter than, but are wiaer than, the rollers 102 and 114. The platen 118 also has two openings, not shown, which accommodate the lower ~aces o~ ma~n~tic headg 208 and 210; and ~hose openings are in register with the rollers 10~ and 114.
Whenever the platens 40 and 118 are in the positions shown by Figs. 4 and 5, the torsion spring 116 will urge the upper portions of the rollers 102 and 114 against the air gaps of the magnetic heads 208 and 210, respectively. If, for any reason, the axis of the pivot 100 is not precisely parallel to the air gap of the magnetic head 208, the frusto-conicalportions which define the opening through the roller 102 will enable the portion of that roller which engages that magnetic head to respond to the force which is applied by the spring 116 to move into pr~cise parallelism with that air gap. Similarly, if, for any reason, the axis of the pivot 112 is not precisely para-llel to the air gap of the magnetic head 210, the frusto-20.

~31~
conical portions which define the opening through theroller 114 will enable the portion of that roller which engages that magnetic head to respond to the force which is applied by the spring 116 to move into precise para-llelism with that air gap. This is important; because it enables the rollers 102 and 114 to assure full line contact between inserted bills and the air gaps of the magnetic heads 208 and 210 -- even where a light pres-sure torsion spring 116 is used to reduce the resistance which the rollers 102 and 114 will offer to the leading edges of inserted bills.
The numeral 140 denotes a cover ~or the p~per currency v~lidator; and that cover has downwardly-directed flanges 142 at the sides thereof. Each of the flanges 142 has a lateral offset therein, as shown by Figs. 1-3; and the cover 140 pre~erably is coextensive with the upper platen 118, as indi.cated by Figs. 4 and 5.
The numeral 144 denotes a switch bracket which is secured to the cover 140, as shown by Fig. 5; and that switch bracket holds a switch 146 adjacent the front of the pla-ten 118. The numeral 148 denotes a sturdy but thin ac-tuator for the switch 146; and that actuator has a lead-ing edge 150 and a trailing edge 152 which extend down-wardly through the slots 132 and 52, respectively, in the platens 118 and ~0. As indicated by Fig. 5, the lead-ing edge 150 is essentially straight, and it inclines down-wardly ~rom the upper left to the lower right whenever the ~3~

actuator 148 is in its normal position. The trailing edge 152 is convex, and it inclines downwardly from the upper riyht to lower left whenever the actuator 148 is in its normal position. The configurations and inclina-tions of the leading and trailing edges 150 and 152, res-pectively, of the switch actuator 148 enables the lead-ing edge and trailing edge, respectively, of a bill to engage the leading edge 150 and the trailing edge 152 and easily raise that actuator upwardly out of the slot 52 in the platen 40. As a result, the switch actuator 148 permits relatively ree movement of bills inwardly and outwardly of the paper currency validatox 30.
'rhe numeral 154 denotes a second s~tch bracket which is secured to the cover 140; and that switch bra-cket supports a switch 156. The numeral 158 denotes the actuator of the switch 156; and that actuator has a convex leading edge 159 which inclines downwardly from upper left to lower right in Fig. 5. That actuator has a trailing edge 161 which is straight and which inclines downwardly from upper right to lower left in Fig. 5. The configurations and inclinations of the leading and trail-ing edges 159 and 161, respectively, of the switch actu-ator 158 enable the leading edge and trailing edge, res-pectively, of a bill to engage the leading edge 159 and the trailing edge 161 and easily raise that actuator up-wardly out of the slot in the platen 40 which is in reg-ister with the opening 134 in the platen 140. As a re-sult, the actuator 158 permits relatively ~ree movement of bills inwardly and outwardly of the paper currency validator 30.
The numeral 160 denotes a third switch bracket which is secured to the cover 140; and that switch bra-cket is adjacent the rear of that cover. That switch bracket supports a switch 162; and that switch has an actuator 164 with a leading edge 166 and a trailing edge 168. The leading edge 166 is essentially straight, and it inclines downwardly from upper left to lower right in 10 Fig. 5; and that leading edge will respond to the inward movement of a bill to move upwardly out of the slot 5~ in the platen 40. The trailing edge 168 of the actuator 164 is generally convex in configuration, but it is ~uite short; and that trailing edge normally is disposed an appreciable distance below the lower ace o:E the platen 40. As a result, the trailing edge of a bill will not nor-mally engage the trailing edge 168 of the actuator 164 once that trailing edge has moved inwardly beyond that trailing edge of that actuator. If a person were to at-20 tempt to pull a bill outwardly of the paper currency vali-dator 30, after the trailing edge of that bill has been moved inwardly beyond the trailing edge 168 of the actu-ator 164, the trailing edge of that bill would be inter-cepted by the inner surface of the leading edge 166 o:E
that actuator. In that event, the actuator 164 would make it impossible for that person to recover that bill in intact ~orm.

The numeral 170 denotes a stud-like pivot which has the reduced-diameter outer end thereof fix-edly positioned within an opening in one of the flanges 142 of the cover 140. The numerals 172, 178 and 180 denote similar stud-like pivots which have the reduced-diameter outer ends thereof fixedly positioned within openings in the flanges 142. As shown by Fig. 6, the pivots 170 and 178 are .in alignment with each other and are close to the front of the paper currency valiaator 30. The pivots 172 and 180 are in axial alignment with each other and are spaced a short distance rearwardly of the aligned pivots 170 and 178. The numeral 174 denotes a bushing which is mounked in one of the :Elanges 142 Oe the cover 140; and the numeral 176 denote~ a Eurther bushing which is mounted in the other flange 142, and that bushing is in axial alignment with the bushing 174.
A shaft 182 is rotatably supported by the bushings 174 and 176; and pulleys 192 and 194, which have serrated peripheries, are fixedly secured to that shaft. A pulley 184 is rotatably mounted on the pivot 170; and pulleys 186, 188 and 190 are rotatably mounted, respectively, on the pivots 172, 178 and 180. The pulleys 184, 186 and 192 : are aligned with each other and are in register with the slot 130; and those pulleys accommodate an elongated end-less belt 196 which has an outer surface that provides a high co~fficient friction. The pulleys 188, 190 and 194 are aligned with each other and are in register with the slot 128; and those pulleys accommodate an elongated end-less belt 198 which has an outer surface that provides~a high coe~ficient o riction. The lower "run" oE the belt 196 is engaged by the upper portions of the rollers 92, 93 and 96; and the lower "run" o the belt 198 is

2~.

~L~3~

engaged by the upper portions of the rollers 82, 86 and 90.
A worm sheet 200 is fixedly secured to the shaft 182; and a worm gear 202 meshes with -that worm wheel. That worm gear is mounted on the output shaft 203 of a D.C. motor 562 which is enclosed by a motor housing 204. As shown particularly by Figs. 1 and 3, that motor housing extends upwardly from the cover 140;
and it has its axis perpendicular to the central portion of that cover. The motor 562 is a reversible permanent magnet motor which drives an A.C. generator 560 by means of a connection 564. ~hat ~.C. generator is located with-in the motor housing 204; and the connection 564 i~ a direct mechanical connection. In the said preferred em-bodiment, the motor 562, the A.C. generator 560 and the connection 564 are parts of a type CYQM Motor With Inte-gral Tachometer Generator which is marketed by the Barber Colman Company as Model No. CYQM 23360-3. When the motor 562 is energized in the "forward" direction, it will di-~` 20 rectly drive the A.C. generator 560, and it will drive the lower "runs" of the belts 196 and 198 inwardly of the paper currency validator 30. When that motor is energized in the "reverse" direction, it will directly drive the A.C. generator 560, and it will drive the lower "runs"
o the belts 196 and 198 outwardly of that paper currency validator.

25.

~3~

The numeral 206 aenotes a mounting bracket which is shown particularly by Fig. 7; and that mount-ing bracket fixedly holds the magnetic heads 208 and 210 in spaced-apart relation. Slots 212 and 214 are provided in that mounting bracket; and the shank of a set screw 216 extends through the slot 212 to seat with-in an opening in the platen 118, while the shank of a set screw 218 extends through the slot 21~ to seat within a further threaded opening in that platen. By loosening and then re-tightening the set screws 216 and 218, it is possible to adjust the longitudinal position oE the mounting brackat 206 relative to the platen 118. This is desirable; because it m~ke~ it possible to po~ition the air gaps o the magnetic heads 208 and 210 so they are precisely tangential with the upper surfaces of the rollers 102 and 114, respectively, as indicated by Fig. 5O
It will be noted that the pulleys 186 and 190 are disposed just a short distance outwaraly of the mag-netic head 208, as indicated by Fig. 5. This is impor-tant; because the leading edge of a well-worn, limp bill, ~; that was being moved inwardly by the belts 196 and 198, might be unable to orce the roller 102 far enough down-wardly to pass between that roller and the air gap of that magnetic head. In that event, the belts 196 and 198 would continue to apply inwardly-directed forces to ; that bill, and would tend to wrinkle and crumple that bill up against the outer face of the magnetic head 208.

26.

If the pulleys 186 and 190 were spaced a considerable distance outwardly o the magnètic head 208, the belts 196 and 198 might be able to move the trailing edge of such a bill well inwardly of the pulleys 186 and 190;
and, thereafter when the motor 562 was r~versed, the portion of the lower "run" of the belt 196 which is between the pulleys 186 and 192 and the portion of the lower "run" of the belt 198 which is between the pulleys 190 and 194 might be unable to apply sufficient pressure to the trailing edge of that bill to cause that bill to move outwardly. However, by disposing the pulleys 186 and 190 just a short distance outwardl~ o the magn~tic head 208, the present invention enables thos@ pulloys to hold the adjacent portions of the lower "runs" of the belts 196 and 198 in such intimate engagement with the rollers 93 and 36, respectively, that those portions of those belts will fully grip the trailing edge of any wrinkled or crumpled up bill. As a result, the present invention makes certain that the lower "runs" of the . 20 belts 1~6 and 198 can apply forces to the trailing edge of a wrinkled and crumpled up bill which will enable the reversal of the motor 562 to move that bill outwardly of the paper currency validator 30.
The numeral 220 denotes an elongated pivot which has the opposite ends thereof secured to the rear portions of the flanges 120 on the upper platen 118; and that pivot extends through aligned openings in the 1anges 42 on the lower platen 40, as indicated by Fig. 3. Consequently, ~38~
the pivot 220 enables the upper platen 118 -- and the cover 140 plus the various components which are mounted on that upper platen and on that cover -- to:be rotated upwardly and away from the lower platen 40. Such rota-tion is desirable, because it permits free and ready access to the space between the lower platen 40 and the upper platen 118. However, the upper platen 118 will normally respond to its weight, to the weight of the cover 140, and to the weight of the components mounted on that upper platen and on that cover to urge the lower face of the lower "run" of the belt 198 into intimate engagement with the upper faces o~ the roller~ 82, 86 ~and 90, an~ also to urge the lower face Oe the lower "run" of the belt 196 into intimate engagement with the upper faces of the rollers 92, 93 and 96. The springs 70, 72, 74, 76, 78 and the spring, not shown, which is in register with the spring 70 will yield slightly in .; response to the combined weights of the upper platen 118, of the cover 140, and of the components which are . 20 carried by that upper platen and by that cover; but those springs will hold the upper surfaces of the rollers 86, 82, 90, 92, 9~ and 93, respectively, above the upper surface of the lower platen 40, as shown by Fig. 4.
Referring particularly to Fig. 11, the numeral 230 denotss a conductor which is connected to the posi-tive terminal of an unregulated source of thirty volts D.C. by a conductor 232; and the numeral 234 denotes a further conductor which is connected to that positive terminal by a conductor 236. The numeral 238 denotes a conductor which serves as a ground for the sub-circuit in Fig. 11; and the numeral 240 denotes a filter capa-citor which is connected between the conductor 230 and the grounded conductor 238.
Each o the magnetic heads 208 and 210 has one terminal thereof connected to the grounded conductor 238.
The other terminal of the magnetic head 208 is connected to the conductor 230 by a constant current diode 242 of a standard and usual design; and the other terminal o the magnetic head 210 is connected to the aonductor 23~
by a similar constant current diode 244. rrhose constant current diodes permit a predetermined amount of direct current to flow through the coils of those magnetic heads, and thereby enable those magnetic heads to oper-ate as biased magnetic heads.
The numeral 246 denotes an Amplifier which in-cludes an NPN transistor 248, and NPN transistor 250, resistors 252, 254, 256 and 258, capacitors 260 r 262, 264 and 266, and a diode 268. The capacitor 260 couples the output of the magnetic head 208 to the base of trans-istor 248; and the output of that transistor is dlrect-ly coupled to the base of the trans~stor 250. ~he num-eral 270 denotes an Amplifier which is shown as being identical to the Ampliier 246; and the counterpart of capac.itor 260 couples the output of magnetic head 210 to the base of the counterpart of transistor 248.

~ ~ J

While . the Amplifiers 246 and 2 70 are very useful and desirable, any suitable high ~uality amplifiers of comparable nature could be sub-stituted for them.
The numeral 2 72 denotes a Squar inq Circuit which includes an ~PN transistor 274 and an inverter 2 76. The capac itor 266 couples the output of Amplifier 246 to the base of trans istor 2 74; and the inverter 276 inverts the output of transistor 274 and couples it to a Fre~uenay Sens:inq Circuit 280. 'rhe numeral 278 denotes a Squaring Ci.rcult whiah i9 iden~ica:l to the S~uaring Circuit 272; and the inverter in the Squaring Circuit 278 couples the output of the transistor o that Squaring Circuit to a P'requency-gensing Circuit 2 92.
The Frequency-Sensing Circuit 2 80 includes a fixed inductor 282, fixed capacitors 284 and 286, a resistor 288, and a diode 290. The capacitors 284 and 286 coact with the inductor 282 to constitute a tuned circuit that has a center frequency of approximately eleven hundred and fifty Hertz. The res istor 288 couples the output of the Squar ing Circuit 2 72 to khat 30.

:~3~Q~

tuned circuit; and the diode 290 couples the output of that tuned circuit to a Threahhold Detector 294.
The Fre~uency-Sensing circuit 292 i5 shown as being identical to the Fre~[uency-Sensing circuit 280; and it has a ixed inductor, two ~ixed capacitors, a resistor, and a diode.
That resistor couples the output of the S~[uaring Circuit 2 78 to khe tuned circuit o~ the Frequency-Sen~ing Cirauit 292; and that dlode couples the output o~ that tuned aircuit to a ~hreshhold I:)etector 308.
The rrhreshhold Detector 294 includes NPN transistor~ 2 96 and 298, a diode 300, a capacitor 302, and resistors 304 and 306. The Threshhold Detector 308 includes NP~ transistors 297 and 299, a diode 301, a ca~pacitor 303, and resistors 305 and 307.
The numeral 310 denotes a Validation Latch Circuit which includes ~A~D gates 312 and 314, an inverter 316, and a conductor 318 which exltends rom the ou~put o:E the inverter 316 to a conductor 319 which interconnects the lower input ~3~

of NAND gate 312 and the upper input of NA~Dgate 314. The numeral 320 denotes a diode which has the anode thereof connected to the ~unction of resi~tors 304 and 306, and which ha~ the cathode thereof connected to the cathode of a diode 322 and al~o to a conductor 328. That conductor extends through Figs. 12 and 13 and into Fig. 14. The diode 322 has ~he anode thereo connected to the junction o resistors 305 and 307. The numeral 326 denotes a conduator which extends rom the output of inverter 316 throwgh Fig. 12 into Fig. 13. The numeral 324 denotes a conductor which is connected to the outputs of NA~D gates 312 and 314; and that conductor extends through Fig. 12 into Fig. 13.
A conductor 325 extends from the conductor 324 in Fig. 11 into Fig.12.
Referring particularly to Fig. 12, the numeral 329 denotes a Start Switch Circuit which includes the switch 146, a resistor 330, an ~P~ transistor 332 and a resistor 338. The resistor 330 connects the collector of transistor 332 to the positive terminal of a regulated source o fifteen volts D.C. The numeral 339 denotes ~3~

a S~quence Switch Circuit which includes the switch 156~ a resistor 340, an NP~ transistor 342, and a resistor 346. The resistor 340, connects the collector of transistor 342 to the positive terminal o the regulated source of fifteen volts D.C. The numeral 349 denotes an Exit Swikch Circuit which includes the switch 162, a resistor 348, an ~P~ transistor 350, and a resistor 354. The resistor 348 connects the collector of transistor 350 to the pO9 itive terminal o~ the regulated source of ~i~teen volts D.C.
The collector of transistor 332 is connected ~o the upper input of a ~A~D ga~e 334, and also to a conductor 336 which extends into Fig. 13. The collector of transistor 342 i9 connected to the middle input of NA~D gate 334, and also to a conductor 344 which extends in~o ~ig. 13. The collector of transistor 350 is connected to the lower input of NA~D gate 334, and also to a conductor 352 which extends into Fig. 13.

~23~

The numeral 356 denotes a Vend Circuit which includes a 2~A~D gate 358, an inver~er 360, a resistor 362, an ~PN transistor 364 ~hich i5 connected as an eight and two-tenths volt Zener diode, an ~P~ transistor 366, a relay coil 368 and a diode 370 whiah are connected in parallel with each other, and normally-open relay contacts 372. The lower terminal o:E coil 368 and the anode of diode 370 are connected to the collector o:E transistor 366; and the upper terminal o:E that coil and the cathode o~ that d:lod~ are connected to the positive terminal of the ~ource o~ unregulated thirty volts D.C. The relay coil 368 controls the normally-open relay contacts 372;
and conductors 374 and 376 extend ~rom those relay contacts to the terminals oi~ a vending machine, not shown. That vending machine could be a change maker, a product vendor or a vendor of services with which the paper currency validator 30 i9 U9ed .
The numeral 378 denotes a conductor which extend~ :Erom the output o~E khe inverter 360 to the input o~ an inverter 380. The output of the latter inverter i9 connected to the bases

3~.

of the transistors 332, 342 and 350 by the resistors 338, 346 and 354, re~pectively.
The numeral 382 denotes a Vend Time Circuit which includes a diode 384, a resistor 386, a capacitor 388, an NPN transistor 392 which is connected as an eight and two-tenths volt Zener diode, resistors 394 and 396, and an ~PN
transistor 398. The cathode of diode 384 is direatly connected to the conductor 352. The lower te~minals o~ resistor 386 and o~ aapacitor 388 are connected i~mediate the anode o~ diode 384 and the emitter o~ transistor 392; and the upper terminals of that resistor and o~
that capacitor are connected to the positive terminal of the souxce of regulated fi~teen volts D.C. by a conductor 390. The emitter of transistor 398 is connected to ground, the collector of that transistor i9 connected to conductor 325, and the base of that tran~i~tor is connected to the junction of resistors 394 and 396.

35.

The numeral 400 deno~as a Gross Time Delay Circuit which includes 2~P~ transistors 402, 404 and 406, capacitors 408 and 410, a diode 412, and resistors 416, 418 and 420. A
eonduetor 4,14 eonneets the eollector of trans-istor 402 and the upper terminal of resistor 420 to the pos itive terminal of the source of regulated fifteen volts D.C. Resistors 416 and 418 conneet the emitter of tran~istor 402 to ground; and the junetion of tho~e resis tor~
i9 eonnected to the ~ba~e O:e ~rans iskor 404.
The lc~wer ~erminal o~ re~istor 420 is eonneeted to the colleetor of trans istor 404 and to the base of transistor 406. A conduetor 422 extends from the collector of transistor 406 through F ig. 13 into F igO 14.
The numeral 424 denotes a conductor which extends from tha output of NAND gate 334 to the upper terminal of capac itor 408 in the Gross Time Delay Circuit 400 and then into Fig.
13. An inverter 426 connects the ou~put of NAWD gate 334 to the lower input of WA~D ga~e 358 in the Vend Cireuit 356. The upper input of ~AWD gate 358 is connected to the conduetor 325,, 36.

Re~erring particularly to Fig~ 13, the numeral 428 denotes a Positional Time Delay Circuit which includes an inverter 430, diodes 432 and 434, a resistor 436, al.~capacitor 440, and an NPN transistor 442 which is connected as a eight and two-tenths volt Zener diode. A conductor 438 connects the upper terminal o the resi~tor 436 -- and hence the anode3 o diodes 432 and 434, the upper terminal o capacitor 440, and the emitter o~ transi~tor 442 -- to the positive term:lnal o the source of regulated 1~teen volts D.C.
The cathode o~ diode 432 i~ connected to conductor 352, and the input of inverter 4320 is connected to conductor 344.
The numeral 444 denotes a Further Time Delay Circuit which includes an inverter 446, diodes 448 and 450, a capacitor 452, a resistor 454, and an NP~ transistor 458 which i9 connected as a eight and two-tenths volt Zener diode. A conductor 456 connects the upper terminal o the resistor 454 -- and hence the anode~ of diodes 448 and 450, the upper terminal 37.

o capaaitor 452, and the emitter of transistor 458 -- to the positive termina~ of the source of regulated ~fteen volts D.C~ The cathode of diode 448 is connected to conductor 326, and the input o~ inverter 446 is connected to conductor 352, The numeral 460 denotes a Time Delay Output Circuit which includes an ~PN transistor 462 and a resistor 464. The collectors o~ the NPN transistors 442 and 458 are connected ~o the upper terminal o~ resistor 46~ and to the base of transistor 462. rrhe lowor termLnal of that resistor and ~he emitter of that transistor are grounded. The numeral 463 denotes a conductor that is connected to the aollector of transistor 462; and that conductor i5 referred to as the motor reverse line.
The numeral 466 denotes a Motor Reverse Circuit which includes the coil 468 of a motor reverse relay that has a set of contacts 470 and a set of contacts 472 in Fig. 14. A diode 474 is connected in parallel with the relay aoil 38.

468: and the upper terminal of that relay ccil and the cathode of that diode are connected to the positive terminal of the source of unregulated thirty volts D.C. The lower terminal of that relay coil and the anode of that diode are aonnected to the aollector of an ~P~
transistor 476 which has the emitter thereof connec~ed to ground by a resistor 478. A
resistor 480 and a Zener diode 482 are con-nected as a voltage divider; and the junction between that resistor and that Zener diode i9 aonneated to the base of transistor 4 76,. rrhe anode of the Zener diode 482 i9 grounded.
The numeral 486 denotes a ~ailgate Circuit which includes an inverter 488 and three diodes 490, 492 and 494. Those diodes have the anodes thereof connected together and to the input of the inverter 488. An inverter 484 connects the conductor 336 to the cathode of diode 490, and also to the upper input of a NA~D gate 506 in a Bill Retrieval Circuit 504.
The cathode of diode 492 is connected to conductor 344, and the ca~hode o~ diode 494 is connected to the output of inverter 446 in the Further Time Delay Circuit 444.

39.

The numeral 496 denotes a Short PaperCircuit which includes a ~A~D gate 498 and diodes 500 and 5020 Tho~e diodes have the anode~
thereof connected together and to the lower input of that ~AND gate. The upper input of NA~D gate 498 i9 connected to the conductor 336;
and the output of that ~AND gate is connected to t~e conductor 463. The cathode of diode 500 is connected to khe output o~ inverter 430, and the cathode of diode 502 is connected to the conductor 352~
The midd~e input o~ the ~D gate 506 in the Bill Retrieval Circuit 504 is connected to the conductor 352; and the lower input of that NAND gate i9 connected to the conductor 324. The output of that NA~D gate is connected to the aonductor 463.
The numeral 508 denotes a Switch-Checking circuit which includes a NAND gate 510;
and the upper input of that ~AND gate is connected to the conductor 336, while the lower input of tha~ ~A~D gate i9 connected to the conductor 326. The middle input o~ the NA~D
gate 510 i9 connected to the output of the inverter ~46 in the Further Time Delay Circuit ~0 .

~3~n~

444, and the output of that NA~D gate i9 connected to the conducto~ 463.
The numeral 512 aenotes a Line cording Circuit which includes a resistor 514 and a capacitor 516. The lower terminals of that resistor and of that capacitor are grounded, and the upper terminals of that resistor and of that capac itor are connected to the conductor 463.
The numeral 518 denotes a ~eversc Relay Latah Circuit which inc:Ludes lnve~ter~ 5Z0 and 522 and diodes 524 and 526. ~he input of inverter 52 0 and the anode of di.ode 524 are connected to the cbnductor 463; and the output o that inverter and the cathode of diode 526 are connected kogether and to the upper terminal of resistor 480 in the Motor Reverse C ircuit 466.
A diode 528 connects the conductor 324 to the cathode of diode 524 and to the output of 2 0 inverter 522; and a diode 532 has the cathode thereof connected to the conductor 424, and h~l9 the anode thereof conneated to the input o:E
inverter 522 and to the anode of diode 526.

~1 .

The numeral 530 denotes a diode which has the cathode thereof connected to the output of inverter 488 in the Tail Gate Circuit 486.
The anode of that diode is connected to the aonductor 463.
Referring particularly to Fig. 14, the numeral 533 denotes an Amplitude-Responsive Control Circuit which includes an integrated circuit 534, ~PN tran~istors 538 and 554, re~i~tors 542, 54~, 552, 556 and 558, a potentiometer 544~ a capacito~ 548, and a diode 550. While various integrated circuits could be used as the integrated circuit 534, the said pre~erred embodiment of paper currency validator uses a Motorola MC 1723-CL Voltage Regulator as that integrated circuit.
A conductor 536 connects pins 11 and 12 of the integrated circuit 534 to the positive terminal of the source of regulated fifteen volts D.C., and pins 3 and 7 of that integrated circuit a~e grounded. Pins 5 and 6 of the ~; integrated aircuit 534 are connected together;
and pin 4 of that integrated circuit is connected 42.

to the movabl~ contact of the potentiometer 544.
The conductor 422 is connec~ed to pin 13 of the integrated circuit 534, and pin 9 of that integrated circuit i9 connected to the base of transi~tor 554 hy the resistor 552. Pin 2 o the integrated circuit 534 i9 connected to the junction of resistors 556 and 558. A
conductor 540 connects the collector of transistor 538 to the positive terminal of the source o~ regulated fi~teen volts D.C. The lower ~erminals of resistor 558 and of capaaitor 548 are grounded. The re~istor 542, th~
potentiometer 544 and the resistor 546 are connected in series between the emitter of transistor 538 and ground.
The motor housing 204 is denoted in Fig. 14 by a dashed-line block: and that motor housing encloses the A.C. generator 560, the D.C. motor 562, and the driving connection 564.
In the said preerred embodiment, a D.C. motor is selected which will produce a minimum of electrical "noise" resulting from the interaction ~3.

' ;.

; between the brushes and the commutator thereof, becau~e any such electrical noise would adversely af~ect the operation o~ the Frequency-Sensing Circuit~ 280 and 292, and could adversely a~ect the operation o~ other circuits o~ that preferred embodiment. However, the electrical noise from even the least noisy commercially-available, reversible~ adjustable-speed D,C. motor is great enough to adversely a~ect the operation o~ the Freguency~Sen~ing Circuits 280 and 292;

and hence a aapaaitor 566 i~ aonnected between the upper terminal o~ th~ motor 562 and the motor housing 204, and a capacitor 568 is connected between the upper and lower terminal~ o~ that motor. Those capacitors will e~fectively attenuate the electrical noise developed by the motor 562, and will thereby keep that electrical noise from affecting the operation of any other componen~ or sub~circuit o~ the paper currency validator 30.

The upper terminal of the motor 562 i9 connected to the left-hand ~tationary relay contact 470, and al~o to the ~tationary right hand relay contact 472. The lowcr terminal of that motor is connected to the le~t-hand stationary relay contact 472, and also to the stationary r ight-hand relay contact 470. The movable relay contact 470 i9 connected to the positive terminal of the source of unregulated thirty volts D.C. by a conduator 569. Ths movable relay con-tact 472 is connectea to the collector of the transi~tor 554; and a diode 570 has the anode thereo~ connected to the movable relay contact 472, and ha~ the cathode thereo:E connea~ed to the movable relay contaat 470. r~hat d io~le wil:l provide a discharge path :~or the lnduative energy within the motor 562 wheneve.r the current 10wing through that motor i9 in terrupted O
The numeral 572 denotes a current-Sensing circuit which includes a differential amplifier 574, a potentiometer 580, resistors 578 and 582, and an inverter 586. One terminal of that differen-tial ampliier is connected to ground, and another terminal of that differential amplifier i9 con-nected to the po9 itive terminal oE the source of regulated ifteen vol:ts D.C. by a conductor 576. The resistor 578~ the potentiomQter 580, and the res istor 582 are connected between ground and a conductor 584 which e~tends to the positive terminal o~ the source of regulated iteen volts D.C.

45.

The movable contact of the pc~tentiometer 580 is connected to the lower input terminal of the differential amplifier 574: and the emitter of the transistor 554 is connected to the upper input terminal of that differential amplifier. The input of the inverter 586 i9 connected to the outputof the differential amplifier 5 74; and the output of that inverter is connected to the conductor 32 8"
Re:Eerring particularly to :F~g. 15, the numeral 588 denotes a ~re~uenc~ Respon~ ~e Control Circuit which can be substituted for the Amplikude-Responsive Control Circuit 533 o Fig. 14. That Frequency-Resporlsi~re Control Circuit i9 not, per se, a part of the present invention; and it is disclosed herein 901ely to illustrate the adaptability of the circuitry of Figs. 11-13 to variou~ speed-regulating control systems. That Frequency-Responsive Control Circuit includes ~PN transistors 590, 624, 630 and 670, resistors 592, 594, 602, 614, 622, 626, 632, 634, 636, 638, 644, 64~, 662, 666, 668, 672 and 674, diodes 598 and 656, a ~table, non-retrigger ing one-shot 606, a potsntiomete.r 646, capacitors 600, 608, 610, 616, 640, 642, 46.

658 and 660, an inverter 620, and an operational ampli~ier 650. A conductor 596 connects the upp~r terminal of resi~tor 594 to the positive terminal of the source of regulated fifteen volts D.C., and ~he left-hand terminal of resistor 592 i9 connected to the un-grounded output terminal of the A.C. generator 560. The diode 598 has the anode thereof grounded, and has the aathode thereo connected between resistor 592 and the base :10 oE transist~r 590. rrhe emitter of trans~stor 590 i~ grounded, and the collector of ~hat transistor is conneated to the lower terminal of resistor 594.
The resistor 602 has the lower terminal thereof conneated between the capacitor 600 and pin 2 o the one-shot 606; and the upper terminal ~f that resistor is connected to the positive terminal of the source of regulated fif~een volts D.C. by a conductor 604. That capacitor and that resistor constitute a differentiator; and the output of that differentia-tor is applied to pin 2 of the one-shot 606 That one-shot will change the state of the output at pin 3 thereof only when a negative-going signal i9 applied to the pin 2 47.

~31~
The capac itor 6 08 connects pin 4 of the one-shot 606 to ground, and the capacitor 610 connects pin 5 of that ona-shot to ground.
A conductor 612 connects pin 8 of the one-shot 606 to the pO9 itive terminal of the source of regulated fi~teen volt 9 D.C.; and the resistor 614 has the upper terminal thereof connected to that positive terminal by a condud~r 618. The capacitor 616 connects the lower terminal o:E
resistor 614 to ground: and the ~unatiorl between that resistor and that aapacitor 19 connected to pins 6 and 7 of the one-shot 606.
The inverter 620 has the input thereof connected to the conductor 422, and has the output thereof connected to the base of transis~or 624 by the res istor 622.. The res i9t:0r 626 has the upper terminal thereo~ connected to the positive terminal of the source of ragulated fifteen volts D.C. by a conduc~tor 628; and the lower terminal of that resistor is connected to the collector of transistor 624, to the collector of tra~sistor 630, to the uppe.r terminal of res istor 634, and to the left-hand terminal of resistor 636. The emitter o~ transistor 630 D~8.

is grounded, and the ba3e of thattransistor i9 connected to the pin 3 o the one-~hot 606 by the resistor 632. ~he right-hand terminal o resistor 636 is connected to the upper terminal of resistor 638, to the upper terminal of capacitor 642~ and to the upper input of operational amplifier 650. The lower terminal o resistor 638 i~ aonnecked to ground by the capacitor 640~
3.0 ~csistor 644 has the upper termi~al thereo connected to the positive terminal o~
the source of regulated fifteen volts D.C.; and the lower terminal of that resistor is connected to the upper terminal o potentiometer 646 which has the lower terminal thereo connected to ground by resistor 6480 Resistor 664 connects the movable contact o potentiometer 646 to the lower input of operational amplifier 650; and one termi~al of that operational amplifier 650:
and one terminal of that operational amplifier is connected to the positive terminal o the source o regulated fifteen volts DdC. by 49.

a conductor 652, wh ile another terminal of that operational amplifier i9 connected to the negative term.~l of that source of regulated fifteen volts D.C. by a conductor 654. The upper terminals: of registor 638 and of càpacitor 642 are connected to the upper input of operational amplifier 650. The diode 656 has ~he anode thereof connected to the output of operational amplifier 650, and has the cathode thereof connected to the base of transistor 670 by the resistor 666. The capaaitor 658 and the series-connected capac itor 660 and r~istor 662 constitut~ :~eed back pa~h~ :Erom ~he cathode of diode 656 to the lower input of operational amplifier 650. The resistor 668 is connected between ground and the r ight-hand terminal of resistor 666 and the base of transistor 6 70;
and resistors 672 and 674 are connected in series between the emitter of that transistor 2 0 and ground. That emitter is connected to the upper input of the differential amplifier 574 of a current-Sensing Cixcuit 572 which is iden~ical to ~he similarly-numbered Current-Sensing Circuit of Fig. 14. The collector of 50.

~3~
transistor 670 is connected to movable relay con-tact 472 and to the anode of diode 570; and that movable relay contact, that diode, the other relay contacts 472, the ralay contacts 470, the motor 562, the motor housing 204, the A.C.
generator 560, the connection 564, the capacitors 566 and 568, and the conductor 569 of Fig. 15 are identical to the similarly-numbered elements in Fig. 14. E~ectively, the subcircuit of Fig.
15 is the same as the sub-circuit oE F ig. 14 except or the ~ubstitution of the Fre~uency-Responsive Control Circuit 588 ~or the Ampllt~de-Respon~ive Control circuit 533 o Fig. 14.
The value~ of capacitors 658 and 660 and the value of resi~tor 662 are selected to make the subcircuit of Fig. 15 operate as a second order system. Such a system is a slightly under-damped system; and hence it will permit a very small amount of overshooting to occur -- thereby enabling that subaircuit to provide a desirably rapid response.
In the said preferred embodiment, some of the NA~D gates are portions o~ integrated circuits, and some o the inverters are parts of integrated circuits. For example, the NA~D gates 312 and 314 of Fig. 11, the ~AND gate 358 in Fig.
12, and the ~AND gate 4~8 in Fig. 13 are parts of 6~
a quaa 2- input NAMD gate which is sold under the trademark Motorola MC 668. The ~A~D gate 334 in Fig. 12 and t~e ~A~D gates 506 and 510 in Fig.
13 are parts of a three 3-input NAND gate which is sold under the trademark Motorola MC 670. The inverter 276 and its counkerpart in Fig. 11, and the inverters 430, 446, 484 and 488 in Fig. 13 are parts of a hex inverter which is sold un~er the trademark Motorola MC 680; and the inverter 316 in Fig. 11, the inverters 360, 380 and 426 in Fig~
12, and the inverters 520 and 522 in Fig 13 are par~s of ano~her he~c inverter whiah i~ ~old under the trademark Motorola MC 680.
The diferential amplifier 574 in Figs.
14 and 15 can be an operational amplifier which is sold under the trademark Motorola MC 1741-CP l.
The one-shot 606 in Fig. 15 can be a timer which is sold under ~he trademark Signetics l~E 555V.
The operational amplifier 650 in Fig. 15 can be an operational amplifier which is sold under the trademark Motorola MC 1741-CP l. The other com-ponents of Figs. 11-15 can be ~tandard and usual commercial grade component~.

In the said preferred embodiment, the length of the lower platen 40 is shorter than the length of a U.S. dollar bill. Specifically, the distance from the rear edge of the upwardly-inclined inner end 38 o~ the platform 32 to the rear of the downwardly-inclined trailing edge 45 of the lower platen 40 is about five and seven-sixteenths inches, whereas ~e average length of a U.S. dollar bill i9 about six and one-eighth inches. rrhe upper platen 118 i9 slightly longer than the lower platen 40, as indicat~d b~
Figs. 4 and 5; and the dlstance ~rom a vertical projection of the front of ~e semi-cylindrical leading edge 124 to a vertical projeation o the rear of the trailing edge 126 i9 just slightly less than six inches. Consequently, the upper platen 118 also i9 shorter than a U.S. dollar bill. The distance between the downwardly-directed flanges 120 at the sides of the upper platen 118 is slightly greater than the width of a U.S.
dollar bill; and`hencesuch a bill can easily be moved inwardly o~ the space defined hy the lower platen 40, ~he upper platen 118, and the flanges 120 on that upper platen.

53.

~o~o~ ~

The outer end of the slot 52 in tha lower platen 40 is located about eleven-~ixteenths of an inch inwardly of the rear edge of the upwardly-inclined inner end o the platform 32 and the outer end of the 9 lot, not shown, in that platen, which is in register with the 5 lot 134 in the platen 118, is located about fifteen-sixteenths of an inch inwardly of that rear edge of ~hat upwardly-inclined inner end. Each of those slots i9 approximately one and one-eighth of an inch long and appro~imately one-eighth o an inch wide. The outer end of the s~ot 54 in the platen 40 is located about one and one-quarter inches outwardly of the rear of the downwardly-inclined trailing edge 45 of that platen; and that slot is approximately fifteen-sixteenths of an inch long and approximately five-sLxteenths of an inch wide.
The outer end of ea~h of the slots 46 and 56 in the platen 40 is located about one inch inwardly of the rear edge o~ the upwardly-inclined inner end 38 of the plat~o~m 32; and each of those slots is abou~ one-half o. an inch long and about nine thirty-seconds of an inch wide. The distance between the inner edge o 54.

3~g33~

9 lot 46 and the outer edge o the 9 lot 48 i9 about one-half of an inch; and, similarly, the distance between the confronting edges of the slots 56 and 58 i9 about one-half of an inch.
Each of the slots 48 and 58 is about one-half of an inch long and about nine thirty-seconds of an inch wide. The distance between the con:Eronting edges of the slots 48 and 50 is about two and one thirty-seconds of an inch; and, similarly, ~he dis~ance be~ween the con:eronting edges oE the ~lots 58 and 60 is abou~ two and one ~hlrt~ eaond~ of an inch. rrhe o~ter edge o the 910t, not shown, hich receives the roller 102 i9 located about two and one-half inches inwardly of tha rear edge of the upwardly-inclined inner end 38 of the plat-form 32; and the outer edge of the slot, not shown, which accolmnodates the roller 114 is located about seven-s ixteenths of an inch inwardly of the inner edge of the 910t which accommodates the roller 102.
The switch actuator 1~8 i9 located so the leading edge of a bill must be moved about one and five-sixteenths of an inch inwardly o:E a vertical projection of the front of the semi-cylindrical leadin~ edge 124 of platen 118 before it moves that switch actuator far enough to close switch 146. The leading edge of that bill must be moved about three-eighths of an inch further inwardly before it can engage the lower "runs" of belts 196 and 198. After the leading edge of that bill has been moved inwardly of the vertical projection of the front of the semi-ciroulæ leading edge 124 of platen 118 a total distance of about one and thirteen-sixteenths of an inch, that leading edge will cau3e the switch actuator 158 to close the switch 156.
~ot until the leading edge of the bill ha~ been moved a total distance of approximately four and fifteen-~ixteenths of an inch inwardly of the vertical projection of the front of the semi-cylindrical leading edge 124 of the upper platen 118 will that leading edge cause the switch actuator 164 to close the switch 162~ -The air gap of the magnetic head 208 is located about three and three-sixteenths of an inch inwardly of the front of the semi-cylindrical leading edge 124 of the upper platen 118; and the air gap of the ma~netic head 210 i9 located about one inch further inwardl~. The leading edge of the ovate portrait background on a U.S. dollar bill will not move into 56.

register with the air gap of the magnetic head 208 until the leading edge of that bill has caused the switch actuator 164 to close the switch 162, and then has been moved approximately three-quarters of an inch urther inwardly.
The leading edge of the inserted bill must be moved approximately four and three-sixteenths of an inch, after it has caused the actuator 158 to close the switah 156, before that leading edge can cause the actuator 164 to close the switah 162. Furkhermore, the bill must be moved appro~imately one and three~uarter~ o~
an inch further i~wardly of the paper currency validator 30, after the leading edge of that bill has caused the actuator 164 to close the sw~tch 162, before the vertical grid lines in the leading half of the portrait background can engage the air gap of the magnetic head 210 and the vertical grid lines in the trailing half of that portrait background can engage the air gap of the magnetic head 208.

57.

The motor 562 will drive the pulley~
192 and 194 ~y means of its output shaft 203, worm gear 202, worm wheel 200, and the shaft 182. That motor will drive the pulleys 192 and 194 at a speed which will make the linear speed of each of the belts between nine and one-tenth and nine and five-tenth~ of an inch per second.
Those belts will cause an inserted bill to move at that same speed: and hence that bill will mo~e inwardly at a rate between nine and one-ten~h and n~ne and ~i~e-tenths o~ an inch per seaond~
This means that it will take an lnserted bill approximately four hundred and fifty milliseconds to move from the position wherein it efects closure of the switch 156 to the position wherein it effeats closure o the switch 162. Thereafter, it will take that bill approximately one hundred and eighty-eight milliseaonds to move from the po~ition wherein it effects clo3ure of the switch 162 to the position wherein the air gaps of both magnetic heads 208 and 210 should sense vertical grid lines in the pcrtrait background.
Those vertical grid lines will move past those air gaps at a rate of approximately eleven hundred and fifty time~ a seaond.

58.

~3~

Whenever the paper curranky validator 30 is in its stanaby condition, the switches 146, 156 and 162 will be open, as shown by Fig. 12. As a result, all of the transistors 332, 342, 350 will be non-conductive; and es~entially fifteen volts will appear at the collectors of each d those transistors. That voltage will constitute a logic "1" whereas ground voltage will constitute a logic "0".
~his means that in the standby condition of the paper currenay validator 30, logic "1" will appear at all o~ the inputs o~ the ~A~D gate 334, at the input o~ inverter 484 in Fig. 13, at the upper input o~ ~A~D gate 498 in Fig. 13, and at the upper input o~ ~A~D gate 510 in Fig. 13.
Additionally, logic "1" will appear at the input of inverter 430 in Fig~ 13 and at the cathode of diode 492 in FigO 13. Further, logic "1" will appear at the cathode of diode 384 in Fig. 12, at the cathode o~ diode 432 in Fig. 13, at the input of inverter 446 in Fig. 13, at the cathode of diode 502 in Fig. 13, and at the middle inpu~
of ~AND gate 506 in Fig. 13. ~he output o~ ~A~D
gate 334 in Fig. 12 will be logic "0"; and hence the tran~iskor 402 ln the Gro~ Time Delay Circuit 59.

400 of Fig. 12 will be non-conducti~Te and the transisto~ 404 in that circuit also will be non-conductive. However, transistor 406 in that circuit will be conductive: and hence the conductor 422 will apply logic "0" to the pin 13 of the voltage regulator 534 in Fig. 14 -- thereby cau~ing pin 9 o that ~Toltage regulator to apply logic "0" to the base o transistor 554. This means that the motor 562 w ill be de-energized, and the belts 196 asld 198 will be stakionary. At this time, logic "0" will appear at pin 2 Oe the voltage regulator 534; and logic "0" will appear at the movable eontact of potentiometer 544 __ and hence at pin 4 o that voltage regulator.
The magnetic heads 208 and 210 will have D.C. biasing currents flowing through them: but those magnetic heads will not supply any signals, to the capacitor 260 in the Amplifier 246 or to the counterpart capac itor in the ~mplifier 270, whieh could be amplified by tho~e Ampliiers~ As a result, the transistors 296 and 297 in the Thr2shold Detec~ors 294 and 308 will be nonconductive; and henae the collector oE trans-istor 298 will apply logic "1" to theupper input 60.

~.~3~

o~ ~AND gate 312, while the collector of transistor 299 will apply logic "1l' to the lcwer input of NA~D gate 314. If, at the t~me the paper currency validator 30 was connected to the sources o~ regulated ~i~teen volts D.C. and o~ unregulated thirty volt~ D.C., the voltage at the lower input of NA~D gate 312 had been logic "0", logic "1" would have appeared at the output o~ that NAND
gate; and that logic "1" would have been applied by the conductor~ 324 and 325 to the colleator o~
~ransistor 398 in Flg~ 12. Becau~e the diode 384 would have had logic "1" at the cathode thereo, that diode would have been back-biased; and hence parallel-connected resi~tor 386 and capacitor 388, transistor 392, and resistors 394 and 396 would have applied a positive voltage to the base of transistor 398 which would have rendered that ~ransistor conductive. Thereupon; tha~
transistor would haue provided a logic "0" on the conductors 325 and 324~ and thus at the input of inverter 316; and that inverter would have applied logic "1" to the lower input o~ NAND gate 312 and to the upper input o ~A~D gate 314.
Those ~AND gates would then have provided lo~ic OII on aonduators 324 and 325 and at the input 61.

of inverter 316; and that inverter would thereafter have maintained logic "1" at the lawer input of NA~D gate 312, at the upper input of NAND gate 314, at the cathode of diode 448 in Fig. 13, and at the lower input of 2~AND gate 510 in Fig. 13. The logic "0" on the conduator 324 would have back-biased the diode 528 and would have appeared ak the lower input of NA~D yate 506; and the logic "0" on the conductor 325 would have r~ndered the transi~tor 398 non-conductive. ~I'he aonductor 325 is consid-ered to be the validat:i.on line of the paper currency validator 30; and the logic "0" on that conductor during the standby condition O:e that paper currency validator means that no validation signal i9 present during that standby condition.
~e logic "0" on the conductor 325 will be applied to the upper input of ~A~D gate 358;
and the r~sulting logic "1" at the output o:E that NAND gate will cause, the inverter 360 to apply logic "0" to the base of transistor 366 and to the input of inverter 380,. Transistor 366 will respond to the logic "0" at the base thereof to be non-aonductive; and hence the vend relay aoil 36B will be de-energized and will leave the relay contacts 6~.

372 open. This means that the Vend circuit 356 will not be supplying a vend s ignal dur ing the standby condition of the paper currency validator 30.
The logic "0" at the input of inverter 380 will cause that in~erter to apply logic "1" to the base of each of the transistors 332, 342 and 350 in Fig. 12. However, all of those transistors will be non~conductive, because the emitter~ thereof are disconneated from ground by the open ~witches 146, 156 and 162~
~he inverter 430 in ~ig. 13 will respond to the logic " 1" at the input thereof to apply logic "0" to the cathode of diode 434 and to the cathode of diode 500. The diode 434.will thus be forward-biased; and it will apply logic "O"
to the upper terminal of capacitor 440 and to the emitter of transistor 442, thereby keeping that transistor from applying a positive voltage to the base of transistor 462. The inverter 446 in Fig.
13 will respond to the logic "1" at the input thereof to apply logic "O" to the cathode o~
: diode 450, to the cathode of diode 494, and to the -~3 -middle input of ~A~D gate 510. The diode 450 will thus be forward-biased; and it will apply logic "0" to the upper texminal of capacitor 452 and to the emitter of transistor 458, thereby keeping that transistor from applying a positive voltage to the base of transistor 462. As a resulk~ the transistor 462 in the Time Delay Output circuit 460 will be non-conductlve; and it will tend to provide logic "1" on conduator 463. This means that logi.a "1" will appear on the motor reverse llne 463 during the standb~
condition of paper currency validator 30.
The logic "1" at the cathode of diode 432 will back-bias that diode; but the forward-biased diode 434 will keep logic "0" on the upper terminal of capacitor 440 and at the emitter of-transisto~ 442 Similarly, the logic "1" at the aathode of diode 448 will back-bias that diode; but the forward-biased diode 450 will keep logic "0" on the upper terminal of capacitox 452 and at the emitter of tran~istor 458. Conse~uently, as indicated herelnbefore, the transistor ~62 will be non-conductive and will provide logic "1" on the conductor 463.

6~.

~æ~
~ he inverter 484 in Fig. 13 will respond to the logic "1" at the input thereof to apply logic "0" to the cathode of diode 490 and also to the upper input of ~A~D gate 506.
The logic "1" at the cathode o diode 492 in Fig.
13 will back-bias that diode; but the logic "0"
at the cathodes of the diodes 490 and 494 will forward-bias those diodes -- thus causing those diodes to apply logic "0" to the input of inverter 488. The resulting logic "1" at the oukpuk of that inverter will back-blas the dlod~ 530 -- there-by permitting logic "1" to remain on the conduator 463.
The logic "1" on the cathode of diode 502 will back-bias that diode; but the logic "0" on the cathode of diode 500 will forward-bias that diode--thus causing that diode to apply logic "0" to the lower input of NA~D gate 498. Although logic "1" is applied to the upper input of that ~A~D
: 20 gate, that ~A~D gate will respond to the logic "0" at the lower input thereof to permit logic "1"
to remain on the conductor 463 65.

The logic llll' on the middle input of the ~A~D gate 506 will tend to develop a logic "0" at the output o~ that ~AND gate;
but logic "0" appears at both the upper and lowe~ inputs of that NA~ gate. As a result, that N~ND gate will permit logic "1" to remain on the conductor 463.
The logic "1~ on the upper and lower inputs o~ the ~AND gate 510 wlll tend to develop a l~gic "0" at the output of that NA~D gate; ~ut logic "0" appears at the middle input o~ that NAND gate. As a result, th~
NAND gate will permit logic "1" to remain on the conductor 463.
The logic "1" on the conductor 463 will cause the inverter 520 to apply logic "0"
to the cathode of diode 526 and also to the base of transistor 4767 That transistor will respond to that logic "0" to remain non-conductive; and hence the re,lay coil 468 will remain de-energized.
This means that the relay contacts 470 and 472 will be in the "~orward" position ~hown by ~Lg.
14. The logic "0" at the cathode of diode 532 in Fig. 13 will ~orward-bias that diod~ and that 66.

diode will apply logic "0" to the anode of diode 526 and to the input of inverter 522. The diode 526 will be back-biased: and the inverter 522 will apply logic "1" to the cathodes of diodes 524 and 528 to back-biase those diode~.
The capacitor 516 in the Line cording circuit 512 will have logic "1" applied to the upper terminal thereo; and hence that capaaitor will be charged. The standby voltage across that capaaitor will be about twelve ~olt~.
The mo~able contack o~ potentiometar 580 in Fig. 14 will apply a positive voltage to the lower input of the dierential amplifier 574. However, the emitter of transistor 554 will apply zero voltage to the upper input of that differential amplifier; and hence that differential amplifier will provide logic "0"
at the output thereof, The inverter 586 will re~pond to that logic "0" to apply logic "1"
to the cathodes of diodes 320 and 322 in Fig. 11.

67.

; The overall result is that whenever ~ the paper currency validator 30 i9 in its - standby condition~ logic "0" appears on the validation conductor 325, logic "l" appears on the motor reverse co~ductor 463, the relay contacts 470 an~ 472 are in the "~orward"
~ po~ition o Fig. 14, the motor 562 is de-; energized, and the vend relay contacts 372 are open. Each of the transistors 332, 342 and 350 has po~iti~e voltages at the colleator and base thereof~ but all o~ those tran3istors are non-aonductlve beaause the sw~tches 146, 156 and 162 are open. However, as soon as any of thos2 switche~ is alosed, the transistor which has the emitter thereooonected to that switch will become conductive.
The Gross Time Delay Circuit 400 in F ig . 12 acts as an inexpensive and simple ~witch and timer. Specifically, as long as the paper currency validator 30 i9 in its stand-by condition, the transistor 402 of that Gross Time Delay Cirauit will respond to the logic "0"
at the upper terminal of capacitor 408 to remain 68.

38~
non-conductive, and will thereby apply logic "0" to the base of transistor 404. The latter transistor will remain non-conductive, and will thereby apply logic "1" to the base o~ transistor 406 -- to cause that transistor to be conductive and to apply logic "O" to ~he conductor 422.
However, as soon as any of the 3witches 146, 156 and 162 is closed, the resulting logic "1" at the upper terminal o~ capacitor 408 will cause current to ~low through that capacitor and through parallel~connected capaci~or 410 and the base-emitter clrauit o~ transi~tor 402 --to render that transistor conducti~e. The con-sequent ~low o~ current through transistor 402, r~sistor 416, and parallel-connected resistor 418 and the base-emitter circuit o~ transis-tor 404 will render the latter transistor conductive --to effectively shunt the base-emitter circuit o~ transistor 4Q6, and thereby render that trans-istor non-conductive. At this time, the Gross Time Delay circuit 400 will change the logic "0" on the conduator 422 to logic "1".

69.

~3E~

The capacitors 408 and 410 will continue to charge; and, at the conclusion of a time interval which will vary between 9iX and twelve seconds with variations in the manufacturing tolerances o~ those capacitors and o~ transist~r 402, those capacitors will have become charged to such an ex~ent that the flow of current through capacikor 408 and the base emitter circuit of transistor 402 wi~l be too small to ke~p tha~
transistor conduative. ~hereupon, that transistor will become non-aonductlve to render trans~skor 404 non-conductive -- thereby enabling transistor 406 to again become conductive to change the logic "1" on conductor 422 back to logic "0". This means that if any or all of the switches 146, 156 and 162 closes for a given time interval of from six to twelve seconds, the Gross Time Delay Circuit 400 will initially change the logic "0" on conductor 422 to l~gic "1" and will then -- at the end of that time interval -- change the logic "1" on that conductor back ko logic llO".

70.

Dur ing normal operation of the paper currency validator 30, none of the switche~
146, 156 and 162 will remain closed for a given time interval of from 9iX to twe~ve seconds and, instead, will re-open in less than a second afker it was closed. Hence, during normal o~ ration of that paper currency validator, the ; capacitors 408 and 410 will not have time to become substantially-fully charged ko render kransl~tor ~02 non-aonductive~ ~9 a resulk, during normal operation o~ the paper currency validator 30, the logia "0" at the upper terminal o capacitor 408 will be restored before the transistor 402 can become non conductive; and hence, during such normal operation, the Gross Time Delay Circuit 400 will respond to the closing of any of the switches 146, 156 and 162 to change the logic "0" on conductpr 422 to logic "1", and then will hold that logic "1" on ~hat conductor as long as any of those switches remains clo~ed. However if, for any reason, any of kho3e switches remains clo~ed for a time interval between six and twelve seconds, the G~o~s Time Delay Circuit 400 will automatically change the logic "1" on conductor 422 back to logic "O".
It t~us should be apparent that the Gross Time Delay circuit 400 is both a switch and a timer. Although the duration o~ the time interval during which that Gross Time Delay Circuit can hold logic "1" on conductor 422 is not precise, a precise time interval is not re~uired: because the restoration o~ logic "O" on the aonductor 422 i9 merely needed ~o prevent aontinuous operation o the motor 562 in the e~ent one o~ the switahes 146~ 156 and 162 does not re-open.
The Vend Time Circuit 382 in Fig. 12 is a timing circuit which provides a time delay of about one hundred and fifty milliseconds.
During ~he standby condition of the paper currency validator 30, the diode 384 of that Vend Time Circuit is back-biased by the logic "1" on conductor 352; and conductor 390, resistor 386, transistor 392, and resistors 394 and 396 permit su~icient current to 10w through the resistor 396 to forward-bias the base-emittex circuit of transi~tor 398. H~wever, because the sub-circuit of Fig. 11 is maintaining ~gic "0"
on conductor 325, that transistor will be non-conductive.
As soon as the switch 162 is closed, the diode 384 in the Vend Time Circuit 382 will be forward-biased; and it will start discharging the capacitor 388 via transistor 350 and ~witch 162 to ground. A~ter about one hal of a mi~isecond, the voltage at the emitter of transi~tor 392 will ~all below the Zenor voltage o~ that transistor; and, thereupon, the voltage at the base of transistor 398 will fall to zero, and that transistor will no longer be forward-biased. The capacitor 388 will continue to dis~harge via transistor 350 and switch 162 until it i9 fully discharged.
The Vend Time Circuit 382 will continue to leave zero voltage on the base of transistor 398 as long as the switch 162 remains closed;
but, when that 9W itch re-opens, the capacitor 73.

æ~

388 will begin to charge. That capacitor and resistor 386 cons~itute an RC circuit which will permit the voltage at the emitter o~
transistor 392 to remain below the Zener voltage o~ that transistor ~or a time interval of about one hundred and ifty milliseconds. At the end of that time interval, the base-emitter circuit of transistor 398 will again be forward-biased: and, if the sub-circuit of Fig. 11 has previously changed the logia "0" on conduator 325 to logic "1", that transi~tor will become conductive and will apply logic "0" to the conductor 325. This means that the Vend Time Circuit 382 will forward-bias the base-emitter circuit o~ ~ransistor 398 until the switch 162 is closedO will remove the forward-bias on that base-emitter circuit as long as that switch remains closed, and subsequently will again forward-bias that base-emitter circuit about one hundred and fi~ty milliseconds after that switch re-opens.

7~.

~3~
The Positional T ime De lay C ircuit 42~ in Fig. 13 is a timing circuit which provides a time delay of about five hundred and fifty milliseconds. During the standby condition o~ the paper currency validator 30, the diode 432 is back-biased by the logic "1" at the cathode thereof, but the diode 434 is forward -biased by the logic "0" which the inverter 430 applies to the cathode thereo~. Because the latter diode is ~orwa~d-biased, it connects the upper terminal o~ capaci~or 440 to ground via the output o~
in~erter 430 -- thereb~ keeping that capacitor discharged to maintain the voltage at the emitter o~ transistor 442 below the Zener voltage of that transistor. The resulting logic "0" at the collector of that transistor will keep the transistor 462 non-conducti~e, and will thereby enable logic "l"
to remain on conductor 463.
However, when the switch 156 is closed, tha resulting logic "0" at the input of inverter 430 will cause that inverter to back-bias the diode 434; and, thereupon, current will ~low ~rom aonductor 438 via resistor 436 and capacitor 440 to start charging that capacikor~ That resistor and that capacitor constitute an RC circuit which will keep the voltage at the upper terminal of that capacitor, and thus at the emltter o~ transistor 442, from reaching the Zener voltage of that transistor ~or a time interval of about five hundred and fif~y milliseconds a~ter the switch 156 is dlosed.
I~ the switch 162 is closed be~ore the end o~ that time interval -~ as will be the case dur ing normal operatlon o~ the paper aurrency valida~or 30-- the resulting logia "O" at the aathoda of diode 432 will forward-bias that diode, and will thereby discharge capacitor 440 via that diode, conductor 352, transistor 350, and switch 162 to ground. Consequently, even though switch 156 and inverter 430 continue to : back-bias the diode 434, the capacitor 440 will become discharged; and hence the voltage at the emitter of transistor 442 will not be able to reach the Zener voltage o~ that transistor.

If, however, the switch 162 i9 not closed before the end of the five hundred and fifty milli-seconds time interval, the voltage at the emitter of tran~istor 442 will reach the Zener voltage of that transistor, and will thereby render the transistor 462 conductive. All of this means that if the switch 162 is closed within five hundred and fifty milliseco~ds after the switch 156 i~ closed, logic "1" can aontinue to appear on the conduc~or 463. }I~wever, i~ the switch 162 is not alosed ~ithin ive hundr~d and fLfty milliseconds after the switch 156 is closed, logia "0" will automatically appear on that conduator.
The Further Time Delay circuit 444 in Fig. 13 is a timing circuit which provides a time interval between two hundred and fifty and three hundred milliseconds. During the ~tandby condition of the paper currency validator 30, the diode 448 of that Further Time Delay Circuit is back-biased by the ~ic "1" on conductor 326, but the diode 450 is forward-biased by the logic "0"
which the inverter 446 applies to the cathode thereof. Because the latter diode is ~orward-biased, Lt connects the upper terminal o capacitor 452 to ground via the output of inverter 44~ --77.

:~3~

thereby keeping ~hat capacitor discharged to main~in the voltage at the emitter of transi~tor 458 below the Zener volkage o~ that transistor.
The re~ulting logic "0" at the collector o~
that tran~istor will keep the tran~istor 462 non-conductive, and will thereby enable logic "1" to remain on conductor 463.
However, when the switch 162 i9 C109ed, the r~sulting logic "0" at the input of inverter 446 will cause that inverter to back~bia~ the diode 450; and, thereupon, current will ~low ~rom conductor 456 vla resistor 454 and capacitor 452 to start charing that capacitor. That resi~tor and that capacitor constitute an RC
circuit which will keep the voltage at the upper terminal of that capacitor~ and thu~ at the emitter of transistor 458, from reaching t~e zener voltage o that transistox *or a time interval between two hundred and fifty and three hundred milliseconds a~ter the switch 162 is closed.

78.

If the inverter 316 in the sub-circuit of Fig. 11 changes the logic "1" on conductor 326 to logic "0" before the end of that time interval -- as will be the case during normal operation o~ the paper currency ~alidator 30 --the resulting logic "0" at the cathode of diode 448 will forward-bias that diode, and will thereby discharge capacitor 452 via that diode, conductor 326 and that ~nverter to ground. Conse~uently, even though switch 162 and inver~er 446 continue to back-bias the diode 450, the aapacitor 452 will become di~charged; and henae the ~oltage at the emitter of transistor 458 will not be able to reach the Zener voltage of that transistor. If, however, the inverter 316 in the sub-circuit of Fig. 11 does not change the logic "1" on conductor 326 to logic "0" beore the end of the ~wo hundred and fifty to three hundred millisecond time in-terval, the voltage at the emitter of transistor 458 will reach the Zener voltage of that transistor, and will thereby render the ~ransistor 462 conductive~ All of this means that if the in~erter 316 in the sub-circuit of Fig. 11 changes the logic "1" on conductor 326 to logic "0" before the end of the two hundred and ~ifty to three 79.

hundred millisecond time interval, logic "1"
can continue to appear on the conductor 463.
However, if that inverter does not change the logic "1" on conductor 326 to logic "0"
~efore the end of that time interval, "0"
will automatically appear on that conductor.
When the leading edge of the green-ink face of an authentic U.S. one dollar bill i9 placed on the platform 32 and is then moved inwardly into the space defined by the lower and upper platens 40 and 118~ respeatively, the leading edge of that bill will engage the leading edge 150 o the actuator 148 and will thereby raise that actuator to close the switch 146~
The~eupon~, the emitter of transistor 332 will be connected to ground; and that transistor will become conductive. The collector of that transistor will apply logic "zero" to the upper inpu~ o~ NA~D gate 334 and al~o to the input of inverter 484, to the upper input of NA~D gate 498, and to the upper input of NA~D gate 510 in Fig. 13. r~he inverter 484 will apply logic "1"
to the cathode of diode 490 and to the upper input 80.

~ 38~
of N~D gate 506; but the signal at the input of inverter 488 will remain logic "0", becau~e diode 494 will 9till be forward-biased; and hence that inverter will back-bias the diode 530. The logic "0" at khe upper input of the NAND gate 498 will leave the output of that ~A~D gate logic "1", and the logic "0" at the upper input of ~he NA~D
gate 510 will leave the output of that ~AND gate logic "1". The logic "1" at the upper input of NAND gate 506 will not change the output of that NAND gate because aond~c~or 324 applie~ log~c "0"
to the lower input of khat NAND gate. This means that logia " 1" will remain on the motor reverse line 463; and hence the motor reverse relay coil 468 will remain de-energized, and the relay contacts 470 and 472 will remain in the "forward" position of Fig~ 14.
The output of MAND gate 334 will become l~gic "1", and the inverter 426 will respond to that logia "1" to apply logic "0" to the lower input of ~AND ga~e 358; and that logic "O" and the logic "0" at the upper lower input of that NAND
gate will keep the output of that NAND gate at logic "1". As a result, the transistor 366 will ~3~

continue to be non-conductive; and the inverter 380 will continue to apply logic "1" to the bases of transistors 332, 342 and 350.
The logic "1" a~ the output of ~A~D
yate 334 will initiatQ the time delay of between six and twelve seconds which i9 provided by the Gros~ Time Delay Circuit 400, all as explained hereinbefore; and, during that time delay, the transi~tor 406 of that Gross Time Delay Circuit will develop and maintain logic "1" on the conductor 422. The resulting application o~ logic "1" to pin 13 o~ ~oltage regulator 534 in ~ig.
14 will cause that ~oltage regulator to develop a pO9 itive voltage o~ about fifteen volts at the pin 9 thereof, and hence at the base of transistor 554. Thereupon, that transistor will become conductive at the saturation level9 and will permit subs~antial current to flow from conductor 569 via the movable and left-hand relay contacts 470, motor 562, the left-hand and mo~able relay contacts 472, transistor 554, and resistors 556 and 558 to ground. As a result, the mo~o~
562 will ~tart operatin~ in the "~orward"
direction; and the lower runs of the belts 196 and 198 will grip the leading edge of the bill as that leading edge i9 pushed into engagement with those runs.

~2.

As the motor 562 op~rates in the "forward" direction, the A.C.generator 560 will develop a feed kack 9 ignal which will be rectified by the diode 550 and filtered by the capacitor 548 and then applied to the base oE transistor 538~ That rectified and iltered signal will render the transistor 538 conductive, and thus will cause a voltage to de~elop at the movable contact of the potentiometer 544. That rectiEied and filtered signal will be a u~ction o the speed o ~he motor 562, and hence the degree oE conductivit~ of transiator 538 and the voltage at the movable contact of potentiome-ter 544, will be a function of the speed o~ that motor.
The voltage regulator 534 maintains a regulated positive five and six-tenths volts at the pin 6 thereof: and that voltage i9 directly applied to the pin 5 -- which is the inverting input of a differential amplifier within the voltage regulator 5340 The pin 4 is the non-in~erting input of that diE-Eerential ampliEier;

83.

~3~

and ~hat differential ampli~ier will act, whenever the voltage at the pin 4 i9 below five and 9iX~
tenths volts, to apply an error signal to the base o transistor 554 which will cause that transistor to supply enough curre~t to the motor 562 to enable that motor to increase its speed. Consequently, that motor will quickly reach its intended speed--which i9 determined by the setting oE the movable contacts o~ the potentiometer 544.
The output shaft o khe mokor 562 will drive the worm gear 202 in a direction which will enable the worm wheel 200, the sha~ 182 and the pulleys 192 and 194 to cause the lower runs ~ .
of the belts 196 and 198 to move inwardly of the paper currency validator 30 at a speed of between nine and one-tenth and nine and ive-tenths of an inch per second. A~ter the leading edge o~ the bill has been gripped by those lcwer runs and has started moving inwardly o~ the paper currency validator 30; that leading edge will quickly be moved into engagement with the leading edge 159 of actuator 158 to raise that actuator and thereby clo~e the switch 156. Thereupon, the emitter o~ tran~istor 3~2 will be conneated to ground;
and that transistor will become conductive and will apply logic "0" to the middle input of 84.

~A~D gate 334 and to the input of inverter 430 and to the cathode of diode 492 in Fig.
13. The logic "0" at the middle input of NA~D gate 334 will not change the output of that ~AND gate, becau~e that output became logic "1" when transisto.r 332 became conductive.
Also the logic "0" at the cathode of diode 492 will not change the voltage at the input of inverter 488 in Fig. 13, because diode 494 will still be forward-biased by the logic "0" at the output of inverter 446. ~owe~er, the applicatlon of loglc "0" to the input of inverter 430 will make the output of that inverter logic "1", and thus will back-bias diode 434 and diode 500 in Fig. 13.
The back-biasing of diode 500 will not be signi-ficant at this time, because the logic "0" which the closing of switch 146 applied, and continues to apply, to the upp r input of ~A~D gate 498 will continue to cause that ~AND gate to develop logic "1" at the output thereof. The back-biasing of diode 434 will, however, be significant because it will initiate the five hundred and fifty millisecond time delay provided by the Po~ional Time Delay Circuit 428, all as explained herein-be.~ore.

85.

' -The motor 562 will continue to cause the belts 196 and 198 to move the bill inwardly of the paper cur-rency validator 30; and, if that bill is being moved in-wardly at the rate of nine and three-tenths of an inch per second, the leading edge of that bill will engage the actuator 164 and close the switch 162 about four hun-dred and fi~ty milliseconds after that leading edge caused the actuator 158 to close the switch 156. As the switch 162 is closed, the transistor 350 will become con-ductive, and logic "0" will appear at the lower input of NAND gate 334, and at the cathode of diode 384, at the cathode o diode 432 in Fig. 13, at the input of inverter 446, at the cathod~ o~ diode 502, and at the mlddle input of NAND gate 506. The logic "0" at the lower ~nput o~
NAND gate 334 will not be signiicant because the output of that NAND gate was, and will continue to be, logic "1".
The logic "0" at the cathode of diode 384 will forward-bias that diode and cause the Vend Time Circuit 382 to remove the forward-bias on the base-emitter circuit of transistor 398 of the Vend Time Circuit 382, all as ex-plained hereinbefore. The logic "0" at the cathode of diode 432 in Fig. 13 will forward-bias that diode; and hence capacitor 440 in the Positional Time Delay Circuit 428 will discharge to keep the voltage at the emitter o~
transistor 442 from reaching the Zener voltage o that transistor, all as explained hereinbefore. The logic "0"
at the cathode of diode 502 will forward-bias that di-ode, and thus will apply logic "0" to the lower input ~6.

of that NAND gate will not change that output. The logic "0" at the middle input of NAND gate 506 will not change the output of that NAND gate because conductor 324 has been applying logic "0" to the lower input of that NAND gate. The logic "0" at the input of the in-verter 446 of the Further Time Delay Circuit 444 will initiate the time interval of two hundred and fifty to three hundred milliseconds which that Further Time Delay Circuit provides, all as explained hereinbefore.
Shortly after the leading edge of the bill causes the actuator 164 to close the switch 162, the vertical grid lines in the leading half of the portrait background of ~h~ bill will move into registry with the air gap of the magnetic head 208. That magn~tic head will xespond to those vertical grid lines to develop a signal which has a frequency of approximately eleven hundred and fifty Hertz; and the capacitor 260 will couple that signal to the base of transistor 248. That transistor and the transistor 250 will amplify that sig-nal; and the capacitor 266 will couple the resulting amplified signal to the base of transistor 274. That transistor and the inverter 276 will square that ampli-fied signal and then apply it to the tuned circuit of the Frequency-Sensing Circuit 280. Because that bill i9 an authentic U.S. one dollar bill, because the black-ink face of that bill confronts the magnetic head 208, and because that bill has the vertical grid lines .in the portrait background thereof moved past the air gap of that magnetic head at a rate of about eleven hundred and fifty per second, a voltage will develop across the inductor 282 of that Fre~uency-Sensing Circuit in a manner which is substantially identical to the manner in which a voltage is developed across the induc-tor in the tuned circuit in Smith et al United States patent No. 3,245,534 for Method and Apparatus For Magnetic Currency Detectors which was granted on April 12, 1966.
The d.iode 290 will apply khak voltage to the base oE
transistor 296; and that voltage will r~nder that trans-istor conductive. Thereupon, the transistor 298 will become conductive and will apply logic "0" to the upper input of NAWD gate 312. The output of that NAND gate will tend to become logic "l"; but because the output of NAND gate 314 is logic "0", the output of NAND gate 312 and the voltage on conductors 324 and 325 will re-main logic "0".
Approximately one hundred and eight-eight milliseconds after the leading edge of the bill caused the actuator 164 to close the switch 162, the vertical grid lines in the leading half of the portrait back-ground will move into register with the air gap of the magnetic head 210, and the vertical grid lines in the trailing half of that portrait background will ~love into register with the air gap of the m~gnetic head 208.

8~.

Those magnetic heads will respond to those vertical grid lines to develop signals which have frequencies of approximately eleven hundred and fifty Hert2; and the capacitor 260 and its counterpart in the Amplifier 270 will couple those signals to the bases of transistor 248 and of its counterpart. The Amplifiers 246 and 270 will amplify the signals from the magnetie heads 208 and 210, an~ the Squaring Circuits 272 and 278 will square the amplified signals and apply them to the tuned cireuits of the Frequency-Sensing Circuits 280 and 292.
Beeause that bill is an authentic U.S. one dollar bill, beeause the blaek-ink faee of that bill con~ronts the magnetic heads 208 and 210, and beeause that blll ha~ th~
vertieal grid lines in the portrait baekground thereof moved past the air gap o~ eaeh of those magnetie heads at a rate of about eleven hundred and fifty per seeond, the diode 290 and its eounterpart will supply signals to the transistors 296 and 297 whieh will render those trans-istors eonduetive. Thereupon, the transistors 298 and : 20 299 will beeome conductive; and logie "0" signals will be applied to the upper input of NAND gate 312 and to the lower input of NAND gate 314. ~ogie "1" will then appear at the outputs of both of the NAND gates 312 and 314, and thus on eonduetors 324 and 325, at the input of inverter 316, on the upper input of NAND gate 358 in Fig. 13, at the collector of transistor 398, at the anode of diode 528, and at the lower input of NAND gata 506. The inver-ter 316 of the Validation Latch Cireuit 310 will apply 89.

logic "0" to the lower input of NAND gate 312 and to the upper input of NAND gate 314; and that logic "0"
will keep the outputs of those NAND gates at logic "1"
after the vertical grid lines in the leading and trail-ing halves of the portrait background of the bill have been moved inwardly beyond the air gaps, respectively, of the magnetic heads 210 and 208. The Validation Latch Circuit 310 then will maintain logic "1" on conductors 324 and 325 until the transistor 398 in the Vend Time Circuit 382 is subsequently rendered conductive during the normal operation of the paper currency validator 30.
The logic "0" at the output o inv~rter 316 also will be applied to the aathode o~ diode 4~8 in the Further Time Delay Circuit 444 in Fig. 13; and khat di-ode will become forward-biased to discharge the capaci tor 452. This means that although the inverter 446 will keep the diode 450 back-biased, the capacitor 452 will become discharged; and hence the voltage at the emitter of transistor 458 will not be able to reach the ``; 20 Zener voltage of that transistor, all as explained here-inbefore. Consequently, the transistor 462 will be able to remain non-conductive, and thereby keep logic "1" on conductor 463. The logic "0" at the output of inverter 312 also will appear at the lower input o~ NAND gate 510.

,qo-The logic "1" on the upper input of NAND gate 358 in Fig. 12 will not be able to change the output of that NAND gate, because the switches 146, 156 and 162, the transistors 332, 342 and 350, the NAND gate 334 and the inverter 426 will coact to apply logic "0" to the lower input of that NAND gate. The logic "1" on the collector of the transistor 398 in Fig. 12 will not be able to render that transistor conductive, because the diode 384 in the Vend Tlme Circuit 382 is forward-biased and is causing the transistor 392 to apply zero voltage to the base of transistor 398. The lo~ic "1" at the anode of diode 528 in Fig. 13 will not be able to or-ward-bias that diode, becau~e the inverter 52~ of the Reverse Relay Latch Circ~it 518 is applying logic "1"
to the cathode of that diode; and hence that Reverse Relay Latch Circuit will permit logic "1" to remain on the conductox 463. The logic "1" at the lower input of NAND gate 506 will not change the output of that NAND
gate, because the logic "0" at the middle input of that NAND gate will cause that NAND gate to continue to pro-vide logic "1" at the output thereof. The logic "0" at the lower input of NAND gate 510 will not change the output of that NAND gate, because the logic "0" at the upper input o that NAND gate will cause that NAND gate to continue to provide logic "1" at the output thereof.
The immediatel~-effective results of the simultaneous passage of the vertical grid lines in the two halves of 91.

the portrait background past the air gaps of the mag-netic heads 208 and 210 are the discharging of the capacitor 452 of the Further Time Delay Circuit 444 to keep the transistor 4~2 from being conductive, and the applying of logic "1" to the conductor 463.
Shortly after the vertical grid lines in the trailing hal~ of the por~rait background of the bill are moved inwardly beyond the air gap of the magnetic head 208, those vertical grid lines will move into en-gagement with the air gap of the magnetic head 210; andthose vertical grid lines will coact with the latter magnetic head to develop signal~. q'he Ampli~ier 270, the Squaring Circuit 27~, the Fre~uenc~-Sensing circuit 292, and the Threshold Detector 308 will respond to those signals to apply logic "0" to the lower input of NAND gate 314. However, because the Validation Latch Circuit 310 can apply logic "1" to the conductor 324 only when both magnetic heads 208 and 210 are sensing vertical grid lines at the same instant, the applica-tion of the logic "0" solely to the lower input of NANDgate 314 could not be significant at any time -- and doubly so ~hen the output of that NAND gate was previ-ously changed to logic "1", and is being held at that value b~ the Validation Latch circuit 310. Consequently, the sub-circuit of Fig. 11 effectively ignores the sig-nals which develop as the trailing hal~ o~ the portrait background is moved past the air gap o~ the magnetic head 210.

, .

9~ .

31 ~3~

As the motor 562 and the belts 196 and 198 continue to move the bill inwardly of the paper cur-rency validator 30, the trailing edge of that bill will move out from under the trailing edge 152 of the switch actuator 148, and will thereby permit the switch 146 to re-open. Thereupon, logic "1" will appear at the upper input o~ NAND gate 334, at the in-put of inverter 484 in Fig. 13, at the upper input of NAND gate 498, and at the upper input of NAND gate 510.
The logic "1" at the upper input of NAND yate 334 will not change the output of that NAND gate because the switches 156 and 162 will still be closed and will be applying logic "~" to the micldle and lower inp~ts of that NAND gate. The logic "1" at the upper input o NAND gate ~98 will not change the output o that NAND
gate because the diode 502 is maintaining logic "0" at the lower input of that NAND gate; and the logic "1"
at the upper input of NAND gate 510 will not change the output of that NAND gate because conductor 326 is apply-~ 20 ing logic "0" at the lower input of that NAND gate~
; The logic "1" at the input of inverter 484 will cause that inverter to appIy logic "0" to the cathode of di-ode 490 in Fig. 13 and to the upper input of NAND gate 506. The logic "0" at the cathode o:E diode 490 will not change the signal applied to the input of inverter 488, because the diode 492 has been appl~ing logic "0" to that input. The logic "0" at the upper input of NAND
gate 506 will not change the output of that NAND gate 93.

~3~
because the logic "0" will continue to appear at the middle input of that NAND gate.
Continued inward movement of the bill will cause the trailing edge o that bill to move out from under the trailing edge 161 of the actuator 158, and thereby permit the switch 156 to re-open. Thereupon, logic "1ll will be applied to the middle input of NAND
gate 334, to the input of inverter 430, and to the cathode of diode 492. The logic "1" at the middle in-put of NAND gate 334 will not change the output of thatNAND gate because the switch 162 will still be closed and will be applying logic "0" to the low~r input o~
that NAND gate. The logic "1" at the cathode o diode 492 will not change the signal applied to the input o ; inverter 488, because the diode 490 will be applying logic "0" to the input of that inverter. The logic "l"
at the input of inverter 430 will cause that inverter to apply logic "0" to the cathode o~ diode 434 and also to the cathode of diode S00. The logic "0" at the cath-ode of diode 434 will connect the upper terminal o cap-acitor 440 to ground via the inverter 430; but that capacitor was previously discharged via diode 432, con-ductor 352, transistor 350 and switch 162. The logic "0" at the cathode of diode 500 will not change the output of NAND gate 498, because the diode 502 will be applying logic "0" to the lower input o that NAND gate.

~3~
Further inward movement of the bill will cause the trailing edge of that bill to move out from under the trailing edge 168 of the actuator 166, and thereby permit the switch 162 to re-open. Thereupon, logic "1" will be applied to the lower input af NAND
gate 334, to the cathode of diode 384, to the cakhode of diode 432 in Fig. 13, to khe input of inverter 446, to the cathode of diode 502, and to the middle inpuk of NAND gate 506. The logic "1" at the cathode of di~
ode 384 will back-bias thak diode; and hence the capa-citor 388 will begin to charge. However, the charge on that capa~itor will take kime to reach the Zener voltage of the transistor 392, and henae the transis-tor 398 will remain non-conductive for one hundred and ~iky milliseconds. The logic "1" ak khe cathode of diode 432 in Fig. 13 will back-bias that diode; but the capacitor 440 will remain discharged, because the diode 434 is forward-biased by the inverter 430. The logic "1" at the cathode of diode 502 in Fig. 13 will back-bias thak diode; but the voltage at the output of NAND gate 498 will not change, because inverter 430 and diode 500 are applying logic "0" ko khe lower input of that NAND gate. The logic "1" ak khe middle inpuk of NAND gake 506 will not change the oukput o that N~ND
gate because the inverter 484 is applying logic "0" to khe upper input of khat NAND gate. The logic "1" at the input of inverker 446 will cause khat inverker to apply 95.

:~3~
logic "0" to the cathode of diode 450, to the cathode of diode 494, and to the middle input of NAND gate 510.
The logic "0" at the cathode of diode 450 will forward-bias that diode, and thereby keep the capacitor 452 discharged via that diode and inverter 446. The logic "0" at the cathode of diode 494 will forward bias that diode, and thereby coact with diode 490 to maintain ; logic "0" at the input of inverter 488. The logic "0"
at the middle input of NAND gate 510 will not change the output of that NAND gate hecause the conductor 326 is applying logic "0" to the lower input of that NAND
gate.
The application o~ lo~ic "l" to the lower in-put o NAND gate 334 will cause the output of that N~ND
gate to become logic "0"; and thereupon, logic lloll will appear at the input of inverter 426, at the upper ter minal of capacitor 408 in the Gross Time Delay Circuit 400, and at the cathode of diode 532 in Fig. 130 The logic ll 0 ll at the upper terminal of capacitor 408 in the 2~ Gross Time Delay Circuit will forward-bias the diode 412, and thus will apply ground voltage to the base of transistor 402 - thereby permitting that transistor to become non-conductive. The transistor 404 then will become non-conductive to xender the transistor 406 con-ductive; and, thereupon, the latter transistor will apply logic lloll to pin 13 of the voltage regulator 53~
in Fig. 14 via conductor ~22. The voltage at the pin 9 96.

of that voltage regulator will then drop to zero, and transistor 554 will become non-conductive. At this time, the motor 562 will become de-energized; and the diode 570 will dissipate the inductive energy within that motor. However, the shaft 182, the pulleys 192 and 194, and the belts 196 and 198 will coact long enough to permik the lower runs of those belts to move the trailing edge of the bill wholly inwardly of the paper currency validator 30 and into a cash box or other bill-receiving device at the outlet of that paper curxency valida~or.
~ he logic "0" at the cathode o diode 532 in Fig. 13 will forward-bias that diode; and hence logic "0" will appear at the anode of diode 526 and at the input of inverter 522. The logic "0" at the anode of diode 526 will back-bias that diode; and the logic "0"
at the input of inverter 522 will cause that inverter to back-bias diodes 5~4 and 528, Consequently, logic "1" will continue to appear on conductor 463 and on conductor 324.
The logic "0" on the input of inverter 426 will cause that inverter to apply logic "1" to the lower input o~ NAND gate 358. Because logic "1" ap-pears on conductor 325, the output of NAND gate 358 becomes logic "0"; and inverter 360 applies logic "1"
to the input of inverter 380 and also to the base o~
transistor 366 via resi.stor 362 and transistor 364.

: 97.

Thereupon, the transistor 366 will become conductive and will energize the relay coil 368 -- with conse-quent closing of the relay contacts 372. Those relay contacts will send a vend signal to the vending mach-ine via conductors 374 and 376.
The application of logic "l" to the input of inverte~ 380 will cause that inverter to apply logic "0"
to the bases of transistors 332, 342 and 350 via resis-tors 338, 346 and 354, respectively. Thereupon, all of those transistors will become non-conductive and will remain non~conductive. This is desirable, because it will keep an~ further closin~ of an~ of the swltches 146, 156 and 162 from chanyin~ the output state of the NAND gate 334 -- whether the closing of an~ of those switches is due to "contact bounce", to the insertion of a foreign object or to the insertion of a further bill.
The capacitor 388 in the Vend Time circuit 382 will continue to charge; and, about one hu~dred and fif-ty milliseconds after the switch 162 re-opened, the vol-tage a~ the emitter of transistor 392 will exceed the Zener voltage of that transistor, and the transistor 398 will become conductive. The resulting logic "0" on conductors 325 and 324 will be applied to the upper in-put of NAND gate 358, to the input of inverter 316 in Fig. 11, to the anode of diode 528 in Fig. 13, and to the lower input of NAND gate 506. The logic "0" at the 9~_ ~V38~

anode of diode 528 will back-bias that diode; and the logic "0" at the lower input of NAND gate 506 will leave the output of that NAND gate unchanged. The logic "0"
at the upper input of NAND gate 358 will make the out-put of that NAND gate logic "l"; and inverter 360 will respond to that logic "1" to apply logic "0" to the input of inverter 380 and to the base of transistor 366.
Inverter 380 will apply logic "1" to the bases of trans-istors 332, 342 and 350 via resistors 338, 346 and 354, respectively; but those transistors will remain non-conductive because all of the switches 146, 156 and 162 will be open. The logic "0" at the base of transistor 366 will render that transistor non-conductive; and, thereupon, the relay coil 368 will become de-energized, and the diode 370 will dissipate the inductive energy in that relay coil. At this time, the relay contacts 372 will re-open, and thus will terminate the vend signal which they had been applying to the vending machine.
The logic "0" at the input of inverter 316 will cause that inverter to apply logic "1" to the lower input of NAND gate 312, to the upper input of NAND gate 314, to the cathode of diode 448 in Fig. 13, and to the lower input of NAND gate 510. The logic "1" at the cathode of diode 448 in Fig. 13 will back-bias that di-ode; but, because inverter 446 is maintaining logic "0"
at the cathode of diode 450, the capacitor 452 will _qq-~315~
continue to remain in its discharged state. The logic "1" at the lower input of NAND gate 510 will not change the output of that NAND gate, because the inverter 446 will continue to apply logic "0" to the middle input of that NAND gate. The logic "1" at the lower input of NAND gate 312 and the logic "1" at the upper input o NAND gate 314 will cause those NAND gates to develop logic "0" at the outputs thereo~. The inverter 316 will respond to that logic "0" to maintain logic "1" at the lQ lower input o~ NAND gate 312 and at the upper input o NAND gate 314; and hence the Validation I.atch Circuit 310 will act to maintain logic "0" on the conductors 325 and 324. The transisto~ 398 will respond to that logic "0" to become non-conductive, even though the voltage at the base o that transistor tends to forward-bias that transistor. The logic "0" at the anode o di-ode 528 will enable that diode to remain back~biased;
' and the logic "0" at the lower input of NAND gate 506 will enable the output of that NAND gate to remain logic "1". At this time, the paper currency validator 30 will be~,~.in its standby condition; and it will remain in that condition until one of the switches 146, 156 or 152 is again closed.
I a person were to insert the leading edge ; of a bill into the paper currency validator 30, and were then to attempt to keep that bill rom moving inwardly at the normal rate of speed o between nine 100.

and one-tenth and nine and five-tenths of an inch per second, the amplitude of the output voltage of the A.C. generator 560 would decrease slightly. The transistor 538 would am-plify that decrease in voltage and would provide an appre-ciable change in the voltage at the movable contact of the potentiometer 544. The voltage regulator 534 would then mat-erially increase the value of the positive voltage which it applies to the base of transistor 554 to enable that trans-istor to materially increase the current flowing through the motor 562.
That increase in current will increase the voltage at khe emitter of that transistor, and hence at th~ upper input of the di~erential ampli~ier 574. The movable con~
tact of the potentiometer 580 will usually be set to estab-lish a reference voltage, at the lower input of that dif-ferential amplifier, which will be higher than the normal ' voltage at the emitter of transistor 554, and which will correspond to the voltage that will develop at that emitter ~: if a person retards or halts the inward movement of a bill.
. 20 As long as the current flowing through the motor 562 is normal, the voltage at the emitter of transistor 554 will be below the reference voltage at the lower input of the differential amplifier 574; and hence the output of that differential ampliier will be logic "0". However, :if the current flowing through the motor 562 increases to the point where the voltage at the emitter of transistor 554 is greater than the reference voltage at the lower input of the differential. ampliier 574, the output o that difer-ential amplifier will change to logic "l"; and the inverter 101.

0~
586 will apply logic "0" to conductor 328. That logic "0"
will forward-bias the diodes 320 and 322 in Fig. 11; and hence the bases of transistors 298 and 299 will be grounded.
Consequently, those transistors could not become conductive even if the magnetic heads 208 and 210 were to coact with the Amplifiers 246 and 270, the Squaring Circuits 272 and 278, and the Frequency-Sensing Circuits 280 and 292 to render the transistors 296 and 297 of the Threshold Detectors 294 and 308 conductive. This means that if a person appreciably retards the rate of movement of a bill inwardly of the paper currency detector 30, the Current-Sensing Circuit 572 in Fig. 14 will keep that paper currency validator from devel-oping a validation signal on conductors 324 and 325; and hence the motor 562 will reverse, and will cause the bill to be backed out of that paper currency validator in the same way in which that motor reverses and backs out a bill that is inserted with its green-ink face up, all as explain-ed hereinafter.
Because the Amplitude-Responsive Control Circuit 533 of Fig. 14 amplifies the output voltage of the A.C.
generator 560, even a visually-imperceptible retardation in the speed of an inserted bill can cause the voltage regu-lator 534 to materially increase the voltage at the emitter of transistor 554. This means that the Current-Sensing Circuit 572 can inhibit the application of a validation signal to the conductor 324 even if the vertical grid lines in the portrait background of a bill are permitted to move 102.

past the air gaps of the magnetic heads 208 and 210 at a rate just slightly less than the pre-set rate. AS a re-sult, that Current-Sensing Circuit can defeat efforts, to attain unauthorized operation of the paper currency vali-dator 30l which the Frequency-Sensing Circuits could not defeat.
The Currency-Sensing ~ircuit 572 is particularly important where the paper currency validator 30 is modified to enable it to distinguish between U.S. one dollar bills and U.S. five dollar bills. Because the spacing between the vertical grid lines in the portrait background of a U.S. five dollar bill is appreciabl~ greater than the spac-ing between the vertical grid lines in the portrait back-ground of a U.S. one dollar bill, lk is possible to equip the paper currency validator 30 with Frequency-Sensing Circuits which sense one center fre~uency that corresponds to one dollar bills and to equip that paper currency vali-dator with other Frequency-Sensing circuits which sense a . second and different center frequency that corresponds to five dollar bills. If a person were able to retard the : rate at which the motor 562 moved a one dollar bill inward-ly of the paper currency validator 30 to a value which caused the vertical grid lines in the portrait background of that bill to move past the air gaps of the magnetic heads 2Q8 and 21Q at the same rate at which the vertical grid lines in the portrait background of a five dollar ~ill are normally moved past those air gaps, the vertical grid lines 103.

~: ' ' ' .

~3~
in the portrait background of the one dollar bill could generate signals that closely simulated the signals which the vertical grid lines in the portrait background of a five dollar bill could generate. As a result, ~he fre-quency-sensing circuits of that modified paper currency validator might be unable to defeat such an attempt to effect unauthorized operation of that paper currency vali-dator.
However, the Current-Sensing Circuit 572 would sense the increased motor current which transistor 538 and voltage regulator 534 would cause the transistor 554 to supply to the motor 562; and that Current-Sensin~ Circuit and inverter 586 would develop lo~ic "0" on concluctor 32~
and at the cathodes of diodes 320 and 322 -- thereby defeat-ing such an attempt to effect unauthori~ed operation of the paper currency validator 30. All of this means that even if the amplifiers, the squaring circuits, the frequency-sensing circuits, and the initial transistors of the thresh-old detectors in the five dollar section of a paper currency validator were to respond to the signals which were devel-oped by retarding the inward movement of a one dollar bill, the Current-Sensing Circuit 572 would forward-bias the di~
odes 320 and 322, and thereby keep the bases of transistors 298 and 299 at logic "0". In such event, the NAND gates 312 and 314 would continue to maintain logic "0" on con-ductors 32~ and 325, and would thereby prevent the devel-opment of a validation signal.

10~ .

~3~
As indicated particularly by Fig. 11, the inductors and the capacitors of the tuned circuits of the Frequency-Sensing Circuits 280 and 292 are fixed, ra~her than adjustable, inductors and capacitors. This is important; because the stability of fixed inductors tends to be greater than the stability o~ adjustable inductors of corresponding qualit~l and the stability of fixed capacitors tends to be greater than the stability of adiustable capacitors of corresponding quality.
Further, the cost of variable inductors is greater than the cost o fixed inductors of corresponding quality, and the cost of adjustable capacitors is higher than the cost o~ corresponding ~ualitv fixed capacitors.
Even where ~ixed inductors and fixed capacitors are used in the tuned circuits of the Frequency-Sensing Circuits 280 and 292, the manufacturing tolerances of such inductors can be as high as plus or minus two percent, and the manufacturing tolerances of such capacitors can be as high as plus or minus five percent. Because each of the tuned circuits, in the Frequency-Sensing Circuits 280 and 292, has two capacitors and an inductor, the total toler-ance variation in either of those tuned circuits could run as high as plus or minus ten percent and would commonly run as high as seven percent. This means that eve~ if the circuit boards of all o the paper currency validators 30, which were made in accordance with the principles and teachings of the present invention, were fabricated with ., ~3~
components which had the same nominal values J the center ~requencies of the tuned circuits of the Fr~quency-Sensing Circuits 280 and 292 of those circuit boards could vary as much as plus or minus ten percent and would commonly run as high as plus or minus seven percent.
The present invention makes it possible to gain the important benefits o greater stability and of lower costs, which the use of fixed inductors and of fixed capa-citors affords, by making it possible to set, and thereafter maintain/ the speed o~ the motor 562 at a value which is a function o the center frequencies of the tuned circuit9 of the Frecluenc~-Sensing Ci.rcuits 280 and 292. Speaiic-ally, the present invention aontempla~es the use o~ a vari-able fre~uency oscillator to determine the center fre-quency of each circuit board for a currency validator 30, and then contemplates the adjusting of the speed of the motor 562 to enable the vertical grid lines in the portrait background of a bill to pass the air gaps of the magnetic heads 208 and 210 at that fre~uency. Because the output shaft 203 of the motor 562 is directly geared to the pul-leys 192 and 194, the speed of the belts 196 and 198 is directly proportional to the speed of that motor; and hence it is possible to set any desired belt speed by appropriately setting the motor speed. The voltage across the series-connected resistors 556 and 558 will be a close indication of the speed of the motor 562; and, consequently, it is only necessary to connect the voltage across those -/oG--~, ~3~

series-connected resistors to an appropriate read out, and then adjust the position of tlle movable contact of the potentiometer 544 to set the desired motor speed.
In this way, the present invention makes it possible to make the speed of the inserted bills a function of the center frequencies of the tuned circuits of the Fre~uency-Sensiny Circuits 280 and 292 rather than to make those center fre~uencies a function of the speed of those bills. Not only does the present invention provide greater stability and less cost for its Fre-quency-Sensing Circuits, but it avoids the cost and bulk of a synchronous motor.
Once the speed o the motor 562 has be~n set, by appropriate adjustment o~ the position of the movable contact of potentiometer 544, the sub-circuit of Fig. 14 will hold that speed fixed within very close limits --despite line voltage variations and despite temperature variations varying from forty to one hundred and sixty degrees Fahrenheit. For example, if the speed of the motor 562 tends to decrease, the amplitude of the A.C.
voltage developed by the A.C. generator 560 also will de-crease, and hence the rectified and filtered voltage which is applied to the base of transistor 538 will be lower than normal. The resulting decrease in aonducti-vity of that transistor will appreciably reduce the vol- ' tage at the pin 4 of the voltage regulator 534; and hence that voltage regulator will cause the voltage at 107, the pin 9 to increase materially. Transistor 554 will respond to the material increase in voltage at the base thereo~ to materially increase the current flowing through the motor 562; and that motor will respond to that materially increased current to promptly increase the speed thereof to its pre-set value. As the speed of the motor 562 approaches its pre-set value, the vol-tage at pin 9 will return to its normal level; and hence the amount of current which the transistor 554 will per-mit to flow through that motor will return to a levelwhich will enable that motor to operate at its pre-set speed.
On the o~her hand, i ~he sp~d oE the motor 562 tends to increase rather than decrease, the ampli-tude of the A.C. voltage which is developed by the A.C.
generator 560 will increase; and hence the base of trans-istor 538 will receive an increased value of rectified and filtered voltage. The increased conductivity of that transistor will cause the voltage at the movable contact of potentiometer 544 to increase appreciably;
and the voltage regulator 534 will respond to that app-reciably increased voltage to materially reduce the val-ue of the voltage at the pin 9 thereof. The resulting material decrease in conductivity of the transistor 5S4 will materially decrease the value of the current flowing through the motor 562; and that motor will respond to that materially reduced current to promptly decrease the speed thereof to its pre-set value. As the speed of the motor 562 approaches its pre-~et speed, the voltage at pin g will tend to return to its normal value, and hence the amount of current which the trans-istor 554 will permit to flow through that motor will return to a level which will enable that motor to oper-ate at its pre-set speed. In this way, the sub~circuit of Fig. 14 will hold the speed of the motor 562 essen-tially constant at any pre-set value which is selected by an appropriate sekting of the movable contact o the potentiometer 544.
Pin 2 of the voltage regulator 53~ will coaat with the re~istor 558 to r~duae the ~alue of the signal at the pin 9 of that voltage regulator if the voltage at the pin 2 ever exceeds a predetermined value. This is desirable, because it will keep the value of the cur-ren-t flowing through motor 562 and the transistor 554 ~rom exceeding a safe level. For example, if something ~` were to happen to the motor 562 which tended to cause that motor to draw an excessive amount of current, the voltage at the upper terminal of the resistor 558 would rise; and, if that voltage reached seven-tenths of a volt, the voltage regulator 534 would reduce the voltage at the pin 9, and thus the current flowing through that motor, until the voltage at the upper terminal of that resistor fell below seven-tenths of a volt. In this way, the sub-circuit of Fig. 14 can respond to unduly-large values of motor current to reduce the conductivity 109.

of transistor 554, and thereby reduce the value of the current flowing through the motor 562.
The Frequency-Responsive Control Circuit 588 of Fig. 15 is an acceptable substitute for the Ampli-tude-Responsive Control Circuit 533 of Fig. 14. That frequency-responsive control circuit is not, per se, a part of the present invention; and it is disclosed herein solely to illustrate the adaptability of the circuitry of Figs. 11-13 to various speed-regulating control systems.
The output of the A.C. generator 560 in Fig.
15 is applied to the base o~ transistor 590 by r~si~tor 592; and the dlode 59a bypasses to gxound the neyative-going components of that output. The transistor 590 will respond to the signals from the A.C. genexator 560 to develop a square wave at the collector thereof which has a frequency that is equal to the frequency of those signals; and that sguare wave will be differentia-ted by the differentiator which consists of capacitor 600 and resistor 602. The resulting differentiated sig-nal will be supplied to pin 2 of the one-shot 606; and that one-shot will trigger on the negative-going edges of that differentiated signal. The output of the one~
shot 606 appears at the pin 3 thereof, and that output is applied to the base of transistor 630 by resistor 532. That output is a square wave with positive-going pulses that have durations less than one-half the 110, duration of each cycle of the output of the A.C. gen-erator 560. In one embodiment of the Frequency-Responsive Control Circuit 588 of Fig. 15, the dura-tion of each positive-going pulse is six-tenths of a millisecond whereas the duration of each cycle of the output of the A.C. generator 560 is one and one-quarker of a millisecond. The transistor 630 will invert the square wave; and each negative-going pulse of that inverted square wave will have a duration of about six-. 10 tenkhs of a millisecond.
Resiskors 626, 63~, 636, 638 and capacitors 6~0 and 6~2 constitute an integrat~ng network; and that integrating network will integrate the negative-going pulses o the square wave at the collector of transistor 630. The output of that integraking network is applied to khe upper input terminal of the operational amplifier 650; and khat output is a D.C. voltage with negligible ripple. The value of khak D.C. voltage is proportional : to the ratio of the duration of the negative-going pulses of the s~uare wave to the duration of each cycle of the A.C. signal from the A.C. generator 560. Consequently, khak D.C. voltage is proporkional ko khe frequency of the signal which is developed by that A.C. generator.
The upper input kerminal o:E the operational amplifier 650 is the non-inverting input of thak opera-kional ampliEier, whereas khe lower input kerminal of that operational amplifier is an inverting input.

111.

~L~3~
Resistors 644 and 648 and the potentiometer 646 establish a reference voltage which is applied to the lower input of the operational amplifier 650; and hence the output of that operational amplifier is proportional to the difference between the voltages which are applied to the upper and lower inputs there-of. Because the D.C. voltage which is applied to the upper input of the operational amplifier 650 is pro-portional to the frequency of the signal developed by the A.C. generator 560, whereas the voltage which is applied to the lower input o~ that operational ampli-~ier is a re~erence voltage, the output of that oper-ational amplifier is an error voltage which is propor-tional to the extent to which the speed of the motor i 560 varies rom its selected value.
If the speed of the motor 562 tends to de-crease, the frequency of the signal which is developed by the A.C. generator 560 will also decrease, and hence the voltage that is supplied to the upper terminal of the operational amplifier 650 will tend to decrease.
The output of that operational amplifier will, however, increase, and will thereby apply a signal to the base of transistor 670 which will tend to render that trans-istor more conductive -~ with a corresponding increase in the value of the current ~lowing through the motor 562. As the speed of that motor increases to its pre-set value, the error signal will decrease and the 112, ~3B~

conductivity of the transistor 670 -- and hence the value of the current flowing through the motor 562 --will return to their pre-set levels. On the other hand, if the speed of the motor 562 tends to increase, the frequency of the signal which is developed by the A.C. generator 560 also will increase, and hence the voltage that is applied to the upper input of opera-tional amplifier 650 will tend to increase. The out-put of that operational amplifier will, however, de-crease, and will thereby apply a signal to the baseof transistor 670 which will tend to render that trans-istor less conduct:Lve -- with A correspondin~ decrease in the value of the curr~nt ~lowin~ through th~ motor 562. As the speed of that motor decreases to its pre-set value, the error signal will decrease and the con-ductivity of the transistor 670 -- and hence the value of the current flowing through the motor 562 -- will return to their pre-set levels. The sub-circuit of Fig. 15, like the sub-circuit of Fig. 14, is an under-damped system, and thus will provide a desirably rapidresponse.
The transistor 624 is connected in parallel with the transistor 630, and it can be rendered conduc-tive to shunt the transistor 630 and thereby halt the supplying of current to the motor 562. The transistor 624 will be rendered conductive, and thus will halt the supplying of current to the motor 562, whenever 113.

~38~
the output of NAND gate 334 in Fig. 12 is logic "0".
At such time, the Gross Time Delay Circuit 400 will b~
applying logic "0" to the conductor 422; and the invert-er 620 in Fig. 15 will respond to that logic "0" to ap-ply logic "1" to the base of transistor 624 ~- thereby rendering that transistor conductive. Consequently, as long as the output of NAND gate 334 in Fig. 12 is logic "0", the motor 562 will be at rest. However, when the output of NAND gate 334 is logic "1", as it will become when any one of the switches 146, 156 and 162 is closed, the inverter 620 in Fig. 15 will apply logic "0" to the base of transistor 624 -- thereb~ rendering that trans-istor non-conductive. ~'hereupon, the Frequency-Respon-sive Control Circuit 588 will energize the motor 562, and will cau~e it to operate at the speed pre-set by the ; setting of the movable contact of potentiometer 646.
The voltage at the emitter of transistor 670, of the Frequency-Responsive Control Circuit 588 in Fig.
15, is applied to the upper input of the differential amplifier 574 of the Current-Sensing Circuit S72 -- in the same way in which the voltage at the emitker of transistor 554 of the Amplitude-Responsive Control Cir-; cuit 533 in Fig. 14 is applied to the upper input of that di~ferential amplifier. The resistors 578 and 582 and the potentiometer 580 in Fig. 15 apply a reference vol-tage to the lower input of the differential amplifier 114.

574 -- in the same way in which the identically numbered resistors and potentiometer supply a reference voltage to the lower input of the differential amplifier 574 in Fig. 14. Consequently, the diferential amplifier 574 in Fig. 15 can cause the inverter 586 to forward-bias the diodes 320 and 322 in Fig. 11 if the current flowing through the motor 562 exceeds a predetermined value. As a result, the Current-Sensing Circuit 572 in Fig. 15, like the identically-numbered Current-Sensing Circuit in Fig. 14, can inhibit validation if a person inserts a bill into the paper currency validator 30, and then at-tempts to retard or halt the inward mov~ment o~ that bill.
I~ a person were, deliberately or inadvertent-ly, to insert a bill so the black-ink face thereof was directed downwardly rather than upwardly, the paper cur-rency validator 30 would move that bill inwardly thereof, but the magnetic heads 208 and 210 would be unable to develop signals which could cause the Frequency-Sensing Circuits 280 and 292 to actuate the Threshold Detectors 294 and 308. As a.:result, the NAND gates 312 and 314 would continue to maintain logic "0" at the outputs thereof, and would thereby cause the inverter 316 in Fig. 11 to maintain logic "1" on conductor 3~6 -- and thus at the cathode of diode 448 in the Further Time Delay Circuit 444 in Fig. 313 and also at the lower input of NAND gate 510 in the Switch-Checking Circuit 508. As the leading edge of the inverted bill engages the actu-ator 164 to close the switch 162, logic "0" will appear 115.

on the conductor 352, and hence at the input o~ in-verter 446 of the Further ~ime Delay Circuit 444 in ; Fi~. 13~ At such time, both of the diodes 448 and 450 will be back-biased; and hence Further Time Delay Cir-cuit 444 will initiate its time delay of from two hun-dred and fifty to three hundred milliseconds.
Because the magnetic heads 208 and 210 will be unable to coact with the green-ink face of a dollar bill to develop signals which could cause the Frequency-Sen-sing Circuits 280 and 292 to actuate the Threshold De-tectors 294 and 308, the logic "1" on conducto~ 3~6 w~ll not change to loyic "0" during the time delay Oe ~he Fur-ther Time Delay Circuit 44~. Con~equently, at the end of that time delày, the voltage across the capacitor 452 of that Further Time Delay Circuit will exceed the Zener voltage of transistor 458. Thereupon, the transistor 462 will become conductive and will change the logic "1" on the conductor 463 to logic "0". The inverter 520 in the Reverse Relay Latch Circuit 518 will respond to the con-sequent application of logic "0" to the input thereof to apply logic "1" to the base of transistor 476, thereby rendering that transistor conductive. Current then will flow through the relay coil 468, transistor 47~ and re-sistor 478 to ground, and will thereby energize that re-lay coil. The movable relay contacts 470 and 472 in Fig.
14 will promptly shift into engagement with the right-hand fixed relay contacts 470 and 472, respectively,and thereby cause the motor 562 to reverse its direction of rotation. The belts 196 and 198 will stop moving the bill inwardly of the paper currency validator 30 and, instead, will start moving that bill outwardly of that paper currency validator.
The NAND gate 334 in Fig. 12 will have logic "1" at the output thereof; and the resulting logic "1"
at the cathode of diode 532 in Fig. 13 will back-bias that diode. When the NAND gate 334 changed the output thereof to logic "1" and before the Further Time Delay Circuit 444 rendered the transistor 462 conducti~e, th~
diode 532 became ~ack-bia~ed and could no long~r back-bias the diode 526. ~t that time, the inverter 520 forward-biased the latter diode, and thus enabled that diode to apply logic "0" to the input of inverter 522 -- to back-bias both of the diodes 524 and 528. However, when the Further Time Delay Circuit 444 rendered the transistor 462 conductive, and the output of inverter 520 became logic "1", the diode 526 became back-biased j and could no longer apply logic "0" to the input o~ in-verter 522. Thereupon the voltage at that input became logic "1", and the resulting logic "0" at the output of that inverter forward-biased both oE the diodes 52~ and 528. The ~orward-biasing of diode 524 will hold conduc-tor 463 at logic "0"! and the ~orward-biasing of diode 117.

3 ~8~

528 will hold conductor 324 at logic "0". This means that the Reverse Relay Latch Clrcuit 518 will hold logic "0" on both conductors 463 and 324 -- thereby keeping the relay contacts 470 and 472 in the "reverse"
position, and inhibiting or cancelling any validation signal -- until all of the switches 146, 156 and 162 re-open to permit logic "0" to re-appear at the output of NAND gate 334. In doing so, the Reverse Relay Latch Circuit 518 effectively latches the revexse relay coil 468 in energized position, and inhibits or cancels any validatio~ signal.
As the leadtng edge o~ the blll is moved out-wardl~ from under the actuator 164 of thc switch 162, that switch will re-open; and logic "1" will be applied to the lower input of NAND gate 334, to the cathode of diode 384, to the cathode o diode 432, to the input of inverter 446, to the cathode of diode 502, and to the middle input of NAND gate 504. The NAND gate 334 will not respond to that logic "1" because logic "0" s~ill appears at ~he middle and upper inputs thereof. The logic "1" at the cathode of diode 384 in Fig. 12 will back-bias that diode, and that back-biasing will initi-ate the time delay of the Vend Time Circuit 382; but the transistor 398 will not become conductive, because logic "0" appears on conductor 325, and thus at the collector of that transistor. The logic "1" at the 118.

B~
cathode of diode 432 can not have any effect at this time because the conductor 463 has logic "0" on it.
The application of logic "1" to the input of inverter 446 will forward-bias the diode 450, and thus will en-able the capacitor 452 to discharge via that diode and that inverter. The application of logic "1" to the cathode of diode 502 will back-bias that diode but that back-biasing can not have any effect at this time because the conductor 463 has logic "0" on it; and the logic "l"
at the middle input of NAND gate 506 will not be signi-ficant at this time because the conductor ~63 ha~ logic "0" on it.
~ s the belts 196 and 198 continue to mo~e the bill outwardl~ of the paper currency validator 30, the leading edge o~ that bill will move outwardly ~rom under the actuator 158 of the switch 156, thereby permitting a logic "l" to appear at the middle input of NAND gate 334, at the input o inverter 430, and at the cathode of di-ode 492. The NAND gate 344 will not be able to respond to that logic "1", because logic "0" still appears at the upper input thereof. The logic "1" at the input of inver-ter 430 will cause that inverter to forward-bias the di-odes 434 and 500, and the logic "1" at the cathode o diode 492 will back-bias that diode. The ~orward-biasing of diode 434 will keep the capacitor 440 discharged; but the forward-biasing of diode 500 and the back-biasing of 119.

diode 492 will not be signi~icant at this time because the conductor 463 has logic "0" on it.
When the leading edge of the bill is moved out-wardly from under the actuator 148 of switch 146, logic "1" will appear at the upper input of NAND gate 334, at the input of inverter 484, at the upper input of NAND
gate 498, and at the upper input of NAND gate 510. The logic "1" at the upper inputs of NAND gates 498 and 510 will not be significant at this time because the conductor 463 has logic "0" on it; and, similarly, the logic "1" at the input o~ inverter 484 will not be significant at this time because that conductor has logic "0" on it. EIow-ever, the NAND gate 334 will respond to the lo~ic "1" at all o~ the inputs thereof to appl~ logic "Oi' to the input o~ inverter 426, to the upper terminal of capacitor 408 in the Gross Time Delay Circuit 400, and to the cathode of diode 532 in Fig. 13. Inverter 426 will apply logic "1" to the lower input o NAND gate 358; but that NAND
gate will continue to apply logic "1" to the input of in~erter 360, because the logic "0" on conductor 325 will be applied to the upper input of that NAND gate. The logic "0" at the upper terminal of capacitor 408 in Fig.
12 will cause the transistors 402 and 404 to become non-conductive, and, thereupon, the transistor 406 will again become conductive, all as explained hereinbefore. The resulting logic "0" at the pin 13 o~ the voltage regula-tor 534 in Fig. 14 will de-energize the motor 562; and 120.

~3~
the diode 570 will dissipate the inductive energy in that motor. However, the shaft 182, the pulleys lg2 and 194, and the belts 196 and 198 will coact long enough to cause the lower runs of those belts to move the bill wholly outwardly of those belts. The logic "0" at the cathode of diode 532 will forward-bias that diode; and the inverter 522 will respond to the result-ing logic "0" at the input thereof to back-bias diodes 524 and 528. At this time, the outer edge of the bill will be projecting outwardly beyond the outer end of the platorm 32; and that bill can then be inverted and again introduced into the paper currency validator 30.
As the aapacitor 452 discharged, when the switch 162 re-opened, the voltage at the emitter of transistor 458 fell below the Zener voltage of that transistor; and hence transistor 462 became non-conduc-tive. ~owever, the inverter 522 of the Reverse Relay Latch Circuit 518 was forward-biasing the diode 524;
and hence that diode kept logic "0" on the conductor ( 463. This was desirable, because it enabled the inver-; ter 520 and the transistor 476 to keep the reverse re-lay coil 468 energized until the bill was moved wholly outwardly of the paper currenc~ ~alidator 30.
At the time the NAND gate 334 applied logic "0" to the cathode of diode 532 in Fig. 13 to forward-bias that diode, the diode 524 was the only component 121.

. ~3~

which was grounding the conductor 463. Consequently, when the forwara-biased diode 532 caused the inverter 522 to back-bias the diode 524, logic !'1" appeared on the conductor 463. The inverter 520 responded to that logic "1" to apply logic "0" to the cathode of diode 526 and to the base of transistor 476 -- thereby back-biasing that diode and rendering that transistor non-conductive. Thereupon, the relay coil 468 became de-energized, and the diode 474 dissipated the inductive energy within that relay coil. The consequent return o~ the relay contacts 470 and ~72 to the forward position of Fig. 1~ places the paper currency validator :ln it~
standby condition.
The inward movement of the bill was halted, and the outward movement of that bill was begun, while that bill was underlying all of the switch actuators 148, 158 and 16~. Consequently, there was no need for the outer edge of that bill to coact with the trailing edge of any of those switch actuators to raise that switch actuator. However, the trailing edges of those switch actuators have configurations and inclinations which enable the outer edge of an outwardly-moving bill to readily raise those switah aatuators.
The overall result o the insertion of a bill into the paper currency validator 30, while that bill is in inverted position, is the movement o that bill inwardly of that paper currency validator until approxi-mately two hundred and fifty to three hundred milli-seconds after the leading edge o~ that bill closes the switch 162. Th~reupon the motor 562 will start operat-ing in the reverse direction, and the bill will be backed out of that paper currency validator. Because the sub-circuit of Fig. 11 will not develop a validation signal, the NAND gate 358 in Fig. 12 will not be able to apply logic "0" to the input of inverter 360; and hence that inverter will not be able to cause the transistor 366 to become conductive to energize the vend relay 368.
Consequently, the vend relay contacts 372 will xemain open, and a vend signal will not be sent to khe vending machine.
If a person were to inadvertently insert a U.S.
two dollar bill, a U.S. five dollar bill, or an even higher denomination U.S. bill, the sub-circuit of Fig.
11 would not cause the NAND gates 312 and 314 to develop a logic "1" on the conductors 324 and 325. As a result, the paper currency validator 30 would permit the lead-ing edge of such a bill to close the switch 162 and tocontinue to move inwardly for approximately two hundred and fifty to three hundred milliseconds; but thereafter would reverse the motor 562 to cause it to back that bill out of that paper currency validator. Neither a valida-tion signal nor a vend signal. would be developed; and hence the vending machine would not be actuated.

123.

I~ a person were to insert just the upper half o~ a bill, and if that upper half were disposed in alignment with switch actuator 148 and magnetic head 210, that half bill would engage that switch ac-tuator and thereby e~fect closing of the switch 146.
The closing of that switch would cause the NAND gate 334 to develop a logic "1" at the output thereof; and the Gross Time Delay Circuit 400 would respond to that logic "1" to start the mokor 562 operating in the "for-ward" direction. As that half bill was moved inwardlyof the paper currency validator 30, it would not ener-gize the switch actuator 158 or the switch actuator 164, and it would no~ ~ngage the magnetic head 208. Elow~r, that half bill would engage the magnetic head 210; and the vertical grid lines in both the leading and trailing halves of the protrait background would engage the air gap of that magnetic head.
As the vertical grid lines in the leading half of the portrait background of the half bill were moved into engagement with the air gap of the magnetic head 210, that magnetic head developed signals which the Amplifier 270, the Squaring Circuit 278, the Frequency-Sensing Cir-cuit 292, and the Threshold Detector 308 responded to and applied logic "0" to the lower input of NAND gate 314.
However, because the Threshold Detector 294 was still applying logic "1" to the upper input of NAND gate 312, logic "0" continued to appear on the conductors 324 and 124.

~3~

325 and at the input of inverter 316. Similarly, when the vertical grid lines in the trailing half of the por-trait background of the half bill subsequently engaged the air gap of the magnetic head 210, that magnetic head developed signals which the Amplifier 270, the Syuaring Circuit 278, the Frequency Sensing Circuit 292, and the Threshold Detector 308 responded to and applied logic "0" to the lower input of NAND gate 314. However, be-cause the Threshold Detector 294 was still applying logic ~ to the upper input o NAND gate 312, logic "0"
continued to appear on the conductors 324 and 325 and at the input of inverter 316. Conse~uentl~, neither a validation signal nor a vend signal was develop~d.
Because the hal bill did nok engage the actu-ator 158 for the switch 156 or the actuator 164 for the switch 162, the output o NAND gate automatically changed back to logic "0" when the trailing edge of the bill was moved inwardly beyond the trailing edge 152 of the switch actuator 148. Consequently, the motor 562 came to rest;
and the half bill was not returned to the person who in-serted it. Instead, that half bill remained in position within the paper currency validator 30; and it will res-pond to the insertion o a further bill to move wholly inwardly of the paper currency validator 30 and into the cash box or other bill-receiving device.

125.

If a person were to insert just the lower half of a bill, and if that lower half were disposed in alignment with the switch actuators 158 and 164 and with the magnetic head 208, that half bill would engage the switch actuator 158 and thereby effect closing of the switch 156. The closing of that switch would cause the NAND gate 334 to develop a logic "1" at the output thereof; and the Gross Time Delay Circuit 400 would respond to that logic !'l" to start the motor 562 operat-ing in the "~orward" direction. As that half bill wasmoved inwardly o~ the paper currency validator 30, it would engage the switch aatuator 164 but wo~lld be un-able to engage khe switch Actuator 1~8. ~t the instant that half bill closes the switch 156, the conductor 336 : would apply logic "1" to the upper input of NAND gate 498; and the conductor 352 would be applying logic "1"
to the cathode of diode 502 while the inverter 430 would be applying logic "1" to the cathode of diode 500. Con-sequently, those diodes would be back-biased, and would thereby permit logic "1" to appear at the lower input of NAND gate 498; and that logic "1" would coact with the logic "1" at the upper input of that NAND gate to make the output of that NAND gate logic "0". Thereupon, logic "0" would appear on conductor 463 -- with consequent re-versal of the motor 562.
The positioning of the magnetic heads 208 and 210 so they will be in register with diagonally-displaced J~

~8~
quadrants of the portrait background of each inserted bill is desirable, because it will permit the accept-ance of an authentic U.S. one dollar bill which has the black-ink face thereof exposed to those magnetic heads -- whether the top of that portrait background engages the magnetic head 208 or the magnetic head 210.
In either case both magnetic heads will sense vertical grid lines at the same time, and thus will be able to ef~ect the development of a validation signal. In this way, the paper currency validator 30 avoids all need of precise orientation of the bill on the plat~orm 32.
If a person were, deliberatel~ or inadvertent-ly, to insert a second bill immediately a~ter the trail-ing edge of a first bill had been drawn into the paper currency validator 30, the switch 146 would be closed by the leading edge of the second bill while the trail-; ing edge of the first bill was still holding the switch 162 closed. At this time, the switches 146 and 162 would be closed but the switch 156 would be open. The resulting logic "0" on conductor 336 would enable theinverter 484 to apply logic "l" to the cathode of diode 490 and thereby back-bias that diode; and the resulting logic "0" on conductor 352 would enable the inverter 446 to apply logic "1" to the cathode of diode 494 and there-by back-bias that diode. The logic "1" on conductor 344 would be back-biasing the diode 492; and hence all o~

127, ~3~

diodes 490, 492 and 494 would be back-biased and would permit logic "1" to appear at the input of inverter 488. The resulting logic "O ll at the cathode of diode 530 would apply logic "O" to conductor 463; and, there-upon, the Reverse Relay Latch Circuit 518 would effect energization of the relay coil 468. The relay contacts 470 and 472 would then shit to their reverse positions, and the motor 562 would reverse direction and cause both of the bills to be backed outwardly of the paper currency 10 validator 30.. In addition, the Reverse Relay Latch Cir-cuit 518 would apply logic "O" to the cathode of diode 528 to orward-b:ias that diode; and the resu:Ltirlg logic "O" on conductor 324 would cancel the validation signal which was developed by the first-inserted bill. Conse-~uently, both bills will be moved outwardly of the paper currency validator 30, and the validation signal which was established by the first-inserted bill will be can-celled. In this way, that person will be kept from obtaining the change, product, or service from the vend-20 ing machine to which the paper currency validator isconnected.
In the event a person inserts a bill, which has a tape or other "tail" attached thereto that is in register with the actuator 148 of the switch 146 but is not in register with the actuator 158 of the switch 156, the krailin~ edge o:E that bill will successively move 128.

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out of engagement with the actuators 148 and 158, but the tape or other "tail" will remain in engagement with the actuator 148. As soon as the switch 15~ re-opens, the conductor 344 will apply logic "1" to the cathode of diode 492 and thereby back-bias that diode; and, because both of the switches 146 and 162 are held closed, the inverter 4~4 will be back-biasing the diode 490 and the inverter 446 will be back biasing the diode 494.
Consequently, logic "1" will develop at the input of inverter 488; and the rèsulting logic "O" at the cath-ode of diode 530 will forward~bias that diode, and there-by apply logic "O" to the conductor 463. Thereuporl, the motor 562 will reverse it~ direction of rotation, and the diode 528 will cancel any validation signal on con-ductors 324 and 325. In this way, the paper currency validator 30 will keep a person rom obtaining the change, product or service from the vending machine with which that paper currency validator is associated, and also will effect the return of the tail-equipped bill to that person.
If a person were to insert just a short length of a bill, or were to insert a short length of a piece of paper, that short length would initially close the switch 146 to start the motor 562; and then would close the switch 156. As the motor 562 continued to move that short length inwardly, the trailing edge o that 129~

v~
short length would move out of engagement with the ac-tuator 148 of the switch 146, and would thereby permit re opening of that switch. At such time, the conductor 336 would apply logic "1" to the upper input of NAND
gate 498; and the conductor 352 would be applying logic "1" to the cathode of diode 502 while the inverter 430 would be applying logic "1" to the cathode o~ diode 500.
Conse~uently, those diodes would be back-biased, and would thereby permit logic "1" to appear at the lower input of ~AND gate 498; and that logic "1" would coact with the logic lll" at the upper inpu~ o~ that NAND gate to make the output of that N~ND gate logic "0". ~here-upon logic "0" would appear on aonducto~ 462 -- with consequent reversal of the motor 562. This means that even i~ a person inserted the central portion of an authentic bill, the paper currency validator 30 would reverse the motor 562 and send that partial length of bill back to that person. As a result, that person would be unable to obtain change, product or services from the vending machine with which the paper currency validator 30 is associated.
If a person were to insert a bill which had a hole or opening therein in alignment wi-th the actuator 164 of the switch 162, that bill would be moved inward-ly of the paper currency validator 30 and would cause the sub-circuit of Fig. 11 to develop a validation 130.

~L~3~31~ i~31~
signal on the conductors 324 and 325. If that hole permitted the actuator 164 of the switch 162 to move downwardly to switch-opening position after the trail-ing edge of that bill had moved past the actuator 148 of switch 146 but while that trailing edge was holding the actuator 158 o switch 156 in closed-switch posi-tion, the diodes 500 and 502 would be back-biased to permit logic "1" to appear at the lower input of N~ND
gate 498 while logic "1" was being applied to the upper input of that NAND gate by the conductor 336. Conse-quently, at that time, that NAND gate would develop logic "0" on the conductor 463 -- with con9e~uent rev~rsal of the motor 562 and with cancellation o~ the validation signal on the conductors 324 and 325. The portion of the switch actuator 164 which extended downwardly through the hole in the bill would keep that bill from being returned to the person who inserted it; and, at the end of the time interval established by the Gross Time Delay Cir-cuit 400, the motor 562 will come to rest. Because the ~0 validation signal was cancelled, the paper currency val-idator would not be able to supply a vend signal to the vending machine.
If a person were to attach a tape or other "tail" to a bill and then attempt to pull that bill out-wardly of the paper currency validator 30 after the sub-circuit of Fig. 11 had developed a validation signal on the conductors 324 and 325, the leading edge of that bill 131~

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would be moved outwardly of the actuator 164 of the switch 162 while the switch 146 was held closed and while logic "1" appeared on the conductors 324 and 325.
At such time, the logic "0" on the conductor 336 would cause the inverter 484 to apply logic "1" to the upper input of the NAND gate 506, the logic "1" on the con-ductor 352 would appear at the middle input of that NAND
gate, and the logic "1" on conductor 324 would appear at the lower input of that NAND gate. Consequently, that NAND yate would apply logic "0" to the conductor 463 --with consequent reversal of the motor 562 and cancella-tion o~ the validation slgnal on the aonductors 32~ and 325. Hence, that bill and its tape or other "tail" would be backed out of the paper currenc~ validator 30, and that paper currency validator would not apply a vend signal to the vending machine.
The Bill Retrieval Circuit 504 would cause re-versal of the motor 562 and cancellation of the valida-tion signal whether the bill was underlying only the ac-tuator 164 of the switch 162, was underlying only the ac~
tuators 164 and 158 of the ~switches 162 and 156, or was underlying all of the actuators 148, 158 and 164 at the time that person started pulling the bill back out of the paper currency validator. As long as the switch 162 is permitted to re-open while a validation signal is present on the conductor 324 and the switch 146 is closed, the NAND gate 506 will apply logic "0" to the conductor 132.

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463 -- with consequent reversal of the motor 562 and cancellation of the validation signal.
If a person inserted an elongated object into the paper currency validator 30 and thereby raised the actuator 164 sufficiently to close the switch 162, the motor 562 would start rotating in the "reverse" direc-tion and logic "0" would be applied to the conductors 324 and 325. Specifically, as the switch 162 was closed, the resulting application of logic "0" to the lower input Of NAND gate 334 would cause that NAND gate to apply logic "1l' to the upper terminal o~ capacitor 408 in the Gross Time Delay Circui~ 400 and also -to the aathod~ oE diode 532 in Fig. 13. The logic "0" on conductor 352 would cause the inverter 446 to apply logic "1" to the middle input of NAND gate 510; and, because the inverter 316 was applying logic "1" to the lower input of that NAND
gate via conductor 326, and conductor 336 was applying logic "1ll to the upper input of that NAND gate, that NAND gate would apply logic 1l 01l to the conductor 463.
The logic "0" on the conductor 422 would be applied to the pin 13 o~ the voltage regulator 534 in Fiy. 14; and that voltage regulator would cause the transis-tor 554 to supply current to the motor 562, and the R~verse Re-lay Latch Circuit 518 would energize the reverse relay 468 and thereby cause that motor to start rotating in the reverse dixection. Also, the diode 528 would become 133.

~31~

forward-biased and would inhibit the development of a validation signal on the conductors 324 and 325.
If a person inserts a bill and then halts in-ward movement of that bill after that bill has closed the switch 146 but before that bill has closed the switch 156, the Gross Time Delay Circuit 400 will ener-giæe the motor 562 in the "orward" direction for the time interval of about six to twelve seconds, and then wi.ll de-energi2e that motor. In such event, that person will not be able to injure the paper currency validator 30, and will not be able to cause that paper currency validator t:o supply a vend signal to the vendlng mach-ine.
I~ a person insert~ a bill and then halts inward movement of that bill after that bill has closed the switches 146 and lS6 but before that bill has closed the switch 162, the Positional Time Delay Circuit 428 will cause the Time Delay Output Circuit 460 to apply logic "0" to the conductor 463. Thereupon, the motor 562 will reverse, and the diode 528 will inhibit the de-velopment of a validation signal on the conductors 324 and 325. In such event, the person will retrieve his bill but will not be able to cause the paper currency validakor 30 to supply a vend signal to the vending mach-ine.
If a person inserts a bill and then halts inward movement of that bill after that bill has closed the switches 146, 156 and 162 but before a validation ~34.

signal can be applied to the conductors 324 and 325, the Further Time Delay Circuit 444 will cause the Time Delay Output Circuit 460 to apply logic "0" to the conductor 463. Thereupon, the motor 562 will reverse, and the diode 528 will inhibit the development of a validation signal on the conductors 324 and 325. In such event, the person will retrieve his bill but will not be able to cause the paper currency validator 30 to supply a vend signal to the vending machine.
I~ a person inserts a bill and then halts in-ward movement of that bill after that bill has clo~ed the switches 146, 156 and 162 and a~ter A validat~on si~nal has been appliecl to the conductors 324 and 325, the Gross Time Dela~ Circuit 400 will keep the motor 562 energized in khe "orward" direction for the time interval of about six to twelve seconds, and then will de-energize that motor. In such event, that person will not be able to injure the paper currency validator 30, and will not be able to cause that paper currency validator to supply a vend signal to the vending mach-ine.
In some instances, persons have been known : to repeatedly pull out and re-insert the line cord of a paper currenay validator in an effort to attain an unauthorized operation of that paper currency valida-tor. In the paper currency validator 30, the parallel-connected resistor 514 and capacitor 516 of the Line-Cording Circuit 51~ maintain a volta~e of about twelve 135.

~3t3~

volts at the upper terminals thereof whenever logic "1"
is present on the conductor 463. If a person pulls out and re-inserts the line cord plug of the paper curr-ency validator 30, the volta~e at the upper terminals of resistor 514 and of capacitor 516 will decrease rapidly, in accordance with the exponential decay curve of that capacitor; and, in a matter of milliseconds, that voltage will decrease to the point where the in-verter 520 will coact with the transistor 476 to ener-gize the reverse relay coil 468. Thereupon, the mov-able relay contacts 470 and ~72 will shift into their reverse positions; and, lf any of the switches 1~6, 156 and 162 is closed, the diode 528 will inhibit or cancel any validation signal. Even if a person was able to re-insert the plug for lengths of time that were exactly e~ual to the lengths of time during which that plug was removed, the voltage at the upper ter-minals of resistor 514 and of capacitor 516 would decrease; because the initial portion of the exponential decay curve of a.capacitor is steeper than the initial portion of the exponential growth curve of that capaci-tor.
: If a person pulls out the line cord plug of the paper currency validator 30, waits a short length of time, and then re-inserts that plug, the voltage 136.

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across the capacitor 516 will not immediately rise to twelve volts. Instead, because the initial portion of the exponential growth curve of that capacitor is not steep, that voltage will remain low for a long enough period of time to apply logic "0" to the conduc-tor 463. Thereupon, the movable relay contacts 470 and 472 will shift to their reverse positions; and, if any of the switches 146, 156 and 162 is closed, the diode 528 will inhibit or cancel any validation signal on the conductors 324 and 325. In these ways, the Line-Cording Circuit 512 of paper currency validator 30 can keep any pulling and re-inserting of the line cord plucJ
from initiating an unauthorized opera~lon o~ that paper currency validator.
When the line cord plug is again solidly seat-ed within the receptacle therefor, and all of the switches 146, 156 and 162 are openl the voltage at the upper ter-minals of resistor 514 and of capacitor 516 will begin to rise; and logic "1" will again appear on the conduc-tor 463. At such time, the inverter 520 and the trans-istor 476 will be unable to keep the relay coil 468 en-ergized; and hence the movable relay contacts 470 and 472 will shift back into their "~orward" positions.
Also, the diode 528 will be back-biased; and the conduc-tors 324 and 325 will be capable of having logic "1"
app~ed thereto.
-~31-~3E~
If a person were to paste or tape the left-hand or right-hand hal~ of an authentic U.S. one dollar bill to a piece of paper which had the dimen-sions of that bill, and if that person inserted that piece o paper into the paper currency validator 30, the leading edge of that piece of paper would be moved inwardly and would suc~essively close the switches 146, 156 and 162. Also, the grid lines in the one-half o the portrait background of that bill would cause the Frequency-Sensing Circuit 280 or 294 to ren-der the transistor 298 or 299, respectively, conductlve.
However, because both o the magnetic heads 208 and 210 ; must be engaging vertiaal ~rid lin~s at the s~me time to enable both NAND gates 312 and 314 to develop logic "1", and because one half of a portrait background is too narrow to span the distance between the air gaps of those magnetic heads~ the half-bill can not cause those NAND gates to apply logic "1" to the conductors 324 and 325. Consequently, at the end of the time de-lay provided by the Further Time Delay Circuit 444, the capacitor 452 and the transistor 458 will render the transistor 462 conductive, and will enable the latter transistor to apply logic "0" to conductor 463 -- with consequent reversal of motor 562 and with consequent in-hibiting of the development o a validation signal on the conductors 324 and 325. In this way, the mountincJ
of the magnetic heads 208 and 210 of the paper currency validator 30 so they sense the vertical grid lines in 138.

diagonally-displaced quadrants of the portrait back-ground of a bill will keep a person from using the left-hand or right-hand half of a bill to effect an unauthorized operation oE that currency validator.
The paper currency validator 30 is shown equipped with just two maynetic heads 208 and 210;
but, if desired, that paper currency validator could be equipped with additional magnetic heads. Further, if desired, that paper currency validator could be e~uipped with other testing dev~ces. Any such addi-tional ma~netic heads and any such other testing de~
vices would have the val~dit~-ch0ckincJ ~ub-c~rcuits thereo~ connected to N~ND gates; and each oE those NAND gates would have one input thereof connected to conductor 319 and would have the output thereof con-nected to the conductor 324.
; The A.C. generator 560 constitutes an inex-pensive and rugged source of feedback for the Amplitude-Responsive Control Circuit 533 of Fig. 14. However, various other dynamic feedback sources, and various static feedback sources, could be used in lieu of the A.C. generator 560. All the Amplitude-Responsive Con-trol Circuit 533 oE Fig. 14 requires is a supply o~
Eeedback which varies the amplitude thereof in response to changes in the speed of the motor 562; and various Eeedback generators -- either dynamic or static in nature -- could be used to supply such feedback to that Amplitude-Responsive Control Circuit.

--/3~-3~
The paper currency validator 30 which is provided by the present invention is small, rugged and inexpensive, but it is accurate and stable in operation. Moreover, that paper currency validator is strongly resistant to efforts of persons to effect unauthorized operation thereof. If desired, the bill-actuated switches 146, 156 and 162 could be replaced by photoelectric switches or other suitable position-sensing switches.
Whereas the drawing and accompanying descrip-tion have shown and described a preferred embodimenk of the present invention, lt ~hould be apparen~ to those skilled in the art that various changes can be made in the form of that invention without affecting the scope thereof.

Claims (17)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A validator which comprises document-moving members that move a document inwardly of said validator, a sensing device that responds to the inward movement of an authentic document relative thereto by said document-moving members to develop a signal, position-sensing means that responds to a document and that senses when said document-moving members move a document inwardly to a predetermined position within said paper currency validator, a timing circuit that responds to the sensing by said position-sensing means of the inward movement of a document to initiate a time period of predetermined duration, and means to reverse the direction of movement of said document-moving members and thereby move said document outwardly of said validator if said sensing device does not develop said signal before the end of said time period.

2. A validator as claimed in claim 1 wherein said position-sensing means senses the inward movement of the leading edge of said document and wherein said sensing device senses a portion of said document which is located rearwardly of said leading edge of said document.

3. A validator as claimed in claim 1 wherein said timing circuit includes a capacitor which experiences a given change in the charge therein during said time period, and wherein an opposite change in said charge in said capacitor occurs, when said sensing device develops said signal to keep said means from reversing the direction of movement of said document-moving members.

4. A validator as claimed in claim 1 wherein said timing circuit includes a capacitor which exper-iences a given change in the charge therein during said time period, wherein an opposite change in said charge in said capacitor occurs, when said sensing device develops said signal, to keep said means from reversing the direction of movement of said document-moving members, wherein said means includes a control element with a threshold level, and wherein said means includes a Zener device that requires the voltage across said capacitor to exceed said threshold level of said control element by a fixed amount before said control element can be actuated.

5. A validator which comprises document-moving members that move a document inwardly of said validator, a sensing device that responds to the inward movement of an authentic document relative thereto by said document-moving members to develop a signal, position-sensing means that responds to a document and that senses when said document-moving members move a document inwardly to a predetermined position within said paper currency validator, a timing circuit that responds to the sensing by said position-sensing means of the inward movement of a document to initi-ate a time period of predetermined duration, and means to reverse the direction of movement of said document-moving members and thereby move said document outwardly of said validator if said sensing device does not develop said signal before the end of said time period, an output circuit, a switch that normally can initiate operation of said sensing device and thereby normally enable said output circuit to develop an output signal, and a circuit that responds to the development of the first said signal to effectively isolate said switch from said sensing device.

6. A validator as claimed in claim 5 wherein an electric motor can provide relative movement between said document and said sensing device, wherein said switch can normally initiate operation of said electric motor, and wherein said responsive circuit effectively isolates said switch from said electric motor whereby it effectively isolates said switch from said sensing device.

7. A validator which comprises document-moving members that move a document inwardly of said validator, a sensing device that responds to the inward movement of an authentic document relative thereto by said document-moving member to develop a signal, position-sensing means that responds to a document and that senses when said document-moving members move a document inwardly to a predetermined position within said paper currency validator, a timing circuit that responds to the sensing by said position-sensing means of the inward movement of a document to initi-ate a time period of predetermined duration, means to reverse the direction of movement of said document-moving members and thereby move said document out-wardly of said validator if said sensing device does not develop said signal before the end of said time period, said document-moving members being adapted to move said document inwardly beyond said sensing device, and further means to determine whether said document-moving members have moved said document inwardly beyond said sensing device, said reversing means reversing the direction of movement of said document-moving members if said further means determines that said document-moving members have not moved said document inwardly beyond said sensing device, said document-moving members providing gripping forces immediately outwardly of said sensing device to enable said document-gripping members to be in register with and to grip the trailing portion of a document which had the major portion of the length thereof wrinkled and crum-pled up against said sensing device while said docu-ment-moving members were moving said document toward said sensing device.

8. A validator as claimed in claim 7 wherein said further means includes a bill-actuated sensing member that senses the inward movement of the leading edge of said document.

9. A validator as claimed in claim 7 wherein said timing circuit will cause said reversing means to reverse the direction of movement of said document-moving members if said further means does not, within a pre-set length of time, determine that said document-moving members have moved said document inwardly beyond said sensing device.

10. A validator as claimed in claim 7 wherein said document-moving members are pulley-driven belts, and wherein at least one pulley for each belt is dis-posed immediately outwardly of said sensing device.

11. A validator as claimed in claim 7 wherein said sensing device must directly engage said document as it senses said document, and wherein the leading edge of said document must force its way between said sensing device and a pressure-applying element which is in register with said sensing device.

12. A validator which comprises document-moving members that move a document inwardly of said validator, a sensing device that responds to the inward movement of an authentic document relative thereto by said document-moving members to develop a signal, position-sensing means that responds to a document and that senses when said document-moving members move a document inwardly to a predetermined position within said paper currency validator, a timing circuit that responds to the sensing by said position-sensing means of the inward movement of a document to initi-ate a time period of predetermined duration, means to reverse the direction of movement of said document-moving members and thereby move said document outwardly of said validator if said sensing device does not develop said signal before the end of said time period, further position-sensing means that senses when said document is moved further inwardly to a second predetermined position within said paper currency validator, said sensing device being located inter-mediate the first said and said further position-sensing means and responding to the inward movement of an authentic document relative thereto by said document-moving members to develop a signal, said reversing means reversing the direction of movement of said document-moving members and thereby moving said document outwardly of said validator if said further position-sensing means does not sense the inward movement of said document before the end of said time period.

13. A validator which comprises document-moving members that move a document inwardly of said validator, a sensing device that responds to the inward movement of an authentic document relative thereto by said document-moving members to develop a signal having a given frequency, position-sensing means that responds to a document and that senses when said docu-ment-moving members move a document inwardly to a pre-determined position within said paper currency validator, a timing circuit that responds to the sensing by said position-sensing means of the inward movement of a document to initiate a time period of predetermined duration, means to reverse the direction of movement of said document-moving members and thereby move said document outwardly of said validator if said sensing device does not develop said signal before the end of said time period and a frequency-sensing circuit which has the essential elements thereof fixed in nature rather than adjustable in nature, whereby said frequency-sensing circuit has greater stability and is less ex-pensive than a comparable frequency-sensing circuit which has the essential elements thereof adjustable in nature, said essential elements of said frequency-sensing circuit helping establish and maintain a pre-determined center frequency for said frequency-sensing circuit, and a driving means for said document-moving members that has a speed-adjusting sub-circuit which permits the rate of said relative movement to be adjusted to cause said given frequency of said signal to be sufficiently close to said predetermined center frequency to enable said frequency-sensing circuit to respond to said signal.

14. A validator as claimed in claim 13 wherein said driving means includes an adjustable speed D.C.
motor and a feedback loop that keeps the adjusted speed of said D.C. motor substantially constant.

15. A validator as claimed in claim 13 wherein said driving means includes an adjustable speed D.C. motor and an amplitude-responsive control circuit which is part of a feedback loop that keeps the adjusted speed of said D.C. motor substantially constant, and wherein a feedback generator supplies feedback to said amplitude-responsive control circuit which has an amplitude that varies with the speed of said D.C.
motor.

16. A validator as claimed in claim 13 wherein said driving means includes an adjustable speed D.C.
motor and an amplitude-responsive control circuit which is part of a feedback loop that keeps the adjusted speed of said D.C. motor substantially constant, wherein a feedback generator supplies feedback to said ampli-tude-responsive control circuit which has an amplitude that varies with the speed of said D.C. motor, wherein said speed-adjusting sub-circuit includes an adjustable impedance to adjust the effective value of said feed-back, and wherein said speed-adjusting sub-circuit develops a reference and compares said effective value of said feedback with said reference to produce an error signal which is proportional to any variation between the actual speed and the desired speed of said D.C. motor.

17. A validator as claimed in claim 13 wherein one of said essential elements of said frequency-sensing circuit is a fixed value inductor, wherein another of said essential elements of said frequency-sensing circuit is a fixed value capacitor, and wherein said fixed value inductor and said fixed value capacitor are components of a tuned circuit.