CA1047166A - Paper currency validator - Google Patents

Abstract

PAPER CURRENCY VALIDATOR

Abstract of the Disclosure: Longitudinally-spaced and laterally-spaced sensors are used to sense part of the upper half and part of the lower half of each inserted bill -- to prevent acceptance of a sheet of paper bearing just the upper half or just the lower half of an authentic bill. One sensor engages and senses part of the leading half, and the other sensor engages and senses part of the trailing half, of each inserted bill -- to prevent acceptance of a sheet of paper bearing just the leading half or just the trailing half of an authentic bill. In addition, the longitudinal spacing enables those sensors to provide four signals which are spaced apart in time;
and thus makes it possible to use two sensors to provide four time-spaced signals. The two sensors of the paper currency validator are connected in series so one ampli-fier can receive and amplify the signals from both of those sensors. The sensors engage and sense the border on each inserted authentic bill before they engage and sense the longitudinally-spaced and laterally-spaced areas on that bill -- thereby making it possible to re-ject any bill which does not have a border.

Description

7~

Field of the Invention: The present invention relates to paper currency validators which are able to distinguish between authentic bills and spurious bills.
Description of the Prior Art: F-ishel et al Canadian Patent No. 1,011,458 for Paper Currency Validator, which was granted on May 31, 1977, discloses a paper currency validator which distinguishes between authentic bills and spurious bills. That paper currency validator performs a number of tests on each inserted bill; and the paper currency validator of the present invention performs improved versions of some of those tests and also performs some additional tests.
Summary of the Invention: The present : invention provides a paper currency validator which receives inserted bills and moves them past two sensors that are spaced apart both longitudinally and laterally of the path of those inserted bills. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part ~4~ 61~

of the lo~er half, of each inserted bill. Consequently, that lateral spacin~ makes it possible for the paper currency Yalidator to preYent the acceptance of a sheet of paper bearing just the upper half of an authentic bill, and also makes: it possible to preyent the acceptance of a sheet of paper bearing just the lower half of an authen-tic bill. The longitudinal spacing of the sensors enables one of those sensors to engage and sense part of the leading half, and enables t~e other cf those sensors to engage and sense part of the tralling half, of each inserted bill~ Consequently, that longitudinal spacing makes it possible for the paper currency ~alidator to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill, and also makes it possible to prevent the acceptance of a sheet o paper bearing just the trailing half of an authe~tic bill.
Furthermore, that longitudinal spacing enables the sensors to proYide four signals which are spaced apart i in time and which correspond to four longitudinally-spaced and laterally-spaced areas on an authentic bill.
In this way, the paper currency validator ls able to use two Sensors to provide four time-spaced signaLs from four longitudinally~spaced and laterally-spaced areas on an authentic bill. It is, therefore, an ob-ject of the present invention to provide a paper currenc~
validator ~hich utilizes two longitudinally~spaced and laterally-spaced sensors to proYide four time-spaced signals that correspond to four longitudinally-spaced -~ L6~;
and laterally~spaced areas.:on an insexted bill.
The t~o.sensors~ of the paper. currency ~alidator proyidea b~ the present inYention are .connected in serles.
The series connecting of those sensoxs, and the time-spacing of the:signals which corresp-ond to the four longitudinally-spaced ~nd laterally spaced areas on an authentic bill, make it possi~le for one amplifier to receiye and amplify thé si.gnals from both of those sensors~ The use of a single ampli~ier is des~rable because lt aYoids the cost of two amplifiers, and also hecause it a~oids problems w.hich could arise from the different responses ~hich two indiYidually-different amplifiers could make to signals ~rom -the two sensors.
It is, therefore, ~n object o~ the present in~ention to connect two sensors of a paper currency Yalidator in series relation and to cause those sensors to apply time-spaced signals to the same amplifier.
The paper currency validator of the present inYentlon uses phase locked loops as frequency detectors--2Q despite the fact that the oscillators of phased locked loops can, and do, ch~nge the frequencies of the signals generated thereby during normal operation of those phase locked loops, and despite the fact that the signals generated by the oscillators of phase locked loops can rando~ly he in phase with or displaced in phase from the signals applied to those phase locked loops.

~'7~6~i Specifically, phase locked loops have oscillators which establish center frequencies for those phase locked loops; and whenever the frequency of a signal, that is applied to the input of a phase locked loop, difers slightly ~rom the center frequency of that phase locked loop, the oscillator of that phase locked loop will change the frequency thereof to "track" the frequency of that applied signal. This mea~s that instead of having a fixed frequency, as do the fre~uency-sens-ing circuits of the said Fishel et al patent, a phased locked loop has a frequency which can, and does, change during the normal operation of that phase loc~ed loop. Also, the 9 ignal generated by the oscillator of a phase locked loop can be in phase with or displaced in phase from the signal applied to the input of that phase locked loop;
and whera the signal generated by the oscillator o~ a phase locked loop i9 displaced in phase from the signal applied to the input of that phase locked loop, that phase locked loop could sometimes re~uire 90 much tim~ to "track" and "lock up with"
that input signal that it might fail to respond to that input signal. Also, where the signal generated by the 09C illator of a phase loc~ed loop is displaced in phase from the signal 6.

~'7~
applied to the input o~ that phase locked loop, that phase locked loop can occasionally develop two output signals rather than just the desired output signal. As a result, the use of a phase locked loop as a ~requency detector ~or a paper currency validator does not, without more, . ,~.. ~i , ~ 6;~ o seem desirable. However, by equipping a phase locked loop with resistors and capacitors which narrowly limit the extent to which the frequency of t:he oscillator of that phase locked loop can change, ancl by providing circuitry which receives the signals from that phase locked loop and which will not responcl to a series of fewer than three or more than five signals from that phase locked loop, the present invention makes it possible to use a phase locked loop as a frequency de-tector for a paper currency validator. It is, -therefore, an ob j ect of the present invention to provide a paper currency validator with phase locked loops which have resistive and capacitive components that narrowly limit the extents to which the fre~uencies of the oscillators of those phase locked loops can shift, and also to apply the output signals of those phase locked loops to circuitry which can not respond to a series of fewer than three or more than five signals from either of those phase locked loops.
One of the phase locked loops responds to signals which are developed as an authentic U. S. one dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U. S.
five dollar bill is engaged and sensed by those sensors, As a result, the paper currency validator provided by the present invention can determine the validity of U.S. authentic one dollar bills and U. S. authentic five dollar bills.

~7~G
That paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such one dollar bills, to reject such five dollar bills, or to reject ,all such one dollar and five dollar bills. As a result, if the dispensing machine is able to dispense change for a one dollar bill but not for a five dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to prevent the acceptance of fu:rther five dollar bills while continuing to accept one dollar bills. On the other hand, if the dispensing machine is able to dispense change for a five dollar bill but not for a one dollar bill, the paper currency validator will respond to an appropriate signal from that ~ispensing machine to prevent the acceptance of further one dollar bills while continuing to accept five dollar bills.
If the dispensing machine is incapable of dispensing change for a one dollar bill as well as for a five dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to reject further one dollar bills as well as further five dollar bills. It is, therefore, an object of the present invention to provide a paper currency validator which can determine the validity of one dollar bills and five dollar bills and which can respond to signals from a dispensing machine with which it is associated to selec-tively reject further one dollar bills, to reject further five dollar bills, or to reject further one and five dollax bills.

~0~616 The sensors o~ the paper currency ~alidator providea by the present invention engage and sense the border on each inserted bill before they enga~e and sense the four longitudinally-spaced and laterally-spaced areas on that bill. The engaging and sensing of the border before the engaging and sensing of the laterally-spaced and longitudinally-spaced areas on the bill makes it possible for the paper currency validator to reject any bill which does not have a border. It is, therefore, an object of the present invention to provide a paper currency validator which checks the border on each inserted bill.
The paper currency validator re~uires a number of specifically-different events to occur within a corresponding number of specifically-diferent time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. In using timing circuits which include a binary counter and gates instead of using R.C.
networks, the paper currency validator attains more precise control over the lengths of those time periods;
because R.C. networks necessarily include components which can tend to "drift". Even resistive and capaci-tive components which have low temperature coefficients experience some changes as the temperatures thereof change; and hence even R.C. networks which utilize components with low temperature coefficients can not proYide the precise timing which is pro~ided by the binary counter and the gates of the present invention. ~oreover, the 47~;G
binary counter and ~ates of the present invention are less costly and occupy less space tha~ do the components of high quality R.C. networks. It is, therefore, an object of the present invention to pro~ide a paper currency validator with timing circuils which utili2e a binary counter and gates to provide a number of indiYidually-different time periods.
Brief Description of the Drawing: In the drawing, Fig. 1 is a vertical section through one perferred embodiment of bill transport that is made in accordance with the principles and teachings of the present invention, Fig. 2 is a diagrammatic view of a bill in position adjacent the magnetic heads of the bill transport of Fig. 1, Fig. 3A diagrammatically shows part of the circuit of the paper currency ~alidator of which the bill transport of Fig. 1 is a part, Fig. 3B diagrammatically shows another part of that circuit, Fig. 3C diagrammatically shows a f~rther part of that circuit, Fig. 4 is a detailed showing of the com-ponents in the BORDER sub-block of Fig. 3B, Fig. 5 is a detailed showing of the components in the SPEED ADJUSTING sub-block of Fig. 3A, Fig. 6 is a detailed showing of the components in the SPEED MAINTAINING sub-block of Fig. 3A, lQ.

~Q471~6 Fig. 7 is a detailed showing of the components in the OY~RL~VEL SENSING sub-block of Fig. 3A, Fig. 8 is a detailed showing of the components in the MOTOR AND RELAY sub-block and in the CURRENT
SENSING sub-block of Fig. 3A, ~ ig. 9 is a detailed showlng of the components in the upper of the FREQUENCY DETECTOR sub-blocks of Fig. 3C, Fig. 10 is a timing chart, and Fig. 11 shows an alternate threshold device for the BORDER sub-block of Fig. 3B.
Description oE Bill Transport: Referring to Fig. 1, the numeral 30 generally denotes one pre-ferred embodiment oE bill transport that is made in accordance with the principles and teachings of the present invention. The numeral 32 denotes a platform which extends outwardly from the front of the bill transport 30; and that platform will receive the leading edge of each bill which is to be tested by the paper currency validator of which that bill transport is a part. A flange 34 and a counterpart flange, not shown, of generally triangular configurations extend upwardly from the sides of the platform 32;and that platform has an upwardly-inclined inner end 38 which merges into a platen 40. An elongated flange 42 and a counterpart flange, not shown, extend downwardly from the elongated sides of the platen 40. The numeral 45 denotes the trailing edge of the platen 40; and that trailing edge inclines downwardly and then terminates in a 30` vertically-directed lip, as shown by Fig. 1.

The numeral 62 denotes a headed pin ~hich is secured to the flange 42 and which is adjacent the front of the bill transport 30. The numeral 65 denotes a short pi~ot which is secured to the flange 42 and which is spaced an appreciable distance to the right of the headed pin 62. The numeral 66 denotes a further headed pin which is supported by the flange ~2 and which is spaced to the right of the pivot 65.
The numeral 70 denotes a leaf-type spring which is bent so the right-hand end thereof, not shown, inclines upwardly to bear against the under surface of the platen 40. That spring is bent to have a downwardly-opening saddle, not shown, which rests upon the pi~ot 65, to have an elongated portion which inclines upwardly and to the left from that saddle, and to have a bifurcated left-hand end with fingers that define an upwardly-opening saddle. The numerals 72 and 74 denote springs which can be identical to the spring 70; but the bifurcated ends of those springs extend to the right rather than to the left in Fig. 1.
The downwardly-opening saddle of spring 72-rests upon the headed pin 62; and hence that spring is adjacent the front of the platen 40. The downwardly-opening saddle of the spring 74 rests upon the headed pin 66;
and hence that spring is adjacent the trailing edge of that platen.
A short pivot 80 is supported by the upwardly~
opening saddle which is defined by the fingers at the bifurcated end of the spring 72; and that pi~ot rotatably supports a roller 82. A similar pivot 84 is supported by the upwardly-~pening saddle.which is defined by the fingers at the bifurcated end of the spring 70; and that pivot rotatably supports a roller 86. A further similar piYot .88 is supported by the upwardly-opening saddle which is. defined by the fingers at the bifurcated end of the spring 74; and that pivot rotatably supports a roller 90.
The numeral 98 denotes an arm which has a hub that encircles the pivot 65. A pivot 100 is fixedly secured to the outer end of the arm 98; and that pivot ; rotatably supports a roller 102. A short pivot, not shown, which is the counterpart of pivot 65 is secured to the counterpart of ~lange 42 at a point to the left o pivot 65; and an arm, not shown, which is the coun-terpart o the arm 98 has the hub thereof encircling that short pivot. A pivot 112 is fixedly secured to the outer end of that arm; and that pivot rotatably supports a roller 114. Springs, not shown, encircle the short pivot 65 and its counterpart pivot; and those springs urge the rollers 102 and 114 upwardl~ relative to the platen ~0.
The numeral 118 denotes an upper platen which normally is disposed in parallel relation with, and in close proximity to, the platen 40. The platen 118 has a downwardly-directed flange 120 and a counterpart flange, not shown, at its elongated sides; and each of those flanges has a downwardly-opening slot 122 adjacent the front end thereof. The numeral 124 denotes a semi-cylindrical leading edge of the platen 118;

13.

~47~6~i and that semi-cylindrical leading edge is disposed ~oxwardly of the upwardly-inclined rear portion 38 of the platform 32. The platen 118 has an upwardly-inclined trailing edge 126, as shown by Fig. 1.
The numeral 140 denotes a co~er for the bill transport 30; and that cover has a down~ardly-directed flange 142 and a counterpart flange, not shown, at the elongated sides thereof. The numeral 144 denotes a switch bracket which is secured to the cover 140; and that switch bracket holds a normally-open, single-pole, single-throw switch 146 adjacent the front of the platen 118. The numeral 148 denotes a sturdy but thin actuator for the switch 146; and that actuator has a leading edge 150 and a trailing edge 152 which extend downwardly through slots, not shown, in the platens 118 and 140. The leading edge 150 is essentially straight, but the trailing edge 152 is convex. The configurations and inclinations of the leading ancl trailing edges 150 and 152, respectively, of actuator 148 enable the leading edge and trailing edge, re-spectively, of a bill to easily raise that actuator upwardly out of the slot in the platen 40. As a result, the switch actuator 148 permits relatively free movement of bills inwardly and outwardly of the bill transport 30.
The numeral 154 denotes a second switch bracket which is secured to the co~er 140; and that switch bracket supports a normally-open, single-pole, single-throw switch 156. The numeral 158 denotes a sturdy but thin actuator for the switch 156; ancl 14.

'7~1~6 that actuator has a convex leading edge'159 and a straight tralling,edge 161 which extends downwardly through slots, not shown, in the platens 118 and 140.
The configurations and inclinations of the leading and trailing edges 159 and 161, respectively, of the switch actuator 158 enable the leading edge cmd trailing edge, respectLvely, of a bill to easily raise that actuator upwardly out of the appropriate slot in the platen 40.
As a result, the swi-tch actuator 158 permits re~atively free movement of bills inwardly and outwardly of the bill transport 30.
The numeral 160 denotes a third switch bracket which is secured to the cover 140; and~that switch bracket is adjacent the rear of that cover. That switch bracket supports a normally-open, single-pole, single-throw switch 162; and that switch has an actuator 164 with a leading edge 166 and a trailing edge 168 which extends downwardly through slots, not shown, in -the platens 118 and 40. The leading edge 166 is essentially 20' straight; but the trailing edge 168 is generally convex and is quite short. That trailing edge normally is disposed an appreciable distance below the lower face of the platen 40. As a result, the trailing edge of a bill will not normally engage the edge 168 of the actuator 164 once that trailing edge has moved inwardly beyond that edge. If a person were to attempt to pull a bill outwardly o~ the bill transport 30, after the trailing edge of that bill had been moved inwardly beyond the edge 168 of actuator 164, the trailing edge o that ~L~473~6~i bill ~ould be intercepted by the inner surface of the leading edge 166 of that actuator. In that eYent, the actuator 164 would make it impossible for that person to recover that bill in intact form.
The numerals 188 and 1~0 denote pulleys which are mounted on short piYotSt not sho~n, that are supported by the flange 42; and the numeral 194 denotes a pulley which is mounted on an elongated shaft 182 that is ro-tatably supported by bushings which are mounted in the Oi flange 142 and in its-counterpart ~lange. The pulleys 188, l90 and 194 accommodate an elongated endless belt 198; and the lower "run" of that belt is engaged by the upper portions of the rollers 82, 86 and 90. A
worm wheel 200 is fixedly secured to the shaft 182, and a worm gear 202 meshes with that worm wheel. That worm gear is mounted on the output shaft 203 o~ a D.C.
motor 562 which is indicated diagrammatically in Fig.
8 and which is enclosed by a motor housing 204 shown in Fig. 1. That motor housing extends upwardly ~rom the cover 140; and it has its axis perpendicular to the central portion of that cover. The motor 562 is a reversible permanent magnet D.C. motor which drives an A.C. generator 560 by means of a connection 564. That A.C. generator is located within the motor housing 204;
and that connection is a direct mechanical connection.
In the said preferred embodiment of bill transport, the motor 562, the A.C. generator 560 and the connection 564 are parts of a type 16.

~473~

CYQ~ Motor ~ith.Integral Tachometer Generatox ~hich is marketed b.y. the~Barbe~ Colman Company as model No.
CYQM 23360-3. When the motor 562 is energized ln the "forward" direction, it will directly dri~e the A.C.
~enerator 560 in that direction, and lt will drive the lower "runs`' of the belt 198 and of its counterpart belt inwardly of the bill transport 30. ~hen that motor is energized in the "reverse" direction, it will directly drive the A~C~ generator 560 in that direction, and it will dri~e the lower "runs" oi' belt 198 and o~ its counterpart belt outw,ardly of that bill transport.
The numeral 206 denotes a mounting bracket which fixedly holds magnetic heads 208 and 210 in spaced-apart relation. Those magnetic heads are spaced both laterally and longitudinally of the elongated axis of the bill transport 30. As indicatea particularly by Fig. 2, which looks downwardly past those magnetic heads at an outline that generally represents the black-ink face of an authentic U.S. one dollar bill 20~. 212, the air gaps of those magnetic heads will sense two laterally-spaced, longitudinally-extending paths.

~ 17.

The numeral 220 denotes an elongated pi~ot which h~s the opposite en~s thereb~ secured to the rear portions of the flange 120 and of its counterpart flange, not shown, on the upper platen 118; and that pivot extends through aligned openlngs in the ~lange 42 and in the counterpart :flange, not shown, on the lower platen 40. As a result, the pl~ot 220 enables the upper platen 118 -- and the cover 140 plus the ~arious components which are mounted on that upper platen and on that coYer -- to ~e rotated up~araly and away from the lower platen 40. Such rotation is desirable; be-cause it permits ready and ree access to the space between the lower platen 40 and the upper platen 118.
However, the upper platen 118 will normally respond to its weight, to the 17A~

~7~6~
weighk of the cover 140, and to the weight o the components mounted on that upper platen and on that cover to urge the low~r face of the lower "run" of the belt 198 into inkimate engagement with the upper faces ~ the rollers 82, 86 and 90. The springs 70, 72 and 74 will yield slightly in response to the combined weights of the upper platen~8, of the cover 140, and of the components which are carried by that upper platen and by that cover; but those springs will hold the upper surfaces of the rollers 82, 86 and 90 above the upper surface of the lower platen.40. Those rollers and the rollers 102 and 114 are in register with openings, not shown, in that lower platen.
The bill transport 30 is essentially identical to the identically numbered bill trans-port in the said Fishel et al patent, except that the magnetic head 210 has been shifted closer to the leading edge of the platen 118~ and the arm 98 and its counterpart have been mounted on the short pivot 65 and its counterpart pivot instead of being mounted on the same elongated pivot. In the said preferred embodiment of bill transport, the air gaps of the magnetic heads 208 and 210 d~ine parallel lines which ~ 18.

~

716~i are transverse of the longitudinal axis of the platen 118 and which are spaced apart one-half of an inchO The inner faces of the magnetic heads 208 and 210 are spaced apart one-sixteenth of an inch transversely of the longitudinal axis of the platen 118. Consequently, whlen the ver-tical centerline of the upper part of the engraved portrait of George Washington on an authentic 18~o 1~7~6~

U.S. one dollar bill is in en~agement with the air gap of the magnetic head 208, the lower left-hand quadrant of the background for that portrait will be in engage-ment with the air gap of the magnetic head 210, as indicated by Fig. 2.
Description of the Circuit: Figs. 3A-3C, which diagrammatically show the circuit o the preferred embodiment of paper currency validator provided by the present inYention, include a number o-E blocks and 10` sub-blocks. The numeral 230 in Fig. 3A denotes a START
AND RUN LOGIC block which contains a three-input NAND
gate 232. Conductors 766, 776 and 780 extend from a SWITCH LOGIC block in Fig. 3B to the three inputs of the NAND gate 232. A branched conductor 234 is con-nected to the output of NAND gate 232; and one branch of that conductor extends to the input of an inverter 238 within a VEND ENABLE LOGIC block 236. The output of that inverter is connected to the upper input of a two-input NAND gate 240 and to a conductor 241.
In the drawing and accompanying description the switches 146, 156 and 162 are switches which have movable and stationary contacts and which have actuators which respond to the leading and trailing edges of bills to moYe those movable contacts. However, if desired, photoelectric cells and other bill-sensin~ devices could be substituted for the switches 146, 156 and 162.
Consequently, it will be recognized that the term "switch"
as used herein includes photo cells and other bill-sensing deYices.

~ 19.

~4c7~6~

A conducto~ 850 extends from a ~ALIDATING AND
VENDING ~OGIC block 784 in Fig. 3C to the lower input of NAND gate 240~ The other branch of conductor 234 extends to the lower input of a t~o-input NAND gate 328 within a MOTOR RE~ERSE LOGIC block 286. I~e conductor 241 extends to the cathode of a diode 245;
and the anode of that diode is connected to a source of regulated plus twelve volts D.C. by a resistor 247, to ground by a capacitor 249, and to the upper input of a NAND gate. A conductor 253 connects the output of that NAND gate to a SPEED MAINTAINING sub-block 358 withln a MOTOR CONTROLLING block 354.
A branched conductor 242 is connected to the output o NAND gate 240; and one branch of that con-ductor extends to the upper input of a two-input NAND
gate 246 within a TIMER

l9A.

block 244. A branch of conductor 766 extends to the lower input of NAND gate 246. The output of NA~D gate 246 is connected to the lower input of a two-input ~AMD gate 248, and a resistor 250 extends between the source of regulated plus twelve volts D C. and the upper input of that ~A~D gate.
The output of NA~D gate 248 is connected to the "reset" input of a BINARY COUNTER 254; and the output of a PULSE GE~ERATOR 252 is connected to the "count" input of that BI~ARY COU~TER. The input of the PULSE GE~ERATOR 252 is connected to a source of sixty Hertz signals. Although differ-ent pulse generators could be used, a Schmitt trigger has been found to be quite useful as the ; PU~SE GE~ERATOR 252; and it acts to steepen the leading edges and to flatten the tops of sine waves that are supplied to it by the source of sixty Hertz signals. Although different binary counters could be used, the RCA 4024 seven-stage binary counter has been found to be quite useful as the BINARY COUNTER 254 As used herein, RCA
is a trade designation of the Radio Corporation of AmericaO A conductor 256 extends from the binary four output terminal of the BI~ARY COU~TER
254 to the upper input of a three~input ~A~D

.i ~''' ~0147~i6 gate 2 72 in a TIMER LOGIC block 262. A branched conductor 258 extends from the binary eight output terminal of the BI~ARY COUP~TER 254 to the lower input oP a two-input NAND gate 266, to the upper input of a three-input ~A~D gate 268, and to the middla input of the three-input ~AND gate 2 72.
A branched conductor 260 extends from the binary thirty-two output terminal of the BI~ARY COU~TER
254 to the middle input of NAMD gate 268,

2 OA .

47~L66 to the uppex input of a two-input NAND gate 270, and to the lower input of NAND gate 272. A branch of con-ductor 780 is connected to the lo~er input of NAND
gate 270. A conductor 852 ex~ends fr~m the VALIDATING
AND VENDING LOGIC block 784 in Eig. 3C to the lower input of NAND gate. 268.
Another branch of conductor 242 extends to the input of an inverter 264 in the TIMER LOGIC block 262; and the output of that inverter is connected to the upper input of the NAND gate 266. A further branch of the conductor 242 extends to the lower input of NAND gate 251; and a still further branch of that conductor extends to the input of an inverter 762 in the SWITCH hOGIC block 738 in Fig. 3B. The remainlny branch of conductor 242 extends to the lower inputs of NOR gates 838 and 840.,in the VALIDATING AND VENDING
hOGIC block 784 in Fig. 3C.
A conductor 278 extends from the output of MAND gate 266 to the second-uppermost inputs of four-20. input NAND gates 728 and 730 in an INHIBIT LOGIC block 718 in Fig. 3B. A conductor 280 extends from the out-put of NAND gate 268 to the upper input of a four-input NAND gate 326 in the MOTOR REVERSE LOGIC block 286. A conductor 282 extends from the output of NAND
gate 270 to the second uppermost input of NAND gate 326. An inverter 274 has the input thereof connected to the output of NAND gate 272, and it has the output thereof connected to the anode of a diode 2760 A
conductor 284 connects the cathode of diode 276 to the upper input of a three-inpu-t NOR gate 295 in the MOTOR
REVERSE hOGIC block 286.

21.

7~
The numerals 288, 290, and 294 denote further three-input NOR gates within the MOTOR REVERSE LOGIC
block 286; and ~ranches of conductor 776 extend to the upper inputs of NOR gates 288 and 292. Branches of conductor 780 extend to the middle input of NOR gate 290 and to the lower input of NOR gate 292. A branch of conductor 766 extends to the middl~e input of NOR
gate 294. A conductor 76~4 extends from the SWITCH
LOGIC block 738 to the upper inputs of NOR gates 290 and 294. A conductor 778 extends from that SWITCH
LOGIC block to the middle input of NOR gate 29 2 and to the lower input of an OVERLEVEL SENSING sub-~block 296. A branch of conductor 852 is~ connected to -the lower input of NOR gate 28 8; and a conductor 768 ex-tends from SWITCH LOGIC block 738 to the middle input of that NOR gate and to the lower input of NOR gate 294. A conductor 791 extends from the YALIDATING AND
VENDING LOGIC block 784 to the upper input of the OVERLEVEL SENSING sub-block 29 6 . A diode 29 8 has the anode thereof connected to the output of NAND gate 288, and has the cathode thereof connected to the upper input terminal of NOR gate 295 by the conductor 284.
Similarly, a diode 300 has the anode thereof connected to the output of NAND gate 290, and has the cathode there~f connected to the upper input of NOR gate 29 5 by the conductor 2 84 . A conductor 29 7 and the conductor 284 connect the output of the ovERL:ævEL SBNSING sub-block 296 to the upper input of NOR gate 295~ The output of NOR gate 292 is directly connected 22.

~0~7~6 to the middle input of NOR gate 295; and the output of NOR ~ate 294 is directly connected to the lower input of that NO;R .gate.
The numeral 302 denotes an NPN transistor in the ~OTOR ~E~IERSE LOGIC block 286; and a resistor 312 connects the `connector of that transistor to the source of regulated plus twe1ve volts D.C. The emitter of that transistor is grounded; and the base of that transistor is connected tOthe junction of resistors 306 and 3~8 which coact with a thirteen Yolt Zener diode 304 to constitute a voltage diYider between ground and a source of non-regulated plus twenty-four ~7olts D.C.
A capacitor 329 is connected between ground and the collector of transistor 302~ and a resistor 310 is connected between ground and the conductor 284, and thus is. connected between ground and the upper input of NOR gate 295.
An inverter 314 has the input thereof connected to the collector of transistor 302, and has the output thereof connected to the cathode of a diode 318; and a conductor 316 extends from that cathode to the upper-most inputs of the NAND gates 728~and 730 in the IN-HIBIT LOGIC block 718. The output of NOR gate 295 is directly connected to thè cathode of a diode 320;
and the anodes of diodes 318 and 320 are connected together and to the second lowermost input of NAND
gate 326 by a conductor 324. A resistor 322 connects the conductor 324 to the source of regulated plus twelYe Yolts D.C.

~ 23.

~47~66 The output ~f the NAND gate 326 is connected to the input of a RELAY DRIYER 330, and also to the upper input of NAND gate 328. Although different relay driYers could be used, G~
a simple transistor stage which responds to a "O" at the .input th-ereof to pro~ide a "1" at the output there-of and which`responds to a "1" at the input thereof to provide a "O" at the output thereof is qui.te usable.
A conductor 332 extends from the output o relay driver 330 to a MOTOR AND RELAY sub-block 360 within the MOTOR CONTROLLING block 354. The output of NAND gate 328 is directly connected to the lower input of NAND
gate 326 and, by a conductor 334, to the second-lower-most inputs of NAND gates 728 and 730 in the I~HIBIT
LOGIC block 718.
As shown particularly by Fig. 7, the OVER-LEVEL SENSING sub-block 296 has a resistor 336 which connects the conductor 791 to the base o an NPN
transistor 338. The emitter of that transistor is connected to the junction of resistors 350 and 352 which constitute a voltage divider that is connected between ground and the source o regulated plus twelve volts D.C. A diode 340 has the anode thereof connected to the conductor 778; and has the cathode thereof directly connected to the emitter of a PNP transistor 346 and, by series-connected resistors 342 and 344, to the collector of transistor 338. The junction between the resistors 342 and 344 is connected to the base of transistor 346~ A resistor 348 is connected between the collector of transistor 346 and ground; and that collector also is connected to conductor 297.
Conductors 368 and 370 extend from the MOTOR
AND RELAY sub-block 360 to a SPEED ADJUSTING sub-block 356. As shown particularly by Fig. 5, the latter sub-block includes a full wave 24.

~7~

diode bridge 376; and conductor 368 is connected to one of the A~C. termin~ls of that bridge, and the conductor 370 ls connected to-the other of those A.C. terminalsO
One of the D.C~ termlnals of that bridge is grounded,, and the other of those DoC~ terminals is connected to the base of an NPN transistor 378 by a resistor 380.
resistor 382 ls connected bet~een groun~ and the base of that transistor; and the emitter of that transistor is grounded. The collector of that transistor is con-nected to the source of regulated plus twel~e volts D.C.
by a resistor 384.
A capacitor 386 is connected between the col-lector of transistor 378 and terminal 2 of a MONOSTABLE
MU~TIVIBRATOR 392. Although different monostable multi-vibrators could be used, the NE 555V monostable multi-vibrator made by the Signetics Corporation has been found to be Yery useful. A diode 388 has the anode thereof connected to the right-hand terminal of capacitor 386, and has the cathode thereof connected to the regu-lated source of plus twelve volts D.C.; and a resistor 390 is connected in parallel with that diode. Terminal 1 of the monostable'multivihrator 392 is directedly connected to ground, terminal 8 is directly connected to the regulated source of plus twelve volts D.C., and : terminals 6 and 7 are connected together and to a junction between a resistor 398 and a capacitor 396 which are connected between ground and that regulated sour~ce of plus twel~e Yolts D.C. Terminal 5 of that monostable multivibrator is connected to ground~
by a capacitor 394; and terminal 4 is 25.

~047~
connected to ground by a capacitor 410. The latter terminal ~lso ~s connacted to the regulated source of plus twelve volts D.C. and to the-upper terminal of a resistor 400. That resistor and a resistor 402 are ~onnected in series between groun~L and the regulated source o plus twel~e Yolts D.C. Ter~linal. 3 of the mono-stable multivibrator 392 is connected to the base of an NPN .transistor 414 by a resistor 412. The emitter of that transistor is directly connected to ground, and the collector of that transistor is connected to the junction between resistors 400 and 402. A resistor 404, a potentiometer 408 and a reslstor 406 constitute a ~oltage aivider which is connected between grou:nd and the regulated source of plus twelve volts D.C.; and the moYable contact of that potentiometer is connected to thé in~erting terminal of an amplifier 420, Although different amplifiers could be used, an MC 1741 Motorola amplifier has been found to be very useful~ A resistor 416 is connected between the co~lector of transistor 20. 414 and the non-in~erting input of ~mplifier 420i and a capacitor 418 is connected between that non-inverting input and ground. One of the terminals of the amplifier 420 is directly connected to ground; and another of those terminals is directly connected to an unregulated source of plus twenty-four volts D.C., and is connected to ground by a capacitor 422. A capacitor 424 is connected between the output and the inverting terminal of the amplifier 420; and a series-connected capacitor 426 and resistor 428 also are connected bet~een that output and that inverting terminaL.

~L~47~
A Zener diode 430, a resistor 432, and a con duator 364 connect the output of ampliier 420 to the collector o~ an NPN translstor 466, t~ the anode of a diode 470, and to the base of an NPN transistor 468 which are in the S~EED MAINTAINING sub~block 358 -- as shown by Fig. 6. The emitter of trans~stor 466 is directl~ connected to ground, the cathode of diode 470 is connected to ground by a resistor 472, and the e~itter of transistor 468 is connected to ground by a resistor 479. A two-input NAND gate 434 has those inputs connected together to enable that NAND gate to act as an inverter; and those inputs are connected to the conductor 253. The output of that NAND gate is connected to the base of an NPN transistor 438 by a resistor 436. The emitter of that transi.stor is directly grounded, and the collector of that transistor is connected. to the cathodes of diodes 442 and 444.
A resistor 440 connect~ the anode of diode 442 to the regulated source of plus twelve volts D. C .; and the anode of diode 444 is directly connected to the.upper inputs of two-input NAND gates 448 and 450, and is con-nected ko the regulated source of plus twelve volts D. C.
by a resistor 446. A resistor 452 and a capacitor 454 constitute a series RC circuit which is connected between ground and the regulated source of plus twelve volts D.C.; and the junction between that resistor and that capacitor is connected to the lower input of NAND gate 448. A diode 456 has the anode thereof connected to the output of NAND gate 448; and it has 27.

. -~L04~7~66 the cathode thereof connected to the lowex input ofNAND gate 450 by a resistor 462. A capacitor 458 and a resistox 460 constitute a parallel~connected RC circuit which is connected between ground and the cathode of diode 456. The output of NAND gate 450 is connected to the base of transistor 466 by a resistor 464. A resistor 478 connects the collector o~ transistor 468 to the cathode of a diode 476 and to the base o~ a PNP transistor 480. A resistor 474 connects the anode of diode 476 to the regulated source of plus twenty-four volts D.C.; and a resistor 484 connects the emitter of transistor 480 to that regulated source. Resistors 486 and 488 connect the collector of transistor 480 to a conductor 366 which extends to the MOTOR AND RELAY sub-block 360 of Fig. 8. The junction between those resistors is connected to the base of an NPN transistor 482; and the collector of that transistor is connected directly to the regulated source of plus twenty-four volts D.C., and the emitter of that transistor is directly connected to the conductor 366.
As shown particularly by Fig. 8, the conductor 366 is connected to a movable relay contact 492, to the cathode of a diode 496 and ~o one terminal of a capacitor 498. The anode of diode ~96, the other terminal of capacitor 498, and a movable relay contact 494 are connected together and to a conductor 372 which extends to a CURRENT SENSING sub-block 362. The "forward" stationary relay contact 492 is connected to the upper ~7~66 terminal o~ mo~o~ 562, and the ~reverse~ stationary rela~ contact 492 is connected to the lowe~ tenminal of that ~otox. The "for~axd~' stationary xelay con-tact 494 is connected to the lower terminal o~ motor 562 r and the "re~erse~' stationary relay contact 494 is connected to the uppex terminal of that motor.
The coil which controls the movable relay contacts 492 and 494 is denoted b~ ~he numeral 490; and one terminal of that coil is connected to the regula-ted source of plus twenty-four volts D.C., while the other terminal of that coil is connected to the conductor 332. One terminal of the A.C. generator 560 is connected to thel~conductor 370, while the other terminal o~ that A.C. generator is connected to the conductox 368.
The conductor 372 is connected to the base of an NPN transistor 500 by series-connected resistors 504 and 508. A resistor 502 is connected between ground and the junction between conductor 372 and resistor 504; and a resistor 506 is connected between ground and the junction between resistors 504 and 5G8.
The emitter of transistor 500 is grounded; and the collector of that transistor is directly connected to the input of an inverter 512, and is connected to the regulated source of plus twelve volts D.C.
by a resistor 510.
The output of the inverter 512 is connected to a conductor 374 which e~tends to the uppermost input of a four-input NOR gate 518 in a COUNT ENABLE
block 514. One branch of 29.

.

~7~ii6 conductor 776 is connected to the second lowermost input o~ th~t ~OR ~ate, and one bxanch o~ conductor 780 is connected to the lo~er~ost input OS that NOR
gate. A branch o~ conductor 778 is connected to the lowex input o~ a l'BO~DE~I' sub-block 516, and a branch of conductor 791 is connected to the upper input o~ that sub-block. The output of that sub-block is connected to the second uppe:nmost input of ~OR gate 518 by a conductor 517. The output of that NO~ gate is connected to the input of an inverter 520; and the output o~ that in~erter is connected to the lower input of two-input NOR gates 800 and 802 in the VALIDATI~G AND VE~DING LOGIC block 78 by a conductor 522.
~s shown particularly in Fig. 4 the BORDER
sub-block 516 ~as a resistor 684 which connects the conductor 791 to the base of an NPN transistor 682.
Resistors 688 and 690 constitute a voltage divider connected between ground and the regulated source of plus twelve volts D.C., and the junction between those resistors is connected to the emitter of transistor 682.
A resistor 686 connects the collector of that tran-sistor to the regulated source of plus twelve volts D.C. A resistor 692 connects the collector of transistor 682 to the upper inputs of two-input MAND
gates 696 and 700. A capacitor 694 is connected between ground and the junction between resistor 692 and those upper inputs; and that capacitox will by-~ass to ground any high frequency pulses, on conductor 791, such as transients and motor noise.

~ 30.

7~6~

The output o~ NAND gate 696 is:connected to the lowex input of NA~D ~ate 700 and also- tQ the up~ex input o~ a t~o-input NAND ~ate 698. The 30A.

7~

lower input o~ NA~D gate 698 is connected to a branch of conductor 778. The output of NAND gate 698 is connected to the lower inpuk of NAND gate 696, and also to the lower input o~ a two-input NOR gate 708.
The anode of a diode 702 is connected to the output of NAND gate 700; and the cathode of that diode is connected to the interconnected inputs o a two-input NOR gate 704 which serves as an inverter. A resistor 710 and a capacitor 712 constitute a parallel-connected R.C. network connected between ground and the inter- `
connected inputs of NOR gate 704. The output of NOR gate 704 is connected to the cathode of a diode 713; and the anode o~ that diode is connected to the upper input of a two-input NOR gate 706.
resistor 714 and a capacitor 716 constitute a series-connected R.C. circuit connected between ground and the souxce o~ regulated plus twelve volts D.C.; and the junction between that resistor and that capacitor is connected to the anode of diode 713, and to the 20:~ upper input of NOR gate 706. The output of NOR gate 708 is connected to the lower input of NOR gate 706;
and the output of NOR gate 706 is connected to the upper input of NOR gate 708 and also to the conductor 517.
; The numeral 524 denotes a COUPLING block in Fig. 3B; and that block has terminals 526, 528 and 530 which are connectable to a dispensing machine such as a ch~nye-making machine. In one preferred embodiment o~ the present invention, the terminal 526 is connected to a circuit of a dispensing 7~6~

machine which can selectively indicate khat dollar bills should not be accepted, and the terminal 530 is connected to a ci~cuit in that dispensing machine ~hich can selectivel~ indicate that ~ive dollar bills should not be accepted. The terminal 528 is connected to a common conductor from that dispensing machine. A resistor 532 is connected between the terminal 526 and the anode of a diode 536; and a resistor 534 is connected between the terminal 530 and the anode o~ a diode 538. The cathodes of the diodes 536 and 538 are connected together and to the common terminal 528. An opto ooupler 540 is connected in parallel with the diode 536, and an opto-coupler 542 is connected in parallel with the diode 538. The emitters of the light-sensitive elements in those opto-couplers are connected together and to ground. The collector of the light-sensitive element in opto-coupler 540 is directly connected to the cathode of a diode 5~8, and is connected to the source of regulated plus twelve volts D.C. by a re-sistor 544. The collector of the light sensitive element in the opto-coupler 542 is directly connected to the cathode of a diode 550, and is connec~ed to the source of re~ulated plus twelve volts D.C. by a re-sistor 546. A resistor 552-~and a capacitor 556 are connected in series between the source of regulated plus twelve volts D.C. and ~round; and the junction between that resistor and that capacitor is connected to the anode of diode 548, and also to a conductor 566 which e~tends 1047~6 to the IN~IBIT LOGIC block 718. A resistor 554 and a capacitox 558 are connected in series between the source o~ regulated twelve ~olts D.C. and ground; and the junction between that resistor and capacitor is connected to the anode of diode 550 and to a conductor 568 which extends to that IN~IBIT LOGIC block.
The conductor 566 is connected to the upper input of a two-input NAND gate 720 and also to the input of an inverter 724. The conductor 568 is connected to the lower input of NAND gate 720, and also to the input of an inverter 726. The output o~ NAND gate 720 is connected to the input of an inverter 722; and the output o~ that inverter is connected to a conductQr 732 which extends to the S~ITCH LOGIC block 738. The output oE inverter 724 is connected to the lowermost input of NAND gate 728;
and the output of inverter 726 is connected to the lowermost input of NAND gate 730. The output of NAND gate 728 is connected to a conductor 736 which extends to the VAhIDATING AND VENDING hOGIC block 784; and the output of NAND gate 730 is connected to a conductor 734 which also extends to that block.
The movable CQntaCtS of the switches 146, 156 and 162 are connected together and to ground, as shown by Fig.3B. A resistor 740 connects the stationary contact of switch 146 to the source of regulated plus twelve volts D.C.; and a resistor 746 connects that stationary contact to the lower input of a 33.

three-input NOR ~ate 758. ~ capacitox 752 is connected between ~round and the junction between resistor 746 and that lo~er input. A resistor 742 connects the stationar~ contact of switch 156 to the source of regulated plus twelve volts D.C.; and a resistox 748 connects that st~tiona:ry contact to the conductor 766 and also to the input of an inverter 772. The output of that inverter is connected to the conductor 778. A capacitor 754 is connected between ground and the junction of resistor 748, conductor 766, and the input of in~erter 772. A
xesistor 744 connects the stationary contact of switch 162 to the source of regulated plus twelve volts D.C.; and a resistor 750 connects that stationary contact to the lower input of a two-input NOR gate 760. A capacitor 756 is connected between ground and the junction between resistor 750 and that lower : input. The inverter 762 has the output thereof connected to the upper input terminals of NOR gates 758 and 760; and the middle input terminal of NOR
gate 758 is connected to the conductor 732. The output of NOR gate 758 is connected to conductor 76 and to the input of an inverter 770; and the output of that inverter is connected to conductor 776. The output of NOR gate 760 is connected to conductor 768 and to the input of an inverter 774; and the output of that inYerter is connected to conductor 780.
: ~ constant current diode 786 in Fig. 3C
connects one 34.

1~7~6~ii te~minal of the m~gnetic head 208 to the source of regulated plus twelve volts D~C, Although diffexenk constant cuxrent diodes could be used, a lN5297 constant current diode has been found to be very useful. The other terminal of magnetic head 208 is connected to one terminal of magnetic head 210;
and the other terminal of the latter magnetic head is connected to ground by a resistor 788. An amplifier 790 has one input terminal thereof connected to the junction between the cathode of constant current diode 786 and the upper terminal of magnetic head 208, and has the other terminal thereof connected to the junction between resistor 788 and the lower terminal o~ magnetic head 210. The output of amplifier 790 is connected to conductor 791. One branch of that conductor is connected to the input of a FREQUENCY DETECTOR sub-block 792, and another branch of that conductor is connected to the input of a FREQUENCY DETECTOR sub-block 794~ As shown particularly by Fig. 9, the FREQUENCY DETECTOR sub-block 7~2 includes a phase locked loop 854. One very useful phase locked loop is the NE567V phase locked loop of the Signetics Corporation. A resistor 856 and a capacitor 862 connect the conductor 791 to terminal 3 of the phase locked loop 854. Oppositely-polarized diodes 858 and 860 are connected between ground and the junction between resistor 856 and capacitor 862.
A potentiometer 878 has one terminal thereof connected to pin 5 of the phase locked loop 854 and has-the other terminal thereof 35.

716~i connected to pin 6 o~ that phase locked loop by a fixed resistor 880. The movable contact o~ that potentiomete~ is connected to the junction between that potentiometer and tha~ resistor to enable that potentiometer to serve as an adjustab].e resistor.
A capacitor 882 is connected between ground and the junction between resistor 880 and pin 6 of the phase locked loop 854. A conductor 876 directly connects pin 7 of that phase locked loop to ground; and a conductor 864 connects pin 4 of that phase locked loop to a source of regulated plus six volts D.C.
A capacitor 866 connects pin 2 of that phase locked loop to ground; and a conductor 795 is connected to pin 8 of that phase locked loop. A resistor 867 and a conductor 868 connect pin 1 of the phase locked loop to the source of regulated plus six volts D.C.; and a capacitor 870 connects that pin to ground. A resistor 872 and a capacitor 874 connect pin 1 to pin 8 of that phase locked loop.
The FREQUENCY DETECTOR 794 is identical to the FREQUENCY DETECTOR 792 in all respects other than the value of the resistor 880. Thus, in the said preferred embodiment of the present invention, each of the FREQUENCY DETECTOR sub-blocks 792 and 794 has a twenty-two hundred ohm resistor 856, has lN914 diodes 858 and 860, has a one-tenth micro-farad capacitor 862, has a twenty-two hundredths of a microfarad capacitor 866, has a ten thousand ohm potentiometer 878, has a sixty-eight thousandths of a microfarad capacitor 882, has 36.

47~6 a two and two-tenths microfarad capacitor 870, has a one hundred thousand ohm resistor 867, has a one hundred ohm reSistor 872, and has a t~enty-two hun-dredths of a microfarad capacitor 874. The ER~QUENCY
D~TECTOR sub-block 792 differs from t~e FREQU~NC~
D~TECTOR sub-block 794 in havin~ a seventy-five ~undred ohm resistor 880, whereas the latter FREQUENC~
~TECTOR sub-block h~s a fourteen thousand seven hundred ohm resistor 880.
The conductor 795, which is connected to the output of FREQUENCY DETECTOR sub-block 792, is connected to the upper input of NOR gate 800; and a conductor 797, which is connected to the output of FREQU~NCY DETECTOR sub-block 794, is connected to the upper input of NO~ gate 802. A resistor 796 extends between conductor 795 and the source of regulated plus twelve volts D.C.; and a resistor 798 e~tends between the conductor 797 and that regulated source. The output of NOR gate 800 is con-nected to the l'clock" input of a counter 804. While different counters could be used, an RCA 4015 Shift Register has been found to be ver~ useful. The output of NOR gate 802 is connected to the "clock" input of a similar counter 806.
A stationary switch contact 812 and a stationary switch contact 818 are connected together and to the fourth output terminal of counter 804.
Stationary switch contacts 814 and 816 are connected, respecti~ely, to the second and third output ~erminals of that counter. A mo~able switch contact 808 37.

~L0~7~66 and a movable switch contact 81~ are l'ganged" to.g.ether;
and those ~ovable switch contacts coact with the stationar~ switch contacts 812,.814, 816 and 818 to constitute a two-pole, double-thxow switch. In the position shown by ~ig. 3C, mo~ab.le contact 808 is in engagement with stationary contact 814:-and movable contact 810 is in engagement with stationary contact 818. The movable contact 808 is connected to the upper input o~ a two-input NAND gate 834; and a conductor connects the third output *erminal of counter 804 to the lower input of that NAND gate.
The movable contact 810 is connected to the input of an inverter 819; and the output of that inverter is connected to the "data" input of the counter 804.
The conductor 736 is connected to the "reset" terminal of the counter 804.
A stationary swi*ch contact 824,and a stationary switch contact 830 are connected to~ether and to the fourth output terminal of counter 806.
Stationary switch contacts 826 and 828 are connected, respectively, to the second and third outpu~ terminals of that counter. A movable switch contact 820 is connected to the upper input o~ a two-input NAND
gate 836; and a conductor extends ~rom the third output terminal of that counter to the lower input o~ that NAND gate. A movable switch contact 822 is connected to the input of an inverter 832; and the output o~ that invertex is connected to the "data"
input of counter 806. The movable contacts 820 and 822 coact with the stationary contacts 824, 826, 828 and 830 to de~ine a ~8.

~47~66 two-pole, double-thxow switch. In the position $hown b~ Fig. 3C, movable contacts 820 and 822 are in engagement, respectivel~, with stationary contacts 826 and 830. The conductor 734 is connected to the "reset"
terminal of the counter 8060 The output of NAND ~ate 834 is connected to the upper input of NOR gate 838, and also to the input o~ an inverter 844. The output of NAND gate 836 is con-nected to the upper input terminal of NOR gate 840, and also to the input of an inverter 842. The out-puts of inverters 842 and~844 are connected, re-spectively, to the upper and lower inputs of an EXCLUSIVE OR gate 846. The output of that EXCLUSIVE OR gate is connected directly to the conductor 850 and to the input of an inverter 848; and the output of that inverter is connected to the conductor 852. The output of NOR gate 838 is connected to the input of a RELAY DRIVE~ 884; and the output of NOR gate 840 is connected to the input of a RELAY DRIVER 886. The RELAY DRIVERS 884 and 886 could be of different types; but, in the said one preferred embodiment those relay drivers are : simple transistor stages which respond to "0's" at the inputs thereof to provide "l's" at the outputs thereof, and which respond to "l's" at the inputs thereof to provide "0's" at the outputs thereof.
The output o~ REL~Y DRI~ER 884 is connected to one terminal of a relay coil 888; and the output of the REhAY DRIVER 886 is connected to one terminal of a relay coil 890. The other 39.

~047~616 terminals of those relay coils are connected to.yether and to the souxce o~ xegulated plus twenty-~our volts D.C. Those relay coils control contacts, not sho~n, in the dispensing machine,~ vending machine or other device ~ith which .the paper currency validator of the present invention is associated.
At-rest Condition o~ Paper Currency Validator:
In the at-rest condition o~ the paper currency validator, each of the switches 146, 156 and 162 is open; and hence a binary "1" will appear at the lower inputs of NOR gates 758 and 760, on conductor 766, and at the input o~ inverter 772. This means that a binary "0" will appear on conductors 764, 768 and 778, and that a "1" will appear on conductors 776 and 780. The NAND gate 232 in the START AND RUN
LOGIC block 230 in Fig. 3A will respond to the "l's"
at the inputs thereof to apply a "0" to the conductor 234; and the inverter 238 will respond to the resulting "0" at the input thereof to apply l'l's" to the upper input of NAND gate 240 and to the cakhode o~ diode 245. The resulting back biasing o that diode will cause a "1" to appear at the upper input of NAND gate 251. The COUNTERS 804 and 806 in ~ig.
3C will have "0's" at the output terminals thereof;
and NAND gates 834 and 836 will respond to the resulting "0's" at the inputs thereof to apply "l's"
to the upper inputs of NOR gates 838 and 840 and to the inputs of inverters 842 and 844. The resulting application of "0's" to both inputs of the EXCLUSIVE
OR gate will cause that EXC~USrVE OR gate to apply ~ 40.

~l04~7~L66 a "0" to conductor 850 and to the.input o~ invexter 848; and that inverter ~ill apply a "11l to conductor 852 -- and hence to the lower inputs of NAND gate 268 and o~ NQR gate 2B8.

40~.

~L047~66 The "0" an conductor 850 will cause NAND
gate 240 in Fig. 3~ to appl~ a "1~ to conductor 242, and thus to the lower input of N~ND gate 251. The "l's" at both inputs of the latter N~ND gate will cause that NAND gate to apply a "0" to conductor 253, and thus to the intexconnected inputs of NAND gate 434 in the SPE~D MAINTAINING sub-block of Fig. 6.
The resulting "1l' at the output of NAND gate 434 will be applied to the base of transistor 438/ and will render that transistor conductive and cause it to apply a "0" to the cathode of diode 444. The resulting forward biasing of that diode will apply llOI- to the upper inputs o~ N~ND gates 448 and 450;
and the resulting "l's" at the outputs of those NAND
gates will forward bias diode 456 and transistor 466.
The source of regulated plus twelve volts D.C.
: will apply a "1" to the lower input of NAND gate 448.
Capacitor 458 will respond to the forward biasing o~ diode 456 to charge up to a voltage close to twelve volts, and thereby will apply a "1" to the lower input of NAND gate 450. Transistor 466 will become conductive and will thereby apply a "0" to.the base of transistor 468 -- to render the latter transistor non-conductive; and the resulting ~ at the base of transistor 480 will keep that transis~or non-conductive. Consequently, a "0" will appear at the base of transistor 482 to render that transistor non-conductive; and hence cu~rent will not flow through conductor 366 and motor 562. As a result, that motor and the movable parts of the bill tra:nsport will remain at rest.

41.

~11 47~L66 The constant current diode 786 in Fig. 3C
w ill permit a fixed value of direct current to flow through the serially-connected magnetic heads 208 and 210, and thereby will provide a D.C. bias in those heads. However, in the at-rest condition of the paper currency validator, those magnetic heads and the amplifier 790 will cause a "0" to appear on conductor 791. The transistor 338 in the ;:VERLEVEL
Sh~Sr~G sub-block 296 of Fig. 7 will be kept non-conductive by the "0" at the base thereof, and hence transistor 346 also will be kept non-conductive.
As a result, the collector of transistor 346 will permit "0" to appear on conductor 297, and henca at the upper input o NOR gate 2 95.
Ihe "0" on conductor 719 also will be applied to the inputs of FREQUE~CY DETECTORS 792 and 794; and those FREQUE~CY DETECTORS will respond to those 10'9" to permit "1'9" to appear at the outputs thereof. As a result "1" will appear at the upper 2 0 input of each ~OR gate 800 and 802.
The "1" on conductor 242 also will be applied to the input of inverter 264 -- with a consequent application of a "0" to the upper input of ~IA~D gate 266.
In addition, the "1" on conductor 242 will be applied to the inverter 762 in Fig. 3B -- with consequent application of "0~5'1 to the upper inputs of 758 and 760, and to the lower inputs of NOR gates 838 and 840 in Fig. 3C; and those ~OR gates will respond to that "1" or to the "1'9" which the ~AND gates 834 and 836 apply to the lower inputs I:hereof to apply "0'9" to the inputs of REIAY DRIVERS

~2.

~4~6~i 884 and 886. Those RE~Y DRIV~S ~ill apply "l's"
to the le~t-hand texminals o~ rela~ coils 888 and 890;
and hence those relay coils ~ill remai.n unenergized.
The` PU~ G~N~ATOR 252 in L~ig. 3A ~ill be appl~ing steep-sided, flat-topped pulses to the "count" terminal of the BINAR~ COUNTER 254 at a frequency of sixty Hertz; but NAND gate 246 will respond to the "1" on conductor 766 and to the "1" on conductor 242 to apply a "0" to the lower input of NAND gate 248. Although the source of regulated plus twelve volts applies a "1" to the upper input of NAND gate 248, the "0" at the lower input of that NAND gate will cause that NAND gate to apply a "1"
to the "reset" terminal of BINARY COUNTER 254. As lon~ as "1" is applied to that "reset" terminal, "0"
will appear on all o~ the conductoxs 256, 258 an~ 260;
and hence at the lower input of NAND gate 266, at the upper and middle inputs of NAND gate 268, at the upper input of NAND gate 270, and at all of the inputs of NAND gate 272. Those NAND gates will respond to those "0's" to develop "l's" at the outputs thereo~. Inverter 274 will respond to the "1" at the output of NAND gate 272 to apply a "0"
to the anode of diode 276--thereby back biasing that diode, and 42A.

~4716~
thus permitting "0" to appear on conductor 284 ~nd hence at the upper input of NQR gate 295. The "1"
on conductor 776 and the "1" on conductor 780.will c~use ~OR gates 288 and 290.to apply "0" to the ~nodes of diodes 298 and 300 -- thereby back-biasing those diodes, and thus permitting 1l 0 " to appe~r on conductor 284 and hence at the upper input of NOR gate 295.
The "1" on conductor 776 and the "1" on conductor 766 will cause the NOR gates 292 and 294 to apply "0's" to the middle and lower inputs of NOR gate 295; and hence that NOR gate will apply a 'llll to the cathode of diode 320 -- with consequent back-b.iasing of th~t diode and the resulting application of a "1"
to the second lowermost input of NAND gate 326. The transistor 302 will be conductive, and hence will be applying "0" to the input of inverter 314; and that inverter will apply a "1" to the cathode of diode 318 -- with consequent back-biasing of that diode and a resulting uninterrupted application of a "1"
to the second lowermost input of NAND gate 326.
The "0" on conductor 234 will cause NAND
gate 328 in the MOTOR REVERSE LOGIC block 286 in Fig. 3A to apply a "1" to the lowermost input of ~AND gate 3 26; and the "1's" at -the outputs o~
NAND gates 268 and 270 will be applied to the upper-most and second uppermost inputs of NAND gate 326.
AS a result, that NAND gate will apply a "0" to the input of RELAY DRIVER 330 -- with the consequent application of a "1" to the left-hand end of relay coil 490 in ~ig. 8 -- causing that coi~ to remai.n ~ 43.

`de-e~ergized and to pexml~ the ~o~able rela~ con-tact~ 492 and 494 to xe~ain in their "~oxward"
positions.

43A.

~ - ~ ~

1~147~L616 NAND gate 326 also will ~ppl~ a "0" to the upper input o~ NAND ~ate 328O
The dispensing m~chine, with which t~e paper cuxrenc~ validatox is associated, will be ~pplying "l's~" to the:texminals 526 an~ 530 of the COUPLING
block 524 in Fig. 3B; and hence the light-emitting diodes within the opto-couplers 540 and 542 will be emitting light. The light-sensitive elements of those opto-couplers ~ill xespond to that light to be~conductive, and hence "0" will be applied to the cathodes o~ the diodes 548 and 550. The resulting forward biasing of those diodes will cause "0" to be applied to the upper and lower inputs of NAND gate 720 and also to the inputs of inverters 724 and 726.
Those inverters will apply "l's" to the lowermost inputs of NAND gates 728 and 730. The "l" at the output of NAND gate 266 of the TIMER LOGIC block 262 in Fig. 3A will appear at the second uppermost inputs of NAND gates 728 and 730, the "1" at the output of NAND gate 328 in the MOTOR REVERSE LOGIC
block 286 in Fig. 3A will appear at the second lower-most inputs of NAND gates 728 and 730, and the "l"
at the output of inverter 314 in that block will appear at the uppermost inputs o~ NAND gates 728 and 730. As a result "0's" will appear at the outputs of those NAND gates, and hence at the "reset"
terminals of COUNTERS 804 and 806 in the VALIDATING
AND VENDING LOGIC block 784 in Fig. 3C. The "1"
at the output of NAND gate 720 will cause inverter 722 to apply a "0" to the middle input of NOR gate 758.

44.

i The "0" on conductor 791 will be appLied to the base of txansi~tor ~82 in.the BORD~R sub-block 516 in Fig~ 4; and the xesulting non-conducti~e s ate o~ that tran~iskor will enable ~ s" l:o appea~ at the uppe~ inputs o~ NAND gates 696 and 700. The "0" on conductox 778 will be applied to the lower input of ~AND gate 698; with a consequent "1" at the output o~ that NAND gate and hence at the lower inputs of NAND gate 696 and of NOR gate 708. That NOR gate will apply a "0" to the lower input of NAND
gate 706. NAND gate 696 will apply a "0" to the upper input of NAND gate 698, and also to the lower input o~ NAND gate 700; and the resulting "1" at the output of the latter NAND gate will ~orward bias diode 702 and thereby charge capacitor 712 and apply a "1" to the interconnected inputs of NOR gate 704.
That NOR gate will apply a 1l ol- to the cathode of diode 713 to forward bias that diode; and hence capacitor 716 will be discharged, and NOR gate 706 will have "0's" at both inputs thereof, and thus will apply a "1" to~the upper input of NOR gate 708 and also to conductor 517. That conductor will apply that "1" to the second uppermost input of NOR gate 518 and will thereby cause that NOR gate to apply a "0" to the input of inver.te~ 520 -- with consequent application of a "1" to the lower inputs of NOR gates 8dO and 802 in the VALIDATION ~ND VENDING
LOGIC block 784 in Fig. 3C.

~ 45.

~47~
The "1" on conductor 776 will be applied to the second lawexmost input o~ ~OR gate 518,~ the`"0"
on conductox 764 ~ill be applied to the upper inputs o~ NOR gates 290 and 2~94, ~he llol~ on conductor 768 will be ~pplied to...~the middle input of NOR gate 288 and to the lower input o~ NO~ ~ate 294, and the "0" on conductor 778 will be applied to the middle input of ~OR gate 292. The "1" on conductor 780 will be applied to the lower inputs of NOR gates 292 and 518 and of NAND gate 270, and the "0" on conductor 850 will be applied to the lower input of NOR gate 290. The CURRENT SENSING sub-block 362 will be applying a "1" to the uppermost input of ~OR gate 518.
Qperation of Paper Currency Validator by Authentic U.S. One Dollar Bill: If an authentic U.S. one dollar bill is disposed adjacent the platform 32 of the bill transport 30 of Fig. 1 so the black-ink face thereof is up and so the bottom of the portrait of George Washington is close to the flange 142 on the cover 140, the upper portion of the portrait background will be in register with the magnetic head 208 and the lower portion of that poxtrait background will be in register with the magnetic head 210, as indicated by Fig. 2. If the leading edge 45A.

of that bill is moved far enough inwardly of that bill transport, it will cause the actuator 148 of switch 146 to move far enough to close that switch; and, thereupon, the "1" at the lower input of NOR gate 758 in the SWITCH
LOGIC block 738 will change to "0". I}~mediately, the output of that NOR gate will change to "1" -- with a consequent "1" on conductor 764 and a consequent "0" on conductor 776. The resulting "1" at the upper input of NOR gate 294 will not be effective at this time because the "l" at the middle input of that NOR gate had been maintaining "0" at the output of the NOR gate. Simil-arly, the resulting "1" at the upper input of NOR gate 290 will not be effective at this time because the "1'' at the middle input of that NOR gate had been keeping "0" at the output of that NOR gate. The resulting "0"
at the second lowermost input of NOR gate 518 will not be significant at this time kecause the "l's" at the second uppermost and bottom inputs will be maintaining "0" at the output of that NOR gate. The resulting "0"
at the upper input of NOR gate 292 will not be signi-ficant at this time because the "l" at the lower input will be maintaining a "0" at the output of that NOR
gate. Similarly, the resulting "0" at the upper input of NOR gate 288 will not be significant at this time because the "1" at the lower input will be maintain-ing a "0" at the output of that NOR gate. However, the resulting "0" at the upper input of NAND
gate 232 will cause a "l" to appear at the output of that NAND gate and hence on conductor 234.
The resulting application of "1" to the lower ~6.

~4~i~16~i input of NAND gate 328 will not be significant at this time because the "0" at the upper input of that M~D gate will maintain ~1" at the output of that NAND gate. However, the application of "1" to the input of inverter 238 in the VEND ~N~BL~ LOGIC
block 236 will cause that inverter to apply a "0"
to the cathode o~ diode 245 and to the upper input of NAND gate 240. The "0" at the upper input of that NAND gate will not change the output of that NAND gate because conductor 850 has been applying a "0" to the lower input o~ that NAND gate; but the "0" at the cathode of diode 245 will forward bias that diode, and will thereby apply a "0" to the upper input of NAND ~ate 251. The resulting application of "1" to the interconnected inputs of NAND gate 434 in the SPEED MAINT~INING sub-block 358 of the MOTOR CONTROLLING block 354 will cause that NAND gate to apply "0" to the base of transistor 438, thereby rendering that transistor non-conductive.
The resulting "1" at the cathode of diode 444 will back-bias that diode, and hence will enable the source of regulated plus twelve volts D.C. to apply "l's" to the upper inputs of N~ND gates 448 and 450.
The resulting zero at the output of NAND gate 448 will back-bias diode 456, and thereby permit capacitor 458 to s~art discharging through resistor 460. However, that capacitor noxmally requires about eighteen seconds to discharge; and, during that length of time, it will continue to apply a "l",to the lower input of N~ND gate 450. The "1" at the I

47.

~109~7166 upper input o~ NAND gate 450 will cause that NA~D
gate to appl~ a "0" to the base of txansistor 466, thereb~ rendering that transistor non~conductive.
At such time, current ~ill flow ~xo~ the output of amplifier 420 in the SPEED AD~USTING

47A.

~4~16~
sub-block 356 o~ the MOTOR CONTROLLING block 354 via Zener diode 430, resistox 43~, conductox 364, the base~e~ittex circuit of transis~ox 46~ in SP~ED ~AIN-TA~N~G sub~block 358, and xesistor 479 to ~round; and that flow o~ current ~ill rendex that txansistor conductive. The resultin~ drop in the volta~e at the junction of diode 476 and resistor 478 in that sub-block will render transis~or 480 conductive;
and, thereupon, current will flow through the base-emitter circuit of transistor 482 and render that transistor conductive. At such time, current will flow from the source of regulated plus twenty-four volts D.C. via transistor 482, conductor 366, the movable and le~t-hand relay contacts 492 in the MOTOR AND REL~Y sub-block 360, motor 562, the left-hand and movab}e relay contacts 494, conductor 372, and in part to ~round through resistor 502 in the CURRENT SENSING sub-block 362 and in part to ground through resistors 504 and 506. The motor 562 will start rotating in the "forward" direction, and the output shaft 203 thereo~ will rotate worm gear 202, worm wheel 200, and shaft 182; and the belt 198 and its counterpart belt will move the lower "runs"
thereo~ to the~xi~ht in Fi~. l,.and will thereby move the bill inwardly of the bill transport. The motor 562 will drive those belts, and hence each inserted bill,.at the rate of ten inches per second.
After the leading edge o~ the bill has been moved ~ppxoximateIy one~hal~ o~ an inch ~urther inwardly of the bill transport by the belt 198 and ~ 48.

- ~\

~0~7~6 its counterp~rt, the ~ctu~tor 158 o~ the switch 156 ~ill have been mo~ed ~ar enough to close th~t switch.
Thereupon, "O" will ~ppear on conductor 766 and ~'1"

48A.

~al47~6q6 will appear on conductor 778. The resultin~ "0" at the middle input o~ NAND ~ate 232 in the START A~D
RU~ LOGIC block 230 will not be signi~icant at this time, because switch 14-6 rem~ins closed and thereby maintains "1" at the output of that N~ND ~ate.
Similarly, the resulting "0" at the middle input of NOR gate 294 will not be significant at this time, because a "1" appears at the upper inpu~ of that NOR gate. However,the ~'0" at the lower input oE NAND
yate 246 will change the output of that NAND gate to l'l", and thereby will cause NAND gate 248 to xemove the "1" from the reset input of BINARY COUNTER
254; and, thereupon, that counter will begin to count the pulses from the PULSE GENERATOR 252.
The application of a "1" to the middle input of NOR gate 292 is not significant at this time because the "1" at the bottom input of that NOR gate is maintaining "0" at the output of that NOR gate.
The application of a "1" to the anode of the diode 340 in the OVERLEVEL SENSING sub-block 296 of Fig~ 7 will forward bias that diode; but the "0" at the base of transistor 338 will keep that transistor non-conductive, and will thereby act to keep transistor 346 non-conductive. Consequently, "0" will continue to appear at the output of that OVERLEVEL S~NSING
sub-block. The application of "1" to the lower input of NAND gate 698 in the BORD~R sub-block 516 of Fig. 4 will not be e~fective at this time, because the NAND gate 696 will continue to apply "0" to the uppex input of NAND gate 698. Consequently, the ~ 49.

1047~66 motor 562 will cause belt 198 and its counterpart to continue to moYe the bill in~axdly o~ the paper curxency valldator, and the B~NARY COUNTER 254 will begin countin~.

49A.

7~L66 During each operation of the paper cuxrenc~
validator, ~ number of events must occur within closely controlled, indi~idually-di~erent ti~e ~e~iods-o~
the ~otox 562 will xeVexse and will cause the belt 198 and its counterpaxt to mo~e the inserted bill back out through the ~xont of the bill transport.
For example, the switch 162 must close ~ithin five hundred and thirty-~ive milliseconds after the switch 156 is closed, a validation signal must be developed within six hundred and sixty-eight milliseconds-:after switch 156 is closed, and switch 156 must re-open within seVen hundred and thirty-five milliseconds after it is closed. Also, a time period of one hundred and thirty-~our milliseconds must have been developed by the time swit~h 162 re-opens i~ a validation signal is presentO Those various time periods are established by the TIMER block 244 and by the TIMER LOGIC block 262.
The BINARY COUNTER 254 in TIM~R block 244 will apply a 'tl" to conductor 256 whenever the total count therein is four through seven, twelve throuyh ~i~teen, twenty through twenty-three, twenty-eight through thirty-one, thirty-six through thirty-nine, and forty-four. That counter will apply a "1" to conductor 258 whenever the total count therein is eight throuyh fifteen, twent~-~our through thirty-one, and forty through ~orty-four; and it will apply a "1~' to conductor 260 whenever the total count therein is thirt~-two through ~orty-~our.

50.

47~6 The BINA~Y COUNT~R 254 ~ill incxease.the total count therein each time.it .senses the negative-going edge of a pulse ~ro~ :the PUhSE- GEN~RATOR 252;
and it will Xecei~e such pulses at the rate of one every sixteen and seven-ten~hs ~illisleconds. Appxoxi-matel~ sixty-se~en milliseconds a~ter the switch 156 is closed, a "1" will appear on conductor 256 and ~111 be applied to the upper input o~ NAND gate 272; but that '`1l' will not have any immediate e~fect 10. because conductors 258 and 260 will continue to apply "0's" to the middle and lower inputs o~ that NAND gate. Approximately one hundred and thirty-four milliseconds after switch 156 closes, the l'l" on conductor 256 will change back ko "0" and the ~0" on conductor 258 will change to "1". The resulting "1"
at the lowex input o~ NAND gate 266 is not significant at this time because inverter 264 continues to apply a "0" to the upper input o~ that NAND gate. The resulting 1'1" at the upper input of NAND gate 268 is not significant at this time because conductor 260 continues to apply a "0" to the middle input of that NAND gate. ~he resulting "1" at the middle input of NAND gate 272 is not significant at this time because conductor.256 is applying a "0" to the upper input, and because conductor 260 is applying a "0"
to the lowex input, o~ that NAND gate.
Approximately one hundxed and foxt~ milli-seconds after the s~itch 156 cl~sed, the leading edge o~ the leading engra~ed border on the black-ink ~ace of ~he bill will reach, and will start to move past, .

~ L0~71~6 the air gap of the magnetic head 208. Thexeuponl that m~gnetic head will apply pulses to the ampli~ier 790; and that ampli~ier ~ill supply ampli~ied pulses to the conductox 791.
Those ampli~ied pulses will not have a ~xequenc~ to which eithex o~ the FR~QUE~CY D~TECTORS
792 and 794 is intended to respond; and hence those ampli~ied pulses will not a~ect the "l's" at the outputs of those FR~QUENCY DETECTORS. Those ampli$ied pulses will be appliéd to the base of transistor 338 in the OVERLEVEL S~NSING sub-block 296 o~ FIG. 7; but those ampli~ied pulses will nat have su~icient amplitude to render the transistor 338 conductive~ Conse~uentl~, that O~ERLEVEL SENSING
sub-block will continue to permit "0~' to appear on conductor 297. Those ampli~ied pulses also will be applied to the base o~ transistor 682 in the BORDER
sub-block 516 o~ Fig. 4; and the negative-going portions of those amplified pulses will make that transistor non-conductive, but the positive-going portions of those ampli~ied pulses will render that transistor conducti~e. As a result, during the time period when the air gap of magnetic head 208 is sensing the leading border o~ the bill, the upper inputs of NAND gates-696 and 700 will 'see" a succession of alternating "O's" and "l's".
The ~irst "0" which is applied to the upper input o~ NAND gate 696 will ~ake the output o~
th~t NAND ~ate a "l"; and NAND gate 698 will respond to the resulting "1" at the upper input thereof and to the "1" which conductor 778 applies to the lower 52.

- ~ \

~7~61Ei input thereof to apply a continuous "0" to the lowex inputs o~ NOR gate 708 and o~ NAND ~ate 696. The NAMD
gates 696 and 698 thus act as an electronic ~'latch~' which will maintain "0" at.the lo~ex input of ~OR gate 708 ~nd "1" at the lower input of NAND gate 700O The latter NAND gate will, in this way, be able to respond to the succession o~ alternating "0's" and "l's" at the upper input thereo~ to apply a succession o. "l's"
and "0's" to the anode o~ diode 702. Each "1" at t:hat anode will forward-bias that diode and permit capacitor 712 to become charged; and each "0" at that anode will back-bias that diode and pe.rmit that capacitor to start disch'arging through resistor 710. However, the time constant of the RC network constituted by that capacitor and that resistor is about sixty milliseconds; and hence the rapidly-recurring forward-biasing of diode 702,.in response to the amplified pulses ~rom amplifier 790, will enable the charge on capacitor 712 to keep a "1"
at the interconnected inputs o~ NOR gate 704. The resulting "0" at the output of that NOR gate will ~orward-bias the diode 713, thereby keeping capacitor 716 discharged and thereby applying a "0" at the upper input of NOR gate 70fi. m e latter NOR gate will respond to the "0" at the lower input thereof, which has been maintained by the NOR gate 708, to apply a continuous "1" to the upper input of NOR gate 708 and to conductor 517. All o~ this means that as long as the leading border of the bill is in engagement with the air gap of the magnetic head 208, the capacitor 712 will maintain a "1" at the interconnected inputs of NOR gate 704.

53.

1047~1L66 The leadin~. edge o~ the le~ding bo.rder on the black-ink ~ace o~ the inserted bill will moye into. en~ag~ent with the air gap o~ the magnetic head 210 almost immedi-~tely a~ter the trailing edge of that border mo.ves beyond the air gap o~ the magnetic head 208; and the resulting ampli~ied pulses from amplii.ier 790 will forward-bias and back-bias diode 702 in rapid succession.
As a r~sult, until the trailing edge of the leading border moves beyond the air gap of the magnetic head 210, the~.. capacitor 712 will remain essentially full.y charged, and thus will maintain a "1" at the inter-connected inputs of NOR gate 704. In the preferred embodiment of the present invention, the magnetic heads 208 and 210 will respond to the leading border on the bill to cause the amplifier 790 to apply amplified pulses to the transistor 682 for approximately ninety milli-seconds; and, during those ninety millisecondsl the voltage at the upper terminal of capacitor 712 will remain close to twelve volts.
Approximately two hundred and one milli-seconds a~ter the switch 156 closed, and hence while the leading border of the bill was in engagement with the air gap of magnetic head 210, BINARY COU~TER 254 applied "l's" to conductors 256 and 258. However, because conductor 260 was still applying "0's" to the middle input of NAND gate 268 and to the lower input o~
NAND gate 272, and because conductor 242 was-applying a ~'1" to the input o~ inverter 264 and thus was causing that inverter to apply a ~l o ~l to the upper input of NAND gate 266~ the "l's" on conductors 256 and 25B were not significant at that time.
54.

~ 7~66 As soon as the trailin~ edge of the'leading bo~der on the black-ink ~ace of .the bill mo~es beyond the air gap of magnetic head 210~. the capacitor 712 will start discharging through resistox 710. About sixty milli-seconds later,,the charge on that cap~citor will have dissipated through that res'istor to the point where the ~1 !t at the interconnected inputs-of NOR gate 704 becomes a "0". At such time, a "1" will appear at the output of that NOR gate; and that "1" will back-bias diode 713.
Thereupon, capacitor 716 will start to charge; but the time constant of the RC network, constituted by that capacitor and by resistor 714, is about thirty milliseconds. Consequently, a "0" will continue to appear at the upper input of NOR gate 706 for a total of about ninety milliseconds after the trailing edge of the leading border ves out of engagement with the air gap of the magnetic head 210; and then that "0" will change to a "1".
Approximately seventy milliseconds after the trailing edge of the leading border moves out of engagement with the air gap of the magnetic head 210 7 ' and hence approximately twenty milliseconds before the "1" on ¢onductor 517 can become a "0", the leading edge of the bill will cause the actuator 164 of the switch 162 to move far enough to close that switch. In the said pre~erred embodiment of the present invention, the closing of switch .162 occurs approximately three hundred milliseconds a~ter the closing of switch 156. The resulting "0" at the lowex input of NOR gate 760 will coact with the "0" at the upper input of that NOR gate d~
~ 55.

~47166 to apply a "1" to conductor 768 ~nd to the input of inverter 774 -- with a conse~uent appIic~tion o~ 1-0l' to conductor 780. The "1" ~hich will appear at ~he middle input o~ ~OR gate 288 ~ill not be ~igni~icant at this time because conductor 85Z is applyin~ a "1 to the lo~er input o~ that NOR ~ate.

55A.

~047~616 Similarl~, the resulting "1" at ~he lower input of NOR ~ate 2~4 is not significant at this time because conductor 764 is applying a "1" to the uppex input of that NOR gate. The xesultin~ "0~ at the lower input o~ NA~D ~ate 232 is not significant to this kime because conductors 766 and 776 are applying "0's" to the upper and middle inputs of that NAND gate; and the resulting "O" at the lowex input of MAND ~ate 270 is not sig-nificant at this-time because conductor 260 is applying a "0" to the upper input of that NAND gate. The resulting "0" at the middle input of NOR gate 290 is not significant at this time because conductor 764 is applying a "1" to the upper input of that NOR
gate; and the resulting "0~ at the lower inpuk of NOR
gate 292 is not significant at this time because conductor 778 is applying a "1" to the middle input of that NOR gate. The resulting "0" at the lowermost input of NOR gate 518 is not significant at this time because conductor 517, which extends from the BORDER
sub-block 516, is applying a "1" to the second uppermost input of that NOR gate.
Appxoximately twenty milliseconds after switch 162 c~osed, and hence approximately three hundred and twenty milliseconds after switch 156 closed~ the charge on capacitor 716 in the BORDER Su~-block 516 of Fig. 4 will increase to a value at which the "0" at the upper input of NOR gate 706 will change to a "1". The resulting "0" on conductox 517 will be applied to the upper input of NOR gate 708 and to the second uppermost 56.

~ 47~1~6 input of NOR gate 518. The "0" at.the second uppe~most input o~ NOR gate 518 will coact with:the "0's" at .all of the other inputs o~ that ~OR gate to cause that NOR
gate to apply a "1" to the input of inverter 520;~ and the resulting "0" at th.e output o~ that inverter will be applied to the lower inputs o~ ~OR gates 800 and 802.
However, the:outputs. of those NOR gates will remain "0"
because "l's" appear at the outputs o~ the FREQUENCY
DET~CTORS 792 and 794. The "0" at the upper input of NOR gate 708 will coact with the "0" at the lower input of that NOR gate to apply a "1" to the lower input of NOR gate 706. Thereupon those NOR gates will act as an electronic "latch" which will maintain a continuous "0" on conductor 517, and hence at the second uppermost input of NOR ~ate 518, as long as switch 156 remains closed and keeps a "1" on conductor 778, and hence at the lower input of NAND gate 698.
Approximately thirty-four milliseconds after switch 162 closed, and hence approximately three hundred and thirty-four milliseconds after switch 156 closed, BINAR~ COUNT~R 254 will again apply a "1" to conductor 256. However, that "1" will not be significant at this time because conductors 258 and 260 are appl~ing "0'.s"
to the middle and lower inputs of NAND gate 272.
Approximately si~ty milliseconds a~ter switch 162 closed, and hence approximately three hundred and sixty milliseconds after switch 156 closed, the vertical grid lines ln the leading hal~ o~ the uppex portion of the portrait background will engage and start moving past the air gap o~ the 57.

~7~6~
magnetic head 208. That ~netic head will xespond to those vertical gxid line~ to de~elop pulses, and amplifier 790 will amplif~ those p~l~es and apply them to conductor 791. The base o~ transistox 338 in the nyERLEvEL
SENS~NG sub-block 296 of Fi~o 7 will :receive those amplified pulses; but the ~mplitude~ of those amplified pulses will not be great enou~h to. cause that transistor to become conductive. Consequently, that O~ERLEVEL
SE~SING sub-block will continue to supply a "0" to conductor 297. Those a~pli~ied pulses also will be applied to the base of transistor 682 in the BORDER
sub-block 516 o~ Fig..4; and that sub-block will respond to those amplified pulses to charge capacitor 712 and to forw~rd'bias diode 713, and thereby apply a "0" to the upper input of NOR gate 706. However, because that NOR gate and NOR ~ate 708 are acting as an electronic latch which maintains a con~inuous "0" on conductor 517, the amplified pulses which are applied to the BORDER
sub-block 516 can not change the "0" on conductor 517, and hence.:can not cause a change in the "0's" at the lower inputs of NOR gates 800 and 802 in Fig. 3C.
The amplified pulses from amplifier 790 will be applied to the inputs o~ FREQUENCY DETECTORS 792 and 794; and the back-to-back diodes-858 and 860 in the former FREQUENCY DETECTOR and the counterpart back-to-back diodes, not shown, in the latter FREQUENCY DETECTOR
will limit the values of the amplified pulses that are applied to terminal 3 o~ the phase locked loop 854 in the foxmex FREQUENC~ PETECTOR and to terminal 3 of the ~v~
counterpart phase locked loop in the latter FREQUENC~
DETECTOR. The.phase locked loop 854 is set to respond to the signals which are developed b~ the magneti:c heads 208 and 210 when the ~ertical grid lines o an authentlc U.S. one dollar bill engage the air gaps o~
those ma~netic h~ads while *he lower "~uns" o~.the belt 198 and its coun.terpart are moving an inserted bill at the rate of ten inches per second; and the phase locked loop in FREQUENCY DE~ECTOR 794 is set to respond to the signals which are developed by the magnetic heads 208 and 210 when the vertical grid lines of an authentic U.S. five dollar bill engage the air gaps of those magnetic heads while the lower "runs" of the belt 198 and its counterpart are moving an inserted bill at the rate of ten inches per second.
The oscillator of the phase locked loop 854 will tend to shift its center frequency to match the frequency of the amplified pulses which are applied to terminal 3 thereof; but the values of capacitors 866, 870 and 874 and of resistor 872 limit the shifting of that center frequency to plus or minus five percent of that center frequency. As a result, that phase locked loop establishes a desirably narrow pass band that will enable it to respond to amplified pulses which the magnetic heads 208 and 210 generate in response to an authentic U.S. one dollar bi.ll but that will.enable it to be unresponsive to amplified pulses which the magnetic heads 208 and 210 generate in response to a spurious one dollar bill. ~s the oscillator o~ the phase 59.

~L7~

locked loop 854 "locks on" the fxe~uency o~ the'amplified pulses applied to the:terminal 3,,the:"1" on conductor 795 will chan~e to a "0".; and hence'NOR ~ate 800 will change the "0" at'the :outp~t the~eo~ to a "1" and will appl~ that "1" to the clock input of C'OUNTER-80~.
Inverter 819 will be responding to the "0" at-output ter-minal 4 of that COU~TER to apply a "lll to the data input terminal of that COUNTER; and hence the "l" at the cloc~ input of that COUN~ER will cause that COUNTER
to develop a "1" at output.terminal l thereof. Howevér, because that output terminal is not connected to any-thing,,the development of the "l" at that output terminal is not signific~nt. As long as the oscillator of the phase locked loop 856 xemains "locked on" the ~:req.uency o the amplified pulses applied to the terminal 3, the "1" will continue to appear at the output o~ NOR gate 800 and hence at the clock input of COUNTER 804. However, when the vertical grid lines in the leading half of the upper portion of the portrait background move beyond the air gap of magnetic head 208, as they will do approximately three hundred and seventy-four milliseconds ~fter switch 156 closed, t.he "0" at the output of that phase locked loop will.be chan~ed back to a "1".
Thereupon, the "l" which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed to a lloll ~pproximately four hundred and one milliseconds after switch 156 closed, BINARY COUNTER 254 will a~ain 30; apply a "1" to conductor 258. However that "l" will be unable to change the 60.

~7~

output of any of the ~AND gates 266,,268, and 272,, because each o~ those NAND,gates has a "0" at one of the inputs thereof.
Approximatel~ four hundred and ~ix milli-seconds after switch 1~6 closed~ the ~ertical grid lines in the leading half of the lower portion of the portrait background will move into engagement with the air gap of the magnetic head 210. Neither the OVERL~VEL
SENSING sub-block 296 nor the BORDER sub-block 516 will change.the output thereof in response to the resulting amplified pulses from amplifier 790. However, the FREQUENCY DETECTOR 792 will respond to those ampli-fied pulses, in essentially the same manner in wh.ich it responded to the ~mpli~ied pulses corresponding to the leading half of the upper,portion of that portrait backgro,und, to again cause NOR gate 800 to apply a "1" to the clock input of COUNTER 804. Inverter 819 will be responding to the "0" at output terminal 4 of that COUNTER to apply a "1" to the data input terminal of that COUNTER; and hence the "1" at the clock input of that COUNTER will cause that COUNTER to develop a "1" at output terminal 1 thereof. That "1" at that output terminal will not be significant because that output .terminal is not connected to anything,,and the "1" which is developed at output terminal 2 of that COUNTER is not signi~icant at this time because NAND
gate 834 will have a "0" at the lo~er input thereof --and hence will continue ^to apply a "1" to the upper input of NOR gate 838 and to the input of inverter 844.
~hen the vertical lines in the leading half of t:he lower portion of the portrait background move beyond 61.

6~

the air gap of magnetic head 210, as:they will do ap-proxima:$e~1.y ~our hundred and thirt~-eight milli-seconds ~fter switch 1~6 closed~ the "0" at the output 61A.

~4~6i~
of FREQUENCY DETECTOR will be changed back to a "1".
Thereupon, the "1" which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed back to a "0".
Approximately four hundred and fifty-six milli-seconds after switch 156 closed, the vertical grid lines in the trailing half of the upper portion of the portrait background will move into engagement wi.th the air gap of the magnetic head 208. Neither the OVERLEVEL SENSING
sub-block 296 nor the BORDER sub-block 516 will change the output thereof in response to the resulting amplified pulses from amplifier 790. ~lowever, the FREQUENCY DETEC-TOR 792 will respond to those amplified pulses, in essen~
tially the same manner in which it responded to the am-plified pulses corresponding to the leading half of the upper portion of that portrait background, to again cause NOR gake 800 to apply a "1" to the clock input of COUNTER 804. Inverter 819 will be responding to the "0"
at output terminal 4 of that COUNTER to apply a "1" to the data input terminal of that COUNTER; and hence the "1" at the clock input of that COUNTER will cause the COUNTER to develop a "1" at output terminal 1 thereof.
That "1" at that terminal will not be significant because that output terminal is not connected to anything; but the resulting application of "l's" to output terminals 2 and 3 of that COUNTER will cause NAND gate 834 to apply a "0" to the upper input of NOR gate 838 and to the input of inverter 844. That NOR gate will continue to apply a "0" to the input of RELAY DRIVER 88 because conductor 242 continues to apply a "1"
to the lower input of that NOR gate;
,.., ~

1~47~6 but invertex 844 wil} apply a "1" to the lowe~ input of exclusive OR gate`846. .The resulting "1" on conductor 850 is regarded as a VALID~TION signal; but it will not affect the output o NOR ga.te 290 at this time because conductor 764 is applying a "1l' to the upper input o~
that NOR gate, and it will not affect the.output of NAND gate 240 at this time because NAND gate 232 and inverter 238 are applying a "0" to the upper input of NAND gate 240. The resulting "0" on conductor 852 will not afect the output of NO~ gate 288 at this time because conductor 768 is applying a "1" to the middle input of that NOR g,ate; and the resulting "0" at the lower input o NAND gate 268 will not be significant at.this time because conductor 260 is applying a "0" to the middle input of that NAND gate.
Approximately four hundred and sixty-eight milliseconds after switch 156 was closed, and hence while the air gap of magnetic head 208 still is in engagement with the trailing half of the upper portion o the portrait background, BINARY COUNTER 254 will again apply a "1" to conductor 256. However, that "1"
will not change the output of NAND gate 272 because conductor 260 continues to apply a "0" to the lower input of that NAND gate.
When the vertical grid lines in the trailing half of the upper portion of the portrait background move beyond the air gap o magnetic head 208, as they will do approximateIy four'hundred and seventy-two milli,seconds after $witch'156 closed, the "0" at the output of ~REQUE~CY DETECTOR 792 will be changed back to a "1".

~ 63.

~/--~1~47~

Thereupon, the "1" which ~OR:g~te 800 w~ appl~in~ to the clock input o~ COUNTER 804 ~11~ ~e:ch~n~ed b~ck to a "0"

63A.

~ pproxim~tel:~ four hundred and ninety-seVen milliseconds after switch'156 was closed~ the vertical grid lines in the trailing half o the lower poxtion of the poxtxait backg~ound will moVe into engagement with .the air gap of the magnetic head 210. Neither the OvERhEvEL S~NSING sub-bloc~ ~96 nor,the BORD~R sub-block 516 will change the output therleof in response to the resulting amplified pulses from amplifier 790.
However the FREQUENC~ DETECTOR 792 will respond to those amplified pulses, in essentially the same manner in which'it responded to the amplified pulses corresponding to the leading half of the upper portion of that portrait back~round, to again cause NOR gate 800 to apply a "1"
to the clock input o~ COUNTER 804. Inverter 819 will be responding to the "0" at output terminal 4 of that COUNTER to apply a "1" to the data input termina} of that COUNTER; and hence the "1" at the clock input o~
that COUNTER will cause that COUNTER:,to develop a "1"
at output terminal 1 thereof. That "1" at that:output terminal will not be significant because that output terminal is not connected to anything; but the resulting application o~ "l's" to output terminals 2 and 3 of that COUNTER will continue to cause NAND gate 834 to apply a "0" to the upper input of NOR gate 838 and to the input of inverter 844. That NOR gate ~ill continue to apply a "0". to the input of REL~Y`~DRIVER
'884 because conductor 242 continues to apply a "1" to the lower input o~ that NOR gate; and inverter 844 will continue to apply a "1" to the lower input o~ exclusive OR gate 846. The COUNTER 804 will develop a "1" at ~ 64.

7~

output texminal 4 thereo~, and inYerter 819 will xespond to that "l." to apply a "0" to t~:e data input texminal of that COU~T~R.

64~.

3~D47~i6 Approximately five hundred and thirt~.-two milliseconds after switch 156 closed, the trailing half of the lower portion of the portrait bac~round will move beyond the air gap of the magnetic head 210; and, at such time, the "0" at :the output of' FRE~UE~CY D~TECTOR
792 will a~ain be changed ~ack to a "1.". Thereupon, the "1" which NOR gate 800 was applying to the clock input of COUN~ER 804 will be changed back to a "0".
It will be noted that the leading half of the upper portion of the portrait background of the inserted bill engages and mo~es beyond the air gap of the magnetic head 208 before the leading hal of the lower portion of that portrait background can engage the air gap of the magnetic head 210. That leading half of that lower portion of that portrait background will move beyond the air gap of magnetic head 210 before the trailing hal~ of the upper portion of that portrait background can engage the air gap of the magnetic head 208. That trailing half of that upper portion of that portrait background will move beyvnd the air gap of magnetic head 208 before the trailing half o~ the lower portion of that portrait background can engage the air gap of the magnetic head 210. As a result, the magnetic heads 208 and 210 can coact with the four herein-described portions of an inserted bill to provide separate four groups of amplified pulses which are spaced apart in point of time.
Immediately befoxe the trailing half of the lower portion of the portrait back~round mo~es beyond the air gap of magnetic head 210, the leading edge of the "0" of the "ONE~', 1~47166 which is intermediate khat portrait background and the trailing bordex o~ the inserted bill, will engage the air gap of magnetic he:ad 2080 The:resulting pulses from that magnetic head will be ampli~ied by amplifier 790 and applied to the OVE~EVEL S~NSING sub-block 296, to the BORD~R sub-block 516, ana to the FR~QUENCY
DETECTORS 792 and 794. The amplitude of the resulting amplified pulses will not be great enough to cause that OVERLEV~L SENSING sub-block to change the "0" at the output thereo~ to a "1"; and the frequency of those amplified pulses will be quite different from the frequencies to which those FREQUENCY DETECTORS are set. As a result~ those amplified pulses will not affect that OVERLEVEL SENSING sub-block or those FREQUENCY DETECTORS. Those ampli.fied pulses will cause the BORDER sub-block 516 of Fig. 4 to charge the capacitor 712; but the NOR gates 706 and 708 will continue to act as an electronic latch which will maintain a continuous "0" on conductor 517.
Approximately five hundred and thirty-~ive milli-seconds after switch 156 closed, BINARY COUNTER will apply a "1" to conductor 260. However, at this time, that "1" will not be able to change the output of NAND
gate 268 because "0's" are applied to the upper and lower input o~ that NAND gate, will not be able to change the output of NAND gate 270 because a "0" is bein~ applied to the lower input of that NAND ~ate, and will not be able to change the output of NAND gate 272 because "0's" are applied to the upper and middle inputs o~ that NAND gate.

66.

- \

The ~O~ between the portrait background and the trailing border of t~e ins-erted bill will coact with the magnetic heads 208 and 210 to provide repeated pulses to the amplifier 790,until the "E~' of that ''ONEI' has mo~ed beyond the air gap of magnetic head 210. However, the resulting amplified pulses from amplifier 790 will be unable to change t~e outpu~ of any of OVERLEVEL SENSING sub-block, of ~ORDER sub-block 516,,and of FREQUENCY DETECTORS 792 and 794.
Approximately six hundred and two milliseconds after switch 156 closed~ the BINARY COUNTER 254 will again apply a l'l" to conductor 256. However, that "1" will not affect the output of N~D gate 272; because con-ductor 258 is applying a "0~' to the middle input of that ~AND gate.
Appro~imately seven hundred milliseconds after the leading edge of the inserted bill caused actuator 148 to move far enough to close switch 146, the trailing edge of that bill will permit that actuator to move far enough in the opposite direction to permit that switch to xe-open. The resulting "1" at the lower input o~ NOR gate 758 will cause that NOR gate to apply a "0" to conductor 764 and to the input of inverter 770 -- with consequent application of a "1" to conductor 776. The "0" on conductor 764 will not affect the output of NOR gate 290 because conductor 850 is applying a "1" to the lo~er input of that NOR gate; and that "0" wi~l not affect the output of NQR gate 294 because conductox 768 is applying a "1" to the lower input o~ that NOR gate. The resulting "1l' on conductor 776 will ~ 67.

~4~

not a~fect the output of NAND gate 232 because conductors 766 and 780 axe appl~ing "0's": to the ~iddle and lowex inputs o~ that NAND ~ate; ~nd that "1" will not af~ect the output of NOR gate 288 because co,nductor 768 is appl~in~ a ~'1" to the ~iddle input of 67A.

9L~47~6~

that NOR gate. The "1" on conductox 766 will not affect the output of NOR gate 292 because conductor 778 is applying a "1" to the middle input o~ that NOR gate;
but the "1" on conductor 776 will cause the ou~put o~ NOR gate 518 to chan~e ~xom "1~ to ~0~'. The inverter 520 will~.respond to that "0" to apply a "1" to conductor 522 and thus to the lower input o~ each of NOR ~ates 800 and 802 in Fig. 3C -- thereby isolating the outputs of F~QUENCY DETECTORS 792 and 794 ~rom the COUNT~RS
804 and 806.
Approximately six hundred and sixty-eight milliseconds after switch 156 closed, BINARY COUNTER
254 will again apply a "1" to conductor 258.
However, that "1l' will not a~ect the outputs o~ any o~ NAND gates 266, 268 and 272; because inverker 264 is applying a "0" to the upper input of NAND gate 266, because conductor 852 is applying a "0" to the lower input of NAND gate 268, and conductor 256 is applying a "0" to the upper input of NAND gate 272.
Appro~imately six hundred and eighty milli-seconds after the leading edge of the inserted bill caused actuator 158 to move far enough to close switch 156, the trailing edge o~ that bill permitted that actuator to move far enough in the opposite direction to permit that switch to re-open. The resulting "0"
on conductor 778 will not a~fect the output o~ NOR
gate 292 because conductor 776 is applying a "1" to the upper input o~ that NOR gate. The "0" on conductor 778 will back bias the diode 346 in the OVERLEVEL
~ENSING sub-block 296 o~ Fig. 7, and thereby keep "0"

~ 68.

on conductor 297 which is connected to the output of that sub-bIock. The "O" on conductor 778 will cause NAND ~ate 698 in BO~DE~ sub-block 516 in Fig. 4 to change "0": at the output thereof to a "1"; and it will thereby disable the elect~onic "latchl' constituted by that NAND gate and NAND gate 696, 68A.

-1~7~i6 and also will disable .the electronic '~latch" constituted by NOR gates 706 and 708. At this time, N~ND g~te 698 will have a "1~' at its lower input and a "0" at its upper input. NAND gate 700 will have a "0" at the lowex input thereof and a "1" ~t the upper :input thereof;
and NAND gate 696 will have "l~s" at both inputs there-of. Also, NOR gate 706 will have ~'0's" at both inputs thereo~, while NOR gate 708 will have "l's" at both inpuks thereof.
The "1" on conductor 766 will not change the output o~ NAND gate 23Z because conductor 780 is applying a "0" to the lower input o~ that NAND gate. That l'l"
will change the output of NAND gate 246 to a "0"; and NAND ~ate 248 will respond to that "0" to apply a "1"
to the reset terminal of BINARY COUNTER 254 -- thereby re-setting all of the output terminals of that BINARY
COUNTER to "q". The "1" on conductor 766 will not change the output of NOR gate 294 because conductor 768 is applying a "1" to the lower input of that NOR gate.
Approximately seven hundred milliseconds after the leading edge of the inserted bill caused actuator 164 to move far enough to close switch 162, the trailing edge of that bill will permit that actuator to move far enough in the opposite direction to permit that switch to re-open. m e resulting "1" at the lower input o~ NOR gate 760 will cause that NOR gate to apply a "0" to conduckor 768 and to the input of inverter 774 ~-with resultant application of a "1" to conductor 780~
The "0!' on conductor 768 will not change the output of NOR gate 288 because conductor 776 is applying a "1"

69.

~4~47~6 to the upper input of that NOR gate; and that "0"
will not change the output of NOR gate 294 because conductor 766 is applying a "1~' to the ~iddle input o~ that NOR gate.

69A.

~471Ç~

The resulting ~'l" on conductox 780 will be applied to the lower input of NAND gate 232 and will change the output of that NA~D gate from a "l~' to a "0", because conductors 776 and 766 are ap~lying "l's" to the upper and middle inputs o~ that N;~ND gate. The resulting ~IOl~ on condu~tor 234 will be applied to the lower input of NAND gate 328, but the output of that NAND gate will not change because NAND gate 326 is applying a "0" to the upper input of that NAND gate.
However, ,the 1l0ll at the input of inverter 238 will cause that inverter to apply a "l" to the upper input of NAND gate 240 and to the cathode of diode 2~5.
That NA~D gate will change the "1~' on conductor 242 to a "0"; and the resulting llo!l at the upper input of NAND gate 246 will cause that N~ND gate to apply a "l"
to the lower input of NAND gate 248. The latter NAND
gate will change the "1" at the output thereof, and hence at the reset input terminal of BINARY COUNTER 254, to a "0" -- thereby permitting that BINARY COUNTER to a~ain start counting the pulses from PULSE GEN~RATOR
252. The "0" whi,ch conductor 242 applies to the lower input of NAND gate 251 will not change the output of that NAND gate because the forward biasing of diode 245 had been maintaining a "0" at the upper lnput of that NAND gate. The "0" which conductor 242~ applies to the input of inverter 264 will cause that inverter to apply a "1" to the upper input of NAND gate 266;
but the output of that NAND gate will not change beca,use conductor 258 is applying a "0" to the lower input of 70.

~4~166 that NAND gate, the "0" which conductor 242 applies to the input of inverter 762 in Fig. 3B will cause that in-verter to apply a "1" to the upper inputs of NOR gates 758 and 760i but the outputs of those NOR gates will remain "0" because "l's" are applied to the lower inputs of those NOR gates. However, the "l's" which are applied to the upper inputs of NOR gates 758 a:nd 760 will keep any further closings of switches 146 and 162 from chang-ing the outputs of those NOR gates.
The "0" which conductor 242 applies to the lower input of NOR gate 840 in Fig. 3C will not change the out-put of that NOR gate, because NAND gate 836 is applying a "1" to the upper input of that NOR gate. However, the "0" which conductor 242 applies to the lower input of NOR
gate 838 will cause that NOR gate to apply a "1" to the input of RELAY DRIVER ~8~; and, thereupon, the relay coil 888 will respond to the "0" at the output of that RELAY
DRIVER to become energi2ed. At this time, the dispensing machine can start the dispensing of the desired change.
The "1" which inverter 238 applied to the cath-ode of diode 245 will back bias that diode; and thus will permit the source of regulated plus twelve volts D.C. to apply a "1" to the upper input of NAND gate 251. However, because of the "0" which conductor 242 is now applying to the lower input of that NAND gate, a "1" will continue to appear at the output of that NAND gate.
The "1" which conductor 780 applies to the lower input of NAND gate 270 will not be significant at this time because conductor 260 is applying a "0" to the upper i~tof `~ 7;L

71~

that N~NP gate. The "l" which conductor 780 applies to the middle input of NOR g~te 290 will not be'signi~i~
cant at this ~'ime because conductox 850 is applying a "1" to the lower input o~ that NOR gate. The "1"
which conductox 780 applies to the'lo~er input of NOR
gate 292 will not be'significant at this time because conductor~776 is applyin~ a ~'1" to the upper input o~
that NOR gate. The ~ which conductor 780 applies to the lowermost input o~ NOR gate 518 will not be sig-nificant at this time because conductor 776 is applying a "1" to the second lowermost input o~ that NOR gate.
Approximately sixty-seven milliseconds after switch 162 reopened, the BINARY COUNTER 254 will again appl~ a "1" to conductor 256; but ~hat "1" will not be e~fective at this time because NAND gate 272 has "0's" at the middle and lower inputs thereof. Approxi-mately one hundred and thirty-four milliseconds after switch 162 reopened, BINARY COUNTER 25~ will apply a "1" to conductor 258; but that "l" will not change the output of NAND gate 268 because "0'sl' appear at the middle and lower inputs oE tha~ NAND gate, and that "1"
will not change the output o~ NAND gate 272 because conductors 256 and 260 will cause "0's" to appear at the upper and lower inputs of that NAND gate. However, the application o~ that "1" to the lower input o~ NAND
gate 266 will coact with the "1" at the u~per~ut æ ~t ~AND gate to cause that N~ND gate to apply a "0" to conductor 278~ and hence to the second uppermost inputs o~ NA~D gates 728 and 730 in Fig. 3B. The resulting "l's"

~ / ~

~L~4~
on conductors 734 and 736 will app~ar at the reset inputs o~ .COUNT~RS ~804 and 806. Because COUNTER 806 did not rec'e.ive any clock pulses' ~.xo~ NOR gate`'802 as the one:dollar bill pass:ed thxough:the bill transport that COUNTER will alxeady be in.its~ reset state..
However,,the "1" on conduG~or 736"will reset COUNTER
804; and hence "0" will appear at all of the outputs thereof and thus at the input of inverter 819 and at both inputs of N~ND gate 834. The resulting "1" at the output o~ that NAND gate will be applied to the upper input of NOR gate 838 and to the input o~ inverter 8440 The resulting "0" at.the input o~ RELAY DRIVER 884 will cause that RELAY DRIVER to apply a ~ to the left-hand end of relay coil 888,,thereby de-energizing that relay coil. The "l" at the input of inverter 844 will cause that inverter to apply a "0" to the lower input of ~XCLUSIVE OR gate 84 6; and that ~XCLUSIV~ OR gate will change the "1" on conductor 850 back to "0" and will apply a "1" to the input of in~erter 848. That inverter will respond to that "1" to change the "0" on conductor 852 back to a "l".
The "0" which conductor 850 will apply to the lower input of NOR gate 290 will not a~fect the output of that NOR gate, because conductor 780 is applying a "l" to the middle input of that NOR gate~ However, the 1l 0 " which is applied to ~he lower inp~t o~ NAND
gate'240 will cause that NAND gate to chancJe the "0"
on cQnductor 242 bac~ to a "l". The "1" which that conductor will apply to the upper input o~ NAND gate 246 ~ill coact with ~7~L6~
the "1~ at the lowex input o~ that NAND gate ~o cause that NAND gate to appl~ a "0" to the lo~ex input of N~D gate, 248. The xesulting "1" at the output of the lattex NAND gate wi~l xeset BI~AR~ CO~T~R 254~ and will thereby cause that B~NARy COUNTE;R to appl~ ~'0's"
to all of conductors 256, 258 and 260; and that BI~ARY
COUNTER will remain in its reset conditio~ as lon~ as ~AND gate 248 applies a "1" to the reset input terminal thereo~. Conductor 258 will apply a "0" to the lower input of NAND gate 266, and the resulting "1" at the output of that NAND gate will apply a "1" to conductor 278 and to the second uppexmost inputs o~ NAND gates 728 and 730. Those NAND gates will then appl~ "0's~' to conductors 734 and 736, and thus to the reset input terminals of COUNTERS 804 and 806. The "1" which conductor 242 applies to the lower input of NAND gate 251 will coact with the "1" at the upper input of that NAND gate to cause that NAND gate to apply a "0" to the interconnected inputs of NAND gate 434 of the SPEED MAINTAINING sub-block 358 of Fig. 6. IThe resulting "1" at the base of transistor 438 will render that transistor co~ductive, and hence diode 444 will be forwarded biased to apply a "0" to the upper inputs of NAND gates 448 and 450. The resulting "1"
at the output of the latter NAND gate will forward bias transistor 466; and the consequent "0~' at the base of transistor 468 will rendex the latter tran~istor non-conducti~e. Thereupon,,txansistor 480 and then txansistox 482 will become non-conducti~e, and the motox 562 ~ill become de-energized. ~owever, the continued 74.

7~

ener~ization o~ t~at motox, ~ox one hundred and thixty-~our milli~econ~s a~tex s~itch 162 rebpened, made cextain that the inserted bill ~as ~o~ed wholly b-ey!ond the trailing ed~e~ o~ the platens 40 and 118 o~ the bill tran~port.
The fll" which conductox 242 applies to the input of in~erter 264 will cause that inverter to apply a "0" to the upper input of ~A~D gate 266; but that "O" will not change the output of that NA~D gate because "0" is being applied to the lower input o~ that NAND
gate. ~he ~ which conductor 242 applies to the input o~ inverter 762 in Fig. 3B will cause that inverter to apply "0's" to the upper inputs o~ NOR gates 758 and 760. However, those "0's" will not a~fect the outputs of thbse NOR gates because "l~s" are being applied to the lower inputs o~ those NOR gates. The "1" on conductor 242 will be applied to the lower inputs of NOR gates 838 and 840; but that "1" will not change the outputs o~ those NOR gates because "l's" are being applied to the upper inputs oE those NOR gates.
The "1" on conductor 852 will be applied to the lower input terminal o~ NAND gate 268; but that "1"
will not change the output of that NAND gate because conductors 258 and 260 are applying "0's" to the upper and middle inputs o~ that NAND gate. The l'l" on conductor 852 also will be applied to the lower input o~ NO~ gate 2B8, but that "1" ~ill not change the output of th~t NOR gate because conductor 776 is applying a "1" to the upper input o~ that NOR ~ate.

75.

7~
At this time, the paper currency validator will have completed one cycle of operation, and it will again be in its at-rest condition. During that cycle of operation, that paper currency validator responded to an authentic U.S. one dollar bill to energize the relay coil 888 in the dis-pensing machine for one hundred and thirty-four milliseconds, and it also moved that bill into the bill-receiving area, not shown, of that dispensing machine. Preferably, that area will include a bill stacker of the type disclosed and claimed in Gustav F. Erickson Canadian patent No.
1,019,709 for Escrow-Stacker For Paper Currency ; which was granted October 25, 1977.
For the purposes of this cletailed description of the operation of the paper currency validator, it was assumed that an authentic U.S.
one dollar bill had been introduced into the bill transport 30 of Fig. 1. If that bill had been an authentic U.S. five dollar bill~ the operation of the paper currency validator would have been identical, except that the FREQUENCY
DETECTO~ 792 would not have responded to the amplified pulses from ampliier 790; and hence 76.

~7~l66 COU~TER 804 would have remained inactive, and relay coil 888 would not have been ene~gized.
Instead, FREQUE~CY DETECTOR 7 94 would have responded to the amplified pulses from the amplifier 790 to repeatedly change ~he "1"
at the output thereof to "0", and t~hereby cause ~OR gate 802 to apply a succession of "l's" to the clock input of COU~TER 806. ~A~D
gate 836 would have reponded to the resulting - 76Ao ~ ~ - ~

47~
"1's." at output.~er~inals.2 and 3 of that COU~TER to apply a "0~ to the upper input o~ ~O~ ~,ate 840 and to the input o~ invextex 842, The "0" at the up~er input of th~t NOR ~ate would have coopexated with'the "0"
which conductox 242 was appl~in~ to the lower input o~ thak NOR gate to cause:that NOR gate to appl~ a "1"
to RELAY DRIVER 886 ~- thexeb~ causing that REhA~ DRIVER
to energize the relay coil`890 in the dispensing machine.
Invertex 842 would have responded to the "0" at the input thereof to cause EXC~uSIV~ OR gate 846 to appl~
a "1" to conductor 850 and, via inverter 848, a "0~' to conductox 852. As a result it can be seen that the insertion o~ an authentic U.S. five dollar bill into the bill transport 30, i~ the same manner in which the authentic U.~. one dollar bill was inserted into that bill transport, would cause the paper currency va7idator to experience a c~cle of operation during which it would energize the relay coil'890 ~or one hundred and thirty-four milliseconds and would: move the inserted bill to khe bill-receiving area o~ the dispensin~
machine. Thereafter, that paper currency validator would again assume its at-rest condition.
I~, instead of disposing an authentic U.S.
one'dollar bill so the bottom of the portrait of George ~ashington was close to the flange 142 on the cover 140, a patron ~exe to insert such a bill so the top o~ that portrait was close to that ~lange, the bordex whlch had been the trailing border in the priox detailed descxiption o~ the paper currency validator 77.

would now be the leading border of that bill. ~s a result,,the QO~E" which is int-ermediate that border and the poxtrait back~round will-engage the air gaps of the magnetic heads 208 and 210 be~ore the portrait backgxound can engage those air gaps. The magnetic ink in the "O~E" will cause the magnetic heads 208 and 210 and ampl-ifier 790 to develop amplified pulses that will cause transistor 682 in the BORDER sub-block 51~ of Fig. 4 to alternati~ely become conductive and non-conductive. The resulting succession of "0's" and "l's'"
at the upper input of NAND gate 700 will cause that N~ND gate to alternately forward bias and back bias diode 702; and hence capacikor 712 will remain charged throughout the time the "O~E" is in engagement with either of the air gaps of magnetic heads 208 and 210.
That time can be as -long as one hundred and thirty milli-seconds if the air gaps of both of those magnetic heads engage the projections at the free ends of the "E"
of the "ONE", but that time will' be shorter if either of those air gaps ails to do so. However, in any event, that time will be longer than sixty-five milli-seconds; and hence the portrait background will engage the air gap of the magnetic head 208 while the capacitor 712 is maintaining a "1" at the interconnected inputs of NOR gate 704 in that BORDER sub-block. Consequently, the diode 713 will be forward biased, and it will maintain a "0" at the upper input of NOR gate 706. That "0" will coact with the "0" at the lower input of that NOR ~ate to cause that NOR gate to continue to ~7~

appl~ a "1" to the conductor 517, and thus to the second uppermost input o~ NOR g~te 518. The lattex NOR gate will respond to that "1": to continue to apply a "0"
to the input o~ invexte~ 52`0;: and that in~erter will continue to apply a "1" to the lower inputs of NOR gates 800 and 802 ~ia conductor 522. Those NOR gates will apply continuous "0's" to tha clock inputs of -the COUNT~R$ 804 and 806, and thus will e~fectively isolate the FREQUENCY DETECTORS 792 and 794 from the COUNTERS
804 and 806. This means that even though the ~our quadrants o~ the portrait background on the bill w:ill cause the ma~netic heads 208 and 210 and ampli~ier 790 to develop amplified pulses, and even though those amplified pulses will cause the FREQUENCY DETECTOR 792 to appl~ ~our "0's" to the upper input of NDR gate 890, th~t NOR gate will be unable to apply "l's" to the clock input of COUNTER 804. As a result, that COUNT~R will continue to apply lloll to the upper and lower inputs o~ NAND gate 834, and that NAND gate will continue to apply a "1" to the upper input of NOR gate 838 and to the input of inverter 844. The consequent continued "0" at the input o~ RELAY DRIVER 884 Will cause that RELAY DRIVER to prevent energization o~ the relay coil 888 in the dispensing machine; and the con-sequent "0" at the lowerinæut of ~XCLUSIVE OR gate 846 will cause that EXGLUSIVE OR gate to continue to main-tain a "0" on conductor 850 and to cause inverter 848 to continue to maintain a "1" on conductor 852.

79.

s The NAND gate 268 in the TIMER LOGIC bl.ock 262 will respond to the "1" on conductor 852 and to: the "lls" whic~ will appear at the upper. and middle:inputs o~ that NAND gate, approximateL~ six hundred and sixty-eight milliseconds a~ter s~itch 156. c:losed, to change the output.thereof from a "1" to a lloll. The resulting "O" at the uppermost input of NAND gate ~26 will de~elop a "1" at t~e output of that NAND gate, and thus at the upper input o~ NAND gate 328 and also at the input o~ RELA~ DRIVER 330. The resulting "0" at the output of that RELAY DRIVER will be applied by conductor 332 to relay coil 490 in the MOTOR AND RELAY sub-block 360 of ~ig. 8 -- causing energization of that relay coil. Thereupon, the movable relay contacts 492 and 494 will be shited rom the "~orward" positions shown in Fig. 8 to their right-hand "re~erse" positions; and ~ery promptly, the motor ~62 will cause the lower "runs"
belt 198 and o~ its counterpart to reverse direction and to start moving the bill back toward the front of the bill transport 30.
The "1" which NAND gate 326 applies to the upper input of NAND gate 328 will coact with the "l"
which conductor 234 is applying to the lower input of that NAND gate to cause that NAND gate to apply a "0" to conductor 334 -- and hence to the second lower-most inputs of NAND gates-728 and-730. The resulting "l's." on conductors 734 and 736 ~ill be applied to the res:et input terminals-o~ CO~NTERS 804 and 806 -- thereby precluding energization of either of the relay coils 888 and 890.

~ 80.

` - ~

7~
The "0" ~t the output of NAND ~ate 328 will also be applied to the lower inpuk of ~AND ~ate 326;
and hence the latter NAND gate will continue to supply a "1" to the: uppex input of NAND ~ate 328 even a~ter the "0" at:the output o~ NANP gate 268 changes back to a "1". ~s a result, NA~D gates 326 and 328 will act as an electronic "latch" *hat will apply a continuous "1" to the input of RELAY DRIVER 330 and that will apply a continuous "0" to the second lowermost inputs of NAND
gates 728 and 730. That electronic "latch" w~ll continue to apply that continuous "1" and that continuous "0"
until the power to the paper currency validator is interrupted or until all of the switches 146, 156 and 162 have been permitted to re-open and thereby cause NAND gate 232 to re-apply a "O" to conductor 234.

80A.

~47~
The motor 562 will continue to drive the lowex "xuns" o~ the belt 198 and o~ its countexpaxt in the "reverse"~ dixection until the bill 212 successi~el~ moves beyond the actuator 164 o~ switch 162 to permit that switch to xeopen, beyond the actu~tor 158 o~ switch 156 to permit that switch to reopen, and beyond the actuator 148 of switch 146 to permit t:hat switch to reopen. As the switch 156 reopens, conductor 766 will again apply a "1" to the lower input of NAND gate 246; , and that "1" will coact with the l'l" which conductor 242 is applying to the upper input of that NAND ~ate to cause that NAND gate to apply a "0" to the lower inp~t o~ D gate 248. The resulting "1" at the reset input terminal o BINARY COUNTER 254 will cause "0's"
to appear on conductors 256, 258 and 260. The "1"
which conductor 766 applies to the middle input o~
NOR gate 294 will not be signi~icant at this time because conductor 764 will be applying a "1" to the upper input of that NOR gate; and the "1" which conductor 766 applies to the middle input of NAND gate 232 will not be significant at this time because conductor 776 will be applying a "0" to the upper input of that NAND
gate. The "0" which conductor 778 applies to the OVERLEVEL SENSING block 296 will not be significant at this time, and the "0" which that conductor applies to the middle input of NOR gate 292 will not be sig-ni~icant at this time~ but the "0" which that conductor applies to the BORDER sub-block 516 will keep capacitor 712 char~ed -- and thus will keep a "1" on conductor 517.

81.

6~
As the swi.tch 146 xeopens, conductor 764 will apply "0's" to the upper inputs of NOR gates 290 and 294,,but.the outp~ts o~ those NOR gates ~ill be unchan~ed. Also, the conductor 776 wi.ll apply a "1"
to the uppex inputs of' NOR ga-tes 288 and 2,92 and to the second lowermost :input of NOR gate 518,.hut.the outputs of those NOR gates will remain unchang.ed.
However, NAND gate 232.will respond to the "1" on conductor 776 to apply a "0". to the lower input of NAND gate 328 and to the input of inverter 238. NAND
gate 328 will apply a "1" to the lowermost input o~
NAND gate 326 and, via conductor 334, will apply a ~'1" to the second lowermost inputs of NAND gates 728 and 730. Thexeupon, those NAND gates will appl~ "0's"
to conductors 734 and 736 and thus to the re-set inputs of COUNTERS 804 and 806. The inverter 238 will apply a "1" to the upper input of NAND gate 240, and that NAND gate will continue to apply a "1" to conductor 242.
The "1" which inverter 238 applies to the cathode of diode 245 will back bias that diode, and the source of regulated plus twelve volts D.C. will start charging the capacitor 249. After a few milliseconds, that capacitor will have charged to a value at whic~ a "1"
will appear at the upper input of NAND gate 251; and that "1" will coact with the "1" which conductor 242 is applying to the lower input of that NAND gate to cause that NAND gate to apply a "0" to the interconnected inputs of N~NP gate 434 in the ~PE~D M~INTAININ~ sub-block 358 o~ Fig. 6. The resulting "1" at the 82.

~4~66 output o~ that NAND gate will xender transistor 438 conductive, and will thereby ~orward bias diode 444 to apply a "0" to the upper inputs of NAND gates 448 and 450. The resulting "1" at the base of transistor 466 will cause transistors 468, 480 and 482 to become non-conductive -- thereby causing the motor 562 to come to rest.
All of this means that the presence of a number of magnetic ink lires intermediate the leading border and the portrait background of a bill will reverse the motor 562 and will prevent energization of either of the relay coils 888 and 890. Consequently, the inserted bill will be returned to the patron who inserked it, and the dispensing machine will be kept from dispensing change. In the preferred embodiment of the present invention, instructions are suitably affixed to the upper surface of the platform to urge patrons to dispose bills with the black-ink face up and with the bottom of the portrait close to the flange 142 on the cover 140.
If an authentic U.S. five dollar bill were`to be inserted in the bi~l transport 30 so the "FI~E", which is located between the leading border and the portrait, would engage the air gaps o~ the magnetic heads 206 and 208 before the portrait background could engage those air gaps, the motor 562 would reverse and the relay coils 888 and 890 would remain un-energized.
Specifically, the magnetic heads 208 and 210 and amplifier 730 would respond to the "FI~E" on the ~ive dollar bill to 83.

~47~;6 develop amplified pulses which would cause the "BORD~R"
sub-block 516 of Fig. 4 to keep capacitor 712 charged until the "F" of the "FIVE" moved be~ond the air gap of the magnetic head 210. At such time, the portrait back-ground would be so close to the air gap of the magnetic head 208 that there would not be enough time to permit capacitor 712 to discharge and for capacitor 716 to charge before that portrait background engaged that magnetic head. The resulting continued "1" on conductor 517 would cause NOR gate 518 and inverter 520 to apply a "1" to NOR gates 800 and 802; and those NOR gates would effectively isolate the FREQUENCY DETECTORS 792 and 794 from the COUNTERS 80~ and 806. As a result, the NAND
gate 836 would apply a "1" to the upper input o~ NOR
gate 840 and to the input o inverter 842; and hence relay coil 890 would remain un-energized, and conductor 852 would apply a "1" to the lower input of NAND gate 268. Approximately six hundred and sixty-eight milli-seconds after switch 156 was closed, conductors 258 and 260 would appl~ "l's" to the upper and middle inputs of NAND gate 268; and, thereupon, that NAND gate would change the output thereof from "1" to "0", and NAND
gate 326 would respond to the resulting "0" at the upper input thereof to cause RELAY DRIVER 330 and the MOTOR
AND ~ELAY sub-block 360 to reverse the motor 562. The overall result is that the five dollar bill would be moved back out of the bill transport 30, and the relay coils 888 and 890 in the dispensing machine would remain un-energized.

84.

As indicated by the two immediately-preceding explanations of the operation of the currency validator by bills which have the "ONE" or "FIVE" thereof disposed ahead of the portrait background, whenever a "0" is applied to any of the inputs of NAND gate 326, the RELAY DRIVER sub-block 330 and the MOTOR AND RELAY
sub-block 360 will reverse the motor 562. Also, the NAND gate 328 will cause NAND gates 728 and 730 to reset the COUNTERS 804 and 806; and the re-setting of ! 10 those COUNTERS Will make certain that relay coils 888 and 890 remain un-energized. All of this means th~t if a "0" is applied to any of the inputs of NAND gate 326, the inser~ed bill will be returned to the patron who inserted it and the dispensing machine will not dispense change.
In an alternate embodiment of the paper currency validator provided by the present invention, a capacitor 892 is connected between ground and the junction of resistor 684 and the base of transistor 682 in the BORDER sub-block 516, all as shown by Fig.
11. Tha~ capacitor acts as an integrator; and it reduces the amplitudes of the ampliied pu~ses which conductor 791 apply to the base of that transistor.
The reduction in the amplitude of the amplified pulses which correspond to the "ONE", that is located between the portrait and the leading border of an authentic U.S.
one dollar bill, will keep those amplified pulses from rendering conductive the transistor 682 in the BORDER
sub-block 516. In permitting transistor 682 to remain non-conductive, that capacitor enables that alternate form of the 85.

7~
paper currency ~alidator to accept authentic U.S. one dollar bills whether the bottom or the top of the portrait of George ~ashington is close to the flange 142 on the cover 140. Consequently, that capacitor permits "two way insertion" of one dollar bills.
Similarly, the capacitor 892 will reduce the amplitudes of the amplified pulses which correspond to the "FIVE" that is located between the portrai~
and the leading border of an authentic U.S. ~ive dollar bill r and thus will keep those amplified pulses rom rendering conductive the transistor 682 in the BORDER
sub-block 516. In permitting transistor 682 to remain non-conductive, that capacitor enables that alternate ~orm of the paper currency validator to accept authentic U.S. five dollar bills whether the bottom or the top of the portrait of Abraham Lincoln is close to the flange 142 on the cover 1~0. Consequently, that capacito.r permits "two way insertion."
If a person were to attempt to make a spurious one dollar bill, by using a copying machine which utilizes metallic particles in producing images, by using magnetic ink to print a simulation of a bill, or by using magnetic ink to draw a simulation of a bill, that spurious bill would be rejected; because the particles on that simulated bill would have magnetic proper~ies that were far more intense than are the magnetic properties o~ the black ink on an authentic U.S. bill. Specifically, as the leading edge o~ the leading border on that 86.

simulated bill engaged the air gap of the magnetic head 208, that magnetic head would generate pulses which, when ampli~ied by amplifier 790, woulcl render the tran-sistor 338 in the OVERLEVEL SENSING sub-block 296 of Fig. 7 conductive. The resulting voltage drop across resistor 342 would forward bias transistor 346, and thereby render that transistor conductive. The resulting "1" at the collector of that transistor would be applied by conductors 297 and 284 to the upper input of NOR gate 295; and the resulting "0" at the output of that NOR gate would be applied to the cathode of diode 320. The consequent forward biasing of that diode would cause a "0" to appear at the second lower-most input o NAND gate 326 -- with resulting reversal of motor 5~2 and with resulting re-setting of COUNTERS
804 and 806, all as pointed out hereinbefore. This means that the instant the magnetic head 208 engages lines which contain substantially more magnetic properties than do the lines in an authentic U.S. dollar bill, the OVERhEVEL SENSING sub-block 296 will effect reversal of the motor 562 and will prevent any and all dispensing of change.
Similarly, if a person were to attempt to make a spurious five dollar bill, by using a copying machine which utilizes metallic particles in producing images, by using magnetic ink to print a simulation of a bill, or by using magnetic ink to draw a simulation of a bill, that spurious bill would be rejected; because the particles on that simulated bill would have magnetic properties that were far more intense than are the magnetic ~ 87.

~47~61~
properties o~ the black ink on an authentic U.S.
bill. Specifically, ~s the leading edge of the leading border on that simulated 87A.

bill engaged the air gap of the magnetic head 208, the OVERLEVEL SENSING sub-block 296 would effect reversal o~ the motor 562 and would prevent any and all dis-pensing of change.
If a person who made such a simulation of a bill was able to learn that the intensity of the magnetic ~aterial in the leading border of the bill was causing rejection of that simulated billj that person might try to decrease the intensity of the magnetic material in that leading border by use of an eraserj by use of water, by use of soap, or by use of some other material -removing material. Even if that person were able to reduce the intensity of the magnetic material in that leading border to a value which enabled the corresponding amplified pulses to be below the threshold level oE
transistor 338 in OVERLEVEL SENSING sub-block 296 and yet be above the threshold levels of transistor 682 in Fig. 11 and of the phase locked loops in FREQUENCY
DETECTORS 792 and 794, the paper currency validator of the present invention would still reject that simulated bill. Specifically, the magnetic material in the succeeding lines on the simulated bill would cause the magnetic head 208 to generate pulses which, when amplified by the amplifier 790, would render con-ductive the transistor 338 in the OVERLEVEL S~NSING
sub-block 296 -- with consequent reversal of the motor and with consequent resetting of the COUNTERS 804 and 806. That re~ersal and that re-setting would occur whether those succeeding lines were the ~ertical grid lines in the portrait background, were the lines in the "ONE" or "FIVE", or any other lines on the simulated bill.

88.

1~47~L~ii6 Even i~ a pe~son who used magnetic material to make a simulation o:E ~ bill was able to reduce the intensity of al~ of that material to a ~alue which enabled the corresponding a~plified pulses to be below the threshold level of transistor 338 in OVERLEVEL
SENSING sub-block 296 and yet be above the threshold levels of transistor 682 in Fig. 11 and of the phase locked loops in FREQUENCY DETECTORS 792 and 794, the paper currency validator of the present invention would reject that simulated bill i~ a "ONE" or "FIVE" of that simulated bill engaged the air gaps of the magnetic heads 208 and 210 before the portrait background on that simulated bill engaged those air gaps. Specifically at the time the "ONE" or the "FIVE" on that simulated bill engaged the air gap of the magnetic head 208, either the capacitor 712 in the BORDER sub-block 516 would still have a charge large enough to enable it to apply a "1" to the interconnected inputs of NOR gate 704 or the capacitor 716 would have little or no charge and thus would be applying a "0" to the upper input of NOR gate 706. In either event, conductor 517 would be applying a "1" to the second uppermost input of NOR
gate 518, and inverter 520 would be applying a "1" to the lower inputs of NOR gates 800 and 802 -- thereby keeping the COUNTERS 804 and 806 from receiving pulses from the FREQUENCY D:ETECTORS 792 and 794. The resulting continued "l's" at the upper inputs of NOR gates 838 and 840 would keep the relay coils 888 and 890 in the dispensing machine un~energized; and the resulting 89.

~)47~6E;

continued "lls" at the inputs of in~erters 842 and 844 would cause ~XCLUSIVE OR gate 846 to continue to maintain a "1~' on conductox 852 ~ with consequent reversal of the motor 562 approximately six hundred and si~ty-eight milliseconds a~ter switch 156 closed. In -this way, the BORDER sub-block 516 will effect the rejection of a simulated bill if that simulated bill has magnetic ink lines spaced ~cross the area intermediate the leading border and the portrait -- even if the intensity o~ all of the magnetic material on that simulated bill is comparable to that of the material in the magnetic ink used to engrave authentic U.S. bills, and regaxdless of the source o~ or reason for those magnetic ink lines.
If a person could insert an authentic U.S.
bill in the ~ill transport 30 and somehow keep the leading edge of that bill from moving the actuator 164 far enough to close the switch 162, the paper currency validator would reverse the motor 562 and would keep the relay coils 888 and 890 un-energized. In such event, the operation of that paper currency validator could, from the time the switch 146 was closed until approximately three hundred milliseconds after the switch 156 was closed, be identical to the normal initial operation of that paper currency validator.
However, approximately three hundred milliseconds after the switch 156 was closed, the conductor 780 would not apply a "0" to the lower input of NAND gate 270 and~
instead, would continue to apply a "1~' to that lower input. Moreover, that conductor would continue -to apply that ~'1" to that lower input until approximately five ~47~6 hundred and thixty-five milliseconds a~tex switch 156 was closed. At that time, the BINARY COUNT~R 254 would apply a "1" to co~ductor 260~ and thus to the upper input of NAND gate 270, and that NA~D gate would apply a ~'0~' to the second uppermost input of' NAND gate 326.
Thereupon, as e~plained hereinbefore, the motor 562 would start operating in the reverse direction and COUNTERS 804 and 806 would be re-set.
If a person could insert an authentic U.S.
bill in the bill transport 30 and somehow keep the trailing edge of that bill from freeing the actuator 158 of the switch 156, the paper currency validator would reverse the motor 56Z and would keep the relay coils 888 and 890 de-energized. In such event, the operation o~ that paper currency validator could, from the time the switch 146 was closed until approximately six hundred and eighty milliseconds after the switch 156 was closed, be identical to the normal initial and intermediate operation of that paper currency validator.
At such time, the switch 156 should be open; because an authentic bill is six and one-eighth inches long, and it should have moved the trailing edge thereof at least half an inch beyond the actuator 158 of that switch. However, if that switch was still closed, approximately six hundred and eighty milliseconds after that switch was closed, the conductor 766 would not apply a "1" to the lower input of NAND gate 246.
Instead, that conductor would continue to apply a "0"
to that lower input, and hence NAND gate 246 would cause NAND gate 24~ to continue to apply a 110l7 to the reset ~ 91.

~47~L~;6 input texminal o~ BINAR~ COUNT~R 254 -- thexeb~ per-mi~tin~ that B~AR~ COU~T~R~:to continue counting t~e pulses from the PUL~E GEN~RATOR 252. Approximately seven hundred and thirty-~ive milliseconds after switch 156 ~as closed, that 91~.

.

~Q~
BINARY COUNTER would apply "l's" to conductors 256, 258 and 260~ and thus to all of the inputs of NAND
gate 272. The resulting ~'0" at the output of that N~ND
~ate ~ould cause inverter 274 to forwclrd bias diode 276 --with consequent application, via conductor 284, of a "1"
to the uppermost input of NOR gate 295. The "0" which that NOR gate would apply to the cathode of diode 320 would forward bias ~hat diode, and thereby cause a "O" to appear at the second lowermost input of NAND
gate 322 -- with consequent reversal of motor 562 and with consequent resetting o~ COUNT~RS 804 and 806.
If a person inserted an authentic U.S. bill with ~he green-ink face thereof up, if a person inserted a Xerox copy of the black-ink ace of an authentic U.S. bill, or if a person inserted any other object which did not have magnetic ink on the upper face thereof, the paper currency validator would reverse the motor 562 and would keep the relay coils 888 and 890 un-energized. In such event, the operation of that paper currency validator could, from the time the switch 146 was closed until approximately one hundred and forty milliseconds after the switch 156 was closed, be iclenti-cal to the normal initial operation of that paper currency validator. However, approximately one hundred and forty milliseconds after the switch 156 was closed, the magnetic head 708 and the amplifier 790 would not supply amplified pulses to the base of transistor 682 in the ~ORDER sub-block 5I6; and hence that BORDER
sub-block would continue, via conductor 517, to apply a "1~ to the 92.

second uppe~most input of NOR gate 518. The resultin~
"0" at the outpu~ o~ th~-t NOR ~ate would cause inverter 520, ~ia conductor 522, to apply ~l's~' to the lower inputs of NOR gates 800 and 802, thereby ef~ectively isol~ting the clock input terminals o~ COUNTERS 804 and 806 from the outputs of the FREQU:ENCY DETECTORS
792 and 794., Subsequently, when the leading and trailing edges of the upper portion of the portrait background en~aged the air gap of the magnetic head 208, that magnetic head would not develop any pulses.
Similarly, when the leading and trailing edges of the lower portion o~ that portrait background engayed the air gap of the magnetic head 210, that magnetic head would not develop any pulses. This means that neither o~ the FREQUENCY DETECTORS 792 and 794 would apply a "0" to the upper input of the adjacent NOR
gate. For these various reasons, the COUNTERS 804 and`806 would continue to apply "0's" to all of the output terminals thereof; and NAND gates 834 and 836 would coact with NOR gates 838 and 840 and with REL~
DRIVERS 884 and 886 to keep the relay coils 888 and 890 un-energized. Also, those NAND gates would coact with inverters 844 and 842 and with EXCLUSIVE OR gate 846 to continue to maintain a "0" on conductor 8S0, and thus at the lower input of NOR gate 290, and to continue to maintain a "l" on conductor 852, and thus at the lower input of NAN~,~ate268. This means that when switch 146 re-opened -- appro~imately seven hundred milliseconds after that switch was closed -- conductor 764 would be applying a "0" to the upper input o~ NOR gate 290, ~47~66 conductor 780 would be applying a "0l' to the ~iddle input of that NOR gate, and conductor 850 would be applying a "0" to the lowe~ input of that NOR gate.
Thereupon, that NOR gate would apply a "1" to the anode of diode 300; and the resulting orward biasing of that diode would cause conductor 284 to apply a "1" to the uppex input of NOR gate 295. The '-01l which the latter NOR gate would apply to the cathode of diode 320 would forward bias that diode and permit a "0" to appear at the second lowermost input of NAND gate 326 --with consequent reversal of the motor 572, all as ex-plained hereinbefore.
If the re-opening of switch 146 happened to occur more than six hundred and sixty-eight milliseconds aEter the switch 156 was closed, -the BIN~RY COUNTER 254 would, via conductors 258 and 260, apply "l's" to the upper and middle inputs of NAND gate 268. Those "l's" would coact with the "1" which conductor 852 would be applying to the lower output of that NAND gate to cause that NAND gate to apply a "0" to conductor 780, and thus to the upper input of NAND gate 326. Thereupon, the latter NAND gate would cause the motor 562 to reverse, all as explained hereinbefore.
If a person were to insert a long object into the bill transport 30 and close the switch 162, the paper currency validator would start the motor 562 operating in the reverse direction and would keep the relay coils 888 and 890 unenergi2ed Speci~ically, as that switch was closed, conductor 780 would apply a "0" to the middle input of NOR gate 290;

94.

IL7:166 and that "0" would coact with the "0~ which conductor 764 would be applying to the uppex input of that NOR
gate and with the "0" which conductor 850 would be appl~ing to the lower input of that NOR gate to cause that NOR ~ate to apply a "1" to the anode of diode 300.
The resulting forward biasing of that diode would cause conductor 284 to apply a "1" to the upper input of NOR
gate 295; and the "0" which that NOR gate would apply to the cathode o~ diode 320 would forward bias that diode and permit a "0" to appear at the second lowermost input of NAND gate 326 -- with consequent re-setting of the COUNTERS 804 and 806 with consequent shifting of the relay contacts 492 and 494 in the MOTOR AND
R~LA~ sub-block 360 o~ Fig. 8 to their "reverse" positions.
This means that when the motor 562 started, as it would when switch 162 was closed, that motor would start operating in the reverse direction.
If a person were to insert a U.S. authentic bill in the bill transport 30, and then immediately thereafter insert a further U.S. authentic bill in that~
bill transport, the paper currency validator would reject both of those bills. Specifically, if the first bill was holding switch 162 closed, but had moved far enough inwardly of the bill transport 30 to permit switch 156 to re-open, the closing of switch 146 by the leading edge of the second bill would cause conductor 776 to apply a " O 1I to the upper input o~ NOR gate 292. At that time, conductox 778 would be applying a 1l0~l to the middle input o~ that NOR gate, and conductor 780 would be applying a "0~' to the 95.

7~
lower input of that NOR gate; and hence that NOR gate would apply a "l" to the middle input of NOR gate 295.
The resulting "0" at the output of the latter NOR gate would forward bias diode 320 and thereby cause a "0" to appear at the second lowermost input of NAND gate 326.
Thereupon, that NAND gate would reverse the motor 562 and also would re-set the COUNTERS 804 and 806, all as explained hereinbefore.
In making certain that two authentic UOS~ bills which were inserted in the bill transport 30 in rapid suc-cession would be rejected, the switches 146, 156 and 162 and the NOR gate 292 also make certain that the motor 562 would reverse and that the COUNTERS 804 and 806 would be re-set in the event a tape, a ribbon, or other "tail", that would move actuator 148 but not actuator 158, was attached to an authentic U.S. bill. Specifically, as the belt 198 and its counterpart moved such a bill inward-ly of the bill transport 30, that bill would successively close switches 146, 156 and 162; and that "tail" would continue to hold switch 146 closed as the trailing edge of the bill moved beyond the actuator 158 and permitted switch 156 to re-open. At such time, the conductors 776, 778 and 780 would be applying "0's" to the upper, middle and lower inputs of NOR gate 292; and that NOR gate would be applying a "1" to the middle input of NOR gate 29S.
The resulting "0" at the output of the latter NOR gate would forward bias diode 320 and ~hereby cause a "0" to appear at the second lowermost input of NAND gate 326 --with consequent reversal of motor 562 and with consequent re-setting of COUNTERS 804 and 806.

96.

~7~
If a pexson were to insext just a short porkion o~ the:len~th o~ an authentic U,~. bill, or were to insert any ob~ect th~t had a con~iguration which would cause it to hold switch 156 closed ~t a time when switches 146 and 162 ~ere open, the paper currency validator would re~erse the motor 562 and would reset the COUNTERS 804 and 806. Specifically, such a portion of a bill ox such an object would permit switch 146 to apply a "0" to the.upper input of NOR gate 294 ~ia ~OR gate 758 and conductor 764, switch 1,56 would apply "0" to the middle input of NOR gate 294 via conductor 766, and switch 162 would apply a "0" to the lower input o~ that NOR gate via NOR gate 760 and conductox 768.
Consequently, NOR gate 294 would apply a "1" to the lower input of NOR gate 295; and the latter NOR gate would apply a "0" to the cathode of diode 320. The resulting forward biasing of that diode would apply a fio 1l to the second lowermost input of NAND gate 326, and thus would effect reversal of the motor 562 and the re-setting of COUNTERS 804 and 806, all as described hereinbefore.
Various configurations of an object could cause that object to permit switches 146 and 162 to be open when switch 158 was closed. For example, a short object of almost any configuration could keep switch 15~
closed while pexmitti~ switches 146 and 162 to be open, a long object with notches in the leadin~ and trailing edges thereo~ could pexmit switches 146 and 162 to be open while:the s~itch 156 was closed, and a long object with an opening in xegister with the actuator 148 97.

~LOgL7~
o~ switch 146 could close switch 1~6 while switches 146 and 1.62 were open. However, regardless of the con~iguration o~ the ob~ect which was inserted in the bill transport 30 t if that object closed switch 156 when s~itches 146 and 162 wexe open, the paper currency ~a~idator would reverse the motor 562 and ~ould re-set the COUNTERS 804 and 806.
The NOR gate 294 and the switch 156 will effect the reversal o~ motor 562 and the re-setting of COUNTERS
804 and 806 in the event an authentic U.S. bill is equipped with a tape, ribbon or other "tail" that will engage the actuator 158 of that switch but will not en-gage either o~ the actuators of switches 146 and 162.
Specificall~, as such a tail-equipped bill passed in-wardly through the bill transport 30, that bill would successively close switches 146, 156 and 162, would pass beyond the actuator 148 to permit the switch 146 to xe-open, would pass beyond the actuator 158, and would pass beyond the actuator 164 to permit the switch 162 to re-open. However, the "tail" would not permit the actuator 158 to move far enough to permit the switch 156 to re-open, and at such time, conductors 764, 766 and 768 would be applying "0's" to the upper, middle and lower inputs of NOR gate 294. The resulting "1"
at the lower input of NOR gate 295 would cause that NOR
~ate to forward bias diode 320, and would thereb~
cause a "0" to appear at the second lowermost ~nput of NAND ~ate 326. At such time, the~motor 562 would reverse and the COUNTERS 804 and 806 would be re-set, all as explained hereinbefore.

98.

~47~6 I~ a pexson ~ade or obtained a simulated bill which was similax, or even identical to an authentic U.S. bill ln all respects other than the spacing between the leadin~ edges of the vertical grid lines in the portrait backgxound, the papex currency validator of the present invention would reject that simulated bill.
The bill transport 30 would respond to the insertion o~ that simulated bill to start the motor 562; and, until the leading half of the upper portion o~ the portrait background of the simulated bill engaged the air gap of the m~gnetic head 208, the operation of the paper curxency validator would be the same as the normal operation oE that paper currency validator. However, the signals which the leading and trailing halves of the upper portion of the portrait background on the simulated bill would cause the magnetic head 208 to develop, and the signals which the leading and trailing hal~es of the lower portion of that portrait background would cause the magnetic head 210 to develop, would not have the ~requencies to which the phase locked loops o~ the ~REQUENCY DETECTORS 792 and 794 will respond;
and hence the COUNTERS 804 and 806 would not receive "l's" at the clock input terminals thereof. As a result, those COUNTERS would leave the relay coils 8~8 and 890 un-energized, and also would leave the "0" on conductor 850 and t~e "1" on conductor 852. This means that when switch 146 re-opened -- appxoximately seven hundred ~illiseconds a~tex that switch ~as closed -- conductor 764 would be applying a "0" to the upper input of NOR gate 290, conductor 780 would be applying a "0" to the middle input of that NOR gate, 99.

47~6 and conductor 850 would be appl~in~ a "0" to the lower input o~ that NOR gate. Thexeupon/ t~at ~OR ~ate would apply a "1": to the'anode o~ diode 30'0; and the xesulting ~oxwaxd biasin~ of that diode would cause conductor 284 to apply a "1" to the upper input of NOR gate 295.
The "0" which the latter NOR gate would apply to the cathode of diode 320 would forwaxd bias that diode and permit a "0" to appear at the second lowermost input o~ NAND gate 326 -- with consequent reversal o~ the motor 572, all as explained hereinbe~ore.
If the re-opening of switch 146 happened to occur more than six hundred and sixty-eight milliseconds ater the switch 156 was closed, the BINARY COUNTER 254 would, via conductors 258 and 260, apply 'll's'l to the upper and middle inputs of NAND gate 268. Those Ill's would coact with the lll" which conductor 852 would be applying to the lower output of that NAND gate to cause that NAND gate to apply a 1l 0 1I to conductor 780, and thus to the upper input of NAND gate 326. Thereupon, the latter NAND gate would cause the motor 562 to reverse, all as explained hereinbefore.
To provide a high rejection rate for simulated bills, it is necessary that the bandpasses of the phase locked loops in the FREQUENCY DETECTORS 792 and 794 be narrow and fixed; and, as indicated herein, the widths of those bandpasses axe only plus and minus five peXcent. Also, it is necessary that the speed of the motor 562 be maintained within narrow, ~ixed limits;
and the SPEEP AD3USTI~G sub-block 356 o~ Fig. 5 main-tains that speed within such limits.

100 .

~47~616 That SPEED ADJUSTING sub-block can include any one of a number of speed controlling systems which can pxoYide close control of the speed of an electric motor.
The A. C. generator 560 in the MOTOR AND RELAY sub-block 360 o ~ig. 8 will supply signals to the full-wave bridge rectifier 376 in the SPEED AD~USTIMG sub-block 356 via conductors 368 and 370; and those sign.als will have the form of a periodic wave form that has an integral number of periods for each revolution of the shaft of the motor 562. The full--wave bridge rectifier 376 will rectify those signals and will apply rectifiecl pulses to the base of transistor 378; and that transistor will act as a high gain amplifier and will respond to those rectified pulses to be driven hard into saturation. Consequently, that transistor will develop steep-sided flat-bottomed nega-tive going pulses at the collector thereof; and, because rectifier 376 is a ull-wave rectifier, the frequency of those negative-going pulses will be double the frequency of the signals supplied by conductors 368 and 370.
The diode 389 will by-pass to the source of regulated plus twelve volts any positive-going output from the transistor 378; and the capacitor 386 and the resistor 390 will differentiate the negative-going pulses from that transistor. The resulting differentiatecl pulses will be applied to pin 2 of the MONOSTABLE MULTIVIBRATOR
392; and that MONOSTABLE MULTIVIBRATOR will respond '~ ~ 101.

:~47~6~

to those dif~erentiated pulses to provide output pulses at pin 3 thereof. Those output pulses will have the same ~requency as the differentiated pulses which are applied to pin 2, but each of those output pulses will ha~e the same precisely-fi~ed duration. The ~ONOST~BLE
MULTIV~BRATOR 392 is set so the durations of those output pulses will always keep the duty cycle of those pulses less than one hundred percent -- even when the motor 562 is opexating at its maximum speed. In this way, that MONO5TABLE ~U~TIVIBRATOR causes the tran-sistox 414 to xespond to the frequency of the output pulses at pin 3 rather than to any harmonics oE that frequency.
The resistor 412 applies the output pulses at pin 3 of the MONOSTABLE MULTIVIBRATOR 392 to the base of transistor 414, and it acts to limit the base-emitter current of that transistor to a safe value.
That transistor operates as a saturated switch; and, in the preferred embodiment of the present invention, that transistor has an e~cceedingly low saturation voltage. Resistors 400 and 402 constitute a voltage divider which is connected between ground and the source of regulated twelve volts; and transistor 414 will selectively permit that voltage divider to apply the voltage at the junction between those resistors to the non-inverting input of the operational amplifier 420. Specifically, whenever that transistor is non-conductive, the voltage at the junction between resistors 400 and 402 will tend to be applied to that non--inverting input; but whenever that transistor is con-ductive gxound voltage will tend to appear at,that 102.

3 ~7~66 non-inverting input. Resistor 416 and capacitor 418 tend to provide an averaging action; and that averaging will substantially average the changing voltages at the col-lector of transistor 414 to apply a voltage to the non-inverting input of operational amplifier 420 which is pro-portional to the duty cycle ofthe OUtpllt pulses at pin 3 of MONOSTABLE MULTIVIBRATOR 392, and thus is proportional to the frequency of the pulses which the signals from the A.C. generator 560 cause the full-wave bridge rectifier 376 and the transistor 378 to apply to pin 2 of that MONO-STABLE MULTIVIBRATOR. The transistor 414 and the resis-tors 400 and 402 constitute one side of a bridge circuit;
and the other side of that bridge circuit is constituted by resistors 404 and 406 and potentiometer 408. That bridge circuit is connected between ground and the source of regulated twelve volts, and hence the voltage at any given point in either side of that bridge circuit will vary with variations in the twelve volts. However, any voltage variations at a given point in one side of that bridge circuit, which are due to variations in the twelve volts, should equal the voltage variations, at the cor-responding point in the other side of that bridge circuit, which are due to variations in the twelve volts. AS a result, although the voltage at the junction between re-sistors 400 and 402 will vary with variations in the vol-tage of the source, and although the voltage at the middle contact of the potentiometer 408`will also vary with variations in the voltage of the source, the var-iations in those voltages which are due to variations in the voltage of the source should be substanti-ally the same. Consequently, the difference 103.

L6~i between the voltage at the junction between resistoxs 400 and 402 and the voltage at the mo~able contact of potentiometer 408 should be essentially independent of and unaffected by variations in the twelve volts;
and the operational a~pli~ier 420 responds to the di~erence.
Specifically, the mo~able contact of potentio-meter 408 is connected to the in~erting input of opera-tional amplifier 42~, and, as pointed out hereinbe~Eore, resistor 416 and capacitor 418 tend to provide an averaging action o~ the changing voltage at the collector of transistor 414 and apply the resulting average voltage to the non-in~erting input of that operational amplifier.
That operational amplifier is connected as a summing integrator, and hence it can respond to a di~ference between the voltages applied to the inputs thereof to develop an output voltage; and thereafter it can maintain that output voltage constant even though both input vol;tages become the same. That operational amplifier enables the SPEED ADJUSTING sub-block~356 to control the speed o~ ~he motor 562 with an exceedingly high degree of accuracy. Thus, in the said one preferred embodiment, that operational amplifier enables that SPEED ADJUSTING
sub-block to limit variations in the speed of the motor 562 to plus or minus one quarter of one percent.
The Zener diode 430 responds to the voltage at the output of the operational amplifier 420 to apply a coxresponding, but lesser, voltage to the base of tran-sistor 468; and resistor 432 will limit the current which that operational amplifier can apply to the ~ 104.

7~66 base-emitter. circuit o~ that tr~nsistor. Txansistor 468 and transistors 480.and 482 ampli~y the signal pro-~ided ~y the Zener diode 430, and the transistor 482 can supply sufficient power to dri~e the motor 562.

104~.

7~66 The speed of the motor.562 is set by appro-priately settin~ the` mo~able contact of the po.tentiometer 408; a~dr in the said pxeferred e~bodiment of the present invention, the speed of that motor is set to cause each inserted bill to move at the rate of t:en inches per second. The A.C. generator 560 will r.espond to rotation o~ the sha~t of the:motor 562 to supply sine waves to the SPEED AD~USTING sub-bloc~ 356; and that sub-block will respond to the frequency, rather than to the amplitude, of the sine waves which are developed by the A.C.
generator 560. As a result, that sub-block minimiges the ef~ects which variations in the temperature of the motor and which variations in the twel~e volts could have on the speed of motor 562. In actual practice, it has been found that the signals which the SPEED ADJUSTING
sub-block 356 applies to the base of transistor 46~ are effectively independent of even substantial changes in the temperature of the motor, whereas the output signals of speed adjusting circuits which respond to the amplitude of sine waves developed by a tachometer can vary as much as plus or minus sixteen percent.
The SPEED ADJUSTING sub-block 356 is not, per se, a part of the present invention; and, for a more detailed explanation of the manner in which it controls the speed of the motor 562,,reference should be made to the said Jones application. However, the inclusion of the SPEED ADJUSTING sub-block 356 in the overall cirquit of the paper currency validator of`the present invention is ~ery desirable because that SPEED ADJUSTING sub-block and the phase locked loops in the FREQUENCY DETECTORS 792 105.

-~47~i6 and 794 make it com~exciall~ practi:ca:L to set the pass bands of plus and ~i~us five percent ~Eor those phase locked loops. The SP~ED ~DJU~TING sub-block 356 controls the speed of the motor 562 so closely that, insofar as the speed of inserted bills was conce:rned, it would be possible to make the pass bands for t:he phase locked loops:even narrower. However, the inherent variations in the engravings on authentic U.S. bills coact with the dimensional changes in those bills due to m~sture and to wear and ~olding to require band passes of plus or minus five percent.
The current which drives khe motor 562 flows from the source of regulated twent~-four volts via the collector-emitter circuit of transistor 482, conductor 366, relay contacts 492, motor 562, relay contacts 494, conductor 372, and then either through resistor 502 to ground or through resiskors 504 and 506 to ground.
The voltage at the junction between resistors 504 and 506 is applied to the base of transistor 500 by a resistor 508; but, under normal conditions of operation o~ the motor 562, the voltage at the base of that transistor will be so close to ground that the transistor 500 will remain non-conductive. However, in the event the value of- the current flowing through the motor 562 were to increase appreciably, the voltage at the junction between resistors 504 and 506 would increase to the point where transistor 500 was forward biased;
and, thereupon, that transistor would become conductive.
The resulting "0" at the input of inverter 512 would cause that inverter to apply a "1" to conductor 106.

i6 374, and thus to the upper input of NOR gate 518 in the COUNT E~AB~ block 514, o~ ~ig. 3B. The resulting "0"
at the output o~ that NOR ~ate would cause inverter 520 to apply a "1" to conductor 522, and :hence to the lower inputs of NOR ~ates 800 and 802 in Fig. 3C. The resulting "0's" at the clock inputs of the COUNTERS
804 and 806 would keep those COUNTERS ~rom applying "l's"
to the input of NAND gates 834 and 836.
The current flowing through the motor 562 would increase to a value ~hich would render conductive the transistor 500, in the CURRENT SENSING sub-block 362 o~ Fig. 8, only in the event a person inserted a bill or other ob~ect in the bill transport 30 and then retarded or halted inward movement of that bill or object. As the inward movement of that bill or object was retarded or halted, the frequency of the signal which the A.C. generator S60 applied to the MONOSTABLE MULTIVIBRATOR 392 via conductors 368 and 370, full-wave bridge rectifier 376, resistor 380, transistor 378 and capacitor 386 would decrease; and the SPEED
ADJUSTING.sub-block 356 of Fig. 5 would respond to that decrease in frequency to sharply increase the voltage at the output of operational amplifier 420. The resulting increase in the current flowing through motor 562 and resistor 506 would cause the voltage at the junction between that resistor and resistor 504 to increase to the point where transistor 500 becomes conductive.
If the person halted further inward movement of the bill be~ore the leading edge of that bill closed the 107.

~0~71~i switch 162, and i~ that person held that bill stationary for five hundred thirty~iYe milliseconds after the switch 156 was closed, NAND gate 270 would respond to the "1" which conductor 260 would apply to the upper input thereof and to the "1" which the conductor 780 would apply to the lower input thereo~ to apply a "0"
to the second uppermost input of NAND gate 326 -- thereby causing the motor 5.62 to reverse and ca--sing re-setting of the CQUWTERS 804 and 806 in the manner described hereinbefore. If that person halted the inward movement of the bill after the leading edge of that bill had closed switch 162 but before the appropriate COUNTER 804 and 806 had acted through the adjacent NAND gate and inverter to ca~se the EXCLUSIV~ OR gate 846 and the inverter 848 to change the ~ l.on conductor 852 to a "0", and if that person held that bill or object sta-tionary until approximately six hundred and sixty-eight milliseconds after the switch 156 was closed, NAND
gate 268 would respond to the "l's" which conductors 258, 260 and 852 would be applying to the upper, middle and lower inputs thereof to apply a "0" to the uppermost input of NAND gate 326. At such time, the latter NAND
gate would efect reversal of the motor 562 and re-setting of the COUNTERS in the manner explained herein-before. If a person did not halt the inward movement of the inserted bill or object but did retard that inward movement su~ficiently to cause the CURRENT sensing sub~block 362 to apply a "1" to conductor 374, the con-tinued "0" on conductor 850 would, at the time switch 146 re-opened, 108.

~7~L~iÇii coact with the "0's" at the upper and middle inputs o~
NOR gate 290 to cause that NO~ gate to forwaxd bias diode 300. At such t~me, NOR gate 295, diode 320 and N~D gate 326 would cause the motor 562 to reverse and would cause the COUNTERS 804 andj806 to re-set, all as explained hereinbefore. If, a person halted or retarded the inward movement of the inserted bill or object and thexeb~ caused that bill or object to keep switch 156 closed approximately seven hundred and thirty-five milliseconds after that switch was closed, NAND gate 272 and inverter 274 would coact with diode 276, NOR gate 295, diode 320 and N~ND gate 326 to cause the motor 562 to re~erse and to cause the COUNTERS 804 and 806 to re-set.
If a person were to halt or were to appreclably retard the inward movement of an authentic U.S. bill after one of the COU~TERS 804 and 806 had caused the adjacent NAND gate and inverter to apply a "0" to the upper input of the adjacent NOR gate and to the input of the adjacent inverter, and if that halting or xetarding was merely momentary in nature, the belt 198 and its counterpart would move that bill into the bill-receiving area of the dispensing machine. The subsequent re-opening of switches 162 would enable NAND gate 232 and inverter 238 to re-apply a "1" to the upper input of NAND gate 240; and that "1" would coact with the "1"
which conductor 850 would be applying to the lower input of that NAND gate to enable that NAND gate to apply "0's" to the lower input of NOR gates 838 and 109 .

~Q4~1~ii6 840--with conse~uent energization of the appropxiate relay coil 888 or 890. This means that if a person retarded or halted the inward mo~e~ent of an authentic U S.
bill after the VALIDATING A~D y~D~NG LOGIC block 784 had applied a "1~' to conductor 850 and a "0" to conductor 852, that person could effect energization of the appropriate relay coil 888 or`890 by promptly releasing that bill. However, if such a person retarded or halted the inward mo~ement of such a bill long enough to cause that bill to keep switch 156 closed approximately seven hundred and thirty-five milliseconds after that switch was closed, ~ND gate 272 and inverter 274 would coact with diode 276, NOR gate 295, diode 320 and NAND gate 326 to cause the motor 562 to reverse and to cause the COUNTERS 804 and 806 to re-set D_ all as explained herein-before. In these various ways, the paper currency vali-dator fully protects both the persons and the owner of the dispensing machine.
In the event a person halted the inward movement o an authentic U.S. bill after the VALIDATING AND VENDING
LOGIC block 784 had applied a "1" to conductor 850 and had applied a "0" to conductor 852, and while that bill was holding switch 162 closed, and if that person there-after pulled that bill far enough toward the platform 32 to release the actuator 164 of that switch, the paper currenGyvalidator would re~erse the motor 562 and would re-set the COU~TERS 804 and 806. Specific~lly, as the switch 162 re-opened, conductor 776 would be applying a "0" to the upper input of NOR gate 288, conductor 768 would apply 110 .

10~
a "0" to the middle input of that NOR gate, and con-ductor 852 ~ould be appl~i~g a ~'0" to the lo~er input of that ~O~ gate. The resulting "1~ at the output of that ~OR gate :would:foxward bias diode 298 and, thereby would cause conducto~ 284 to appl~ a 11 o" to the upper input of NOR gate 2.95~ The resulting "0" at the cathode of diode 320 would ~orward bias that diode and thereby apply a "0" to the second lowermost input of NAND-cJ.ate 326 -- with consequent reversal of the motor 562 and with consequent re-setting of the COUNTERS 804 and 806 in the manner described hereinbefore.
In the event a person were to mount a portrait of an authentic U.S. bill on a sheet of paper/ or were to apply to a sheet of paper a magnetic ink simulation of the portrait background on an authentic U.S. bill, ~nd if that person were to attempt to insert either of those sheets of paper in the bill transport 30, the paper currency validator would reverse the motor 562 and would re-set the COUNTERS 804 and 806. Specifically, because that sheet of paper would not have the leading border which is present on an authentic U.S. bill, the magnetic heads 208 and 210 would.not be able to generate pulses as the leading edge of that sheet of paper en-gaged and passed beneath them. As a result, when the portrait background or the simulation thereof engaged the air gap of the magnetic head 208, the BORDER
sub~bloc~ 516 would be appl~ing a "1~ to the second uppermost input of NOR ~ate 518. The resulting ~'0"
~t t~e input of inverter 111 .

3L~4~ 6 520 would be causing that inVexter to appl~ a "lll to the lower inputs of NOR gates 800: and 802, and would thereby cause ~'0lsl~ to appear at the clock inputs o~
the COUNT~RS 80~ and 806~
~ f the leading hal$ o~ the uppex portion of the portrait background on the sheet of paper caused the magnetic head 208 to develop p,ulses, the amplifier 790 would apply amplified pulses to the FREQUENCY
DETECTORS 792 and 794 and to the BORDER sub-block 516;
and the electronic "latch" which is constituted by NAND gates 696 and 698 in that sub-block would respond to those amplified pulses to apply a continuous "l" to the lower input of NAND gate 700 and a continuous "0"
to the lower input of NOR gate 708. The transistor 682 in that sub-block would respond to those amplified pulses to re-currently become conductive and nonconduc-tive. The resulting "0's" and "l's" at the upper input of NAND gate 700 would cause that NAND gate to alter-nately back bias and forward bias the diode 702; and hence, during the fourteen milliseconds while the leading half of the upper portion of the portrait back-ground was in engagement with the air gap of the magnetic head 208, the capacitor 712 would remain charged. During the thirty-two milliseconds which would elap,se after the leading hal~ o~ the upper poxtion o~
the po~trait background ~oved beyond the air gap of the ma~netic head 208, and before the leading half of the lower portion of that portrait background engaged the air gap of the magnetic head 210, the capacitor 712 would be discharg.ing through resistor 710. However, 112.

1~47~6 at the end o~ that thirt~-two mi~lisecond period, the charge on that capacitor ~ould s~ill he grea~ enough to maintain a "1" at the intexconnected inputs of ~O~
gate 704; and hence t~e BORD~R sub-block 516, NOR gate 518, inverter 520, and NOR gates 800 and 802 would stlll be applying ~0ls~ to the clock :inputs of COUNTERS
804 and 806. As a result, even i~ FRF~QUENCY DETECTOR
792 or FREQUENCY DETECTOR 794 had responded to the amplified pulses from the amplifier 790 to apply a "0" to the upper input of the adjacent NOR gate, that NOR gate would continue to apply a "0" to the clock input of the adjacent COUNTER. This means that neither COUNTER ~ill register a count in response to the engagement between the leading half o~ the upper portion o~ the portrait background and the air gap of magnetic head 208.
As the leading half of the lower portion of the portrait background subsequently moved into engagement with the air gap of magnetic head 210, that magnetic head and amplifier 790 would apply further amplified pulses to the FREQUENCY DETECTORS
792 and 794 and to the transistor 682 in the BORDER
sub-block 516. That transistor, NAND gate i00, and diode 702 would respond to those amplified pulses to recurrently apply charging pulses to the capaci~or 712 during the thirty-two milliseconds while the leading half o~ the lower portion o~ the portrait background is 113.

~7~6i~
in engage~ent with the air gap o~ ma~netic head 210.
As a result,: du~in~ the tL~e the leading hal~ o~ the lower poxtion o~ the poxtrait ~as in engagement ~ith the aix gap of the magnetic head 210~ the BORD~R sub-block 516, NOR gate 518, inverter 520, and NOR gates 800 and 802 would effectively keep any "0~' which either of the FREQUENCY DET~CTORS 792 and 794 .developed at its output from causiny the adjacent COUNTER to register a count. During the eighteen millisecond interval between the instant the leading half of the lower por-tion of the portrait background moved beyond the air gap of magnetic head 210 and the instant the trailing half of the upper portion o that portrait background moved into engagement with the air gap of magnetic head 208, the capacitor 712 uould be discharging through resistor 710. However, at the end of that eighteen millisecond period, the charge on that capacitor would still be great enough to apply a "l" to the inter-connected inputs..of NOR gate 704.

114.

7~
At the end of the eighteen millisecond in-terval, the trailing half of the upper portion of the portrait background would cause magnetic head 208 and amplifier 790 to apply further pulses to the FREQUENCY
DETECTORS 792 and 794 and to the transistor 682 of the BORDER sub-block 516. That transistor, NAND gate 700 and diode 702 would respond to those amplif.ied pulses to supply further charging pulses to capacitor 712, and hence, at the end of the sixteen millisecond pericd of timé during which the trailing half of the upper portion of the por-trait background was in engagement with the air gap of the magnetic head 20~, the capacitor 712 would be applying a "1" to the inter-connected inputs of NOR gate 704. Dur-ing the ensuing twenty-five millisecond period between the instant the trailing half of the upper portion of the por-trait background moved beyond the air gap of magnetic head 208 and the instant the trailing half of the lower portion of that portrait background moved into engagement with the air gap of magnetic head 210, the capacitor 712 would be discharging through resistor 710. However, at the end of that twenty-five milliseconds, the charge on that capa-citor would still be great enough to continue to apply a "1" to the inter-connected inputs of NOR gate 704; and hence the BORDER sub-block 516 would continue to apply a "1" to conductor 517, and thus to the second-uppermost input of NOR gate 518. As a result, inverter 520 would continue to apply "l's" to the lower inputs 115.

1al~7166 of NOR gates 800 and 802,,and those NOR gates would e~ectivel~ keep any "0" which could develo~ at the output of either o~ the`FR~QUENC~ DET~CTORS 792 and 794 from causing the adjacent COUNT~R to xegister a count.
Duxing the ensuin~ thixty-f.ive ~illiseconds when the trailing half of the lower portion of the portxait background was in engage~ent with the air gap o~ the magnetic head 210,,that magnetic head and amplifier 790 applied furthex amplified pulses to the input o~ the FREQUENC~ DETECTORS 792 and 794 and also to the transistor 862 in the BORDER sub-block 516.
The capacitor 712 would be re-charged during those thirty-five milliseconds, and hence the NOR gates 800 and 802 would continue to e~fectively isolate the FREQUENCY DETECTORS 792 and 794 from the adjacent COUNTER.
All of this means that because the sheet of paper did not have a border which was comparable to the border on an authentic U.S. bill, any "0" which was developed at the ~utput of either of the FREQUENCY
DETECTORS 792 and 794 could not have caused the adjacent COUNTER to register a count. Further, it means that neither of the NAND gates 834 and q36 was able to apply a 1l0ll to the upper input of the adjacent NOR
gate or to,~he input o~ the adjacent inverter. As a result, either when the'switch 146 subsequently xeopened as the trailing edge o~ the inserted bill moved inwardly beyond the actuator 148,,or approximatel~

116.

six hundxed sixty-eight milli:s.econds after the swi.tch 156 was closed, whichever occurs first, the motor 562 would Xevexse~ Specifically, as the switch 146 re opened, NOR gate 290 would have "0's" applied to all of the inputs thereof, and the resulting "1" at the output thereof would forward bias diode 300 and thereby cause conductor 284 to apply a "1~' to the upper input of NOR gate 295. The resulting "0" at the output of that NOR gate would forward bias the diode 320 and apply a "0" to the second lowermost input of NAND gate 326~ with consequent reversal of the motor 562 and with consequent re-settiny of the COUNTERS 804 and 806.
If the swltch 146 did not re-open before approximately six hundred sixty-eight milliseconds after switch 156 was closed, NAND gate 268 would have "l's" applied to all of t~he inputs thereof, and it would apply a "0"
to.the uppermost input of NAND gate 326, with con-sequent reversal of the motor 562 and with consequent re-setting of the COUNTERS 804 and 806. It thus should be clear that the insertion of a sheet of paper which has the portrait backgrund of an authentic U.S.
bill thereon but which does not have a border corres-ponding to the leading border of such a bill would cause the paper currency validator to reverse the motor 562 and to re-set the COUNTERS 804 and 806.
If a person were to insert into the bill transport 30 an authentic U.S. bill which had been altered so the 117.

~7~
intensity of the m~gnetic ink in the leading border thereo~ was too low,.t~e ampliPied pulses which magnetic head 208 and amplifier 790 would apply to the BORDER
sub-block 516 would not attain the threshold value of tr~nsistor 862 in that sub-block. As a result, that transistor would remain non-conductive; and that sub-block would coact with NOR gate 518, .inverter 520, and NOR gates 800 and 802 to effectively isolate -the COUN~ERS 804 and 806 from the FREQUENCY DETECTORS 7 9 2 and 794, all as explained hereinbeore. Consequently, the paper currency validator would reject such a bill in the same manner in which it rejected the sheet of papex which had the portrait background of an authentic b~ll applied to it.
In the event a person were to insert into the bill tranSpOrt 30 an authentic U~S. bill which had a denomination other than a one or a five, the pulses which the magnetic heads 208 and 210 would generate as the appropriate portions of the portrait background moved past the air gaps of those magnetic heads with fre-quencies to ~hich the phase locked loop, in the FREQUENCY DETECTORS 792 and 794 could not respond. AS
a result, the insertion of any such U.S. bills would leave "0's" at the outputs of the COUNTERS 804 and 806, and hence the NAND gates 834 and 836 would continue to apply "l's" to the upper inputs of NOR ga~es 838 and 840 and to the inputs o~ inverters 842 and 844. Consequently, the motor ~62 would reverse approxi-11~ .

6i~
~ately six hundred sixty-eigh~ milliseconds af~er. switch 156 was closed or ~hen.inwaxd movement of the inserted bill pexmitted the switch 1~6 to Xeopen, whichever occurred first. In this way, the paper currency validator of the present.invention pro.tects a patron against the loss of a high denomination bill through the inadvertent insertion o~ that bill in the bill transport 30.
If a person were to obtain or make an object which had a leading border that closely simulated the leading border of an authentic U.S. bill, and which had parallel lines of magnetic material on the upper face.
thereo~ that were spaced so they caused each o~ the FREQUENCY DETEcTORS 792 and 794 to apply four clock pulses to its COUNTER as that bill or object moved past the magnetic heads 208 and 210, those COU~TERS would cause the NA~D gates 834 and 836 to apply "0's" to.the upper inputs of NOR gates 838 and 840 and to the inputs o~ inverters 844 and 842. The resulting "1" at both inputs of the EXCLUSIVE OR ga-te 846 would cause that EXCLUSIVE OR gate to continue to apply a "0" ~o con-ductor 850 and to the input of inverter 848. The resulting "1" on conductor 852, and the resulting "0"
on conductor 850, would cause the motor 562 to reverse and would cause the COUNTERS 804 and 806 to re-set approximately six hundred sixty-eight milliseconds after the switch 156 was closed or as the trailing edge of the inwardly ~oving bill permitted 119 .

~47~i6 the s~itch 146 to re-open, ~iche~ex occurred ~irst.
This means that any ob.ject ~hich could cause both COUNT~RS 804 a~d 806 to receive foux counts as that object moved past the magnetic heads.208 and 210 would be rejected.
In the.event any o~ the switches 146, 156 or 162 were to be held closed, either deliberately or accidental-ly, for more than seventeen seconds~ the RC network which is-constituted by resistor 460 and capacitor 458 in the SPEED MAINTAINING sub-block 358 of Fig. 6 would be ~Itime out". As the switGh 146 closes during each opera-tion of the paper currency validator, NAND gate 251 will apply a "1" to the conductor 253, and thus to the inter-connected inputs o~ NAND gate 434 in Fig. 6.
The resulting 1l 0 " at the output of the latter NAND
gate will make transistor 438 non-conductive, and the consequent "1" at the collector of that transistor will back bias the~diode 444. NAND gate 448 will respond to the lll" at the upper input thereof and to the "1"
at the lower input thereo~ to apply a "0" to the anode of diode 456; and the resulting back biasing of that diode will permit the capacitor 450 to start discharging through the resistor 460. However, in the normal operation of the paper currency validator, the inserted bill will move inwardly and will successively permit the switches 146, 156 and 162 to re-open in less than one second, or the motor 562 will reverse and that bill will move back out o~ the bill transport 30, and thereby permit all o~ those switches to re-open, 120.

10~a7~

in less than two seconds. Cansequentl~, during the nor~al opexation of the paper cuxxency val-idatox,the switches 146, 156 and 162 will xe-open, and will cause NAND gate 232, inverter 238, diode 245 and NAND gate 251 to re-apply a "0" to the in*erconnected inputs of NA~D gate 434 -- with consequent xe-charging of capacitor 458 -- long before the charge on that capacitor can decrease to a le~el at which the "1" which that capaci-tor applies to the lower input of NAND gate 450 could beco~e a lloll. However, if any o~ the switches 146, 156 and 162 were held closed for more than seventeen seconds, the capacitor 458 would be pexmitted to dis-charge ~or that length of time; and the charge on that capacitor would decrease to the point where the "1"
at the lower input of NAND gate 450 would change to a "0". Thereupon, a "1" would be applied to the base o~ transistor 466; and that transistor would again become conductive and would thereby again render the transistor 468, 480 and 482 non-conductive. At such time, the motor 562 would come to rest.
~hen that closed switch re-opened, either accidentally or as a result of positive action, the resulting "0" at the output of NAND gate 232 would cause inverter 238 to back bias the diode 245; and the resulting "1" at the upper input o~ N~ND gate 251 would coact with the "1" which conductox 242 was applying to the lowex input of that NAND gate to cause that NAND
gate to reapply a "0" to the interconnected inputs of N~ND ~ate 434 in Fig~ 6. Consequently, the re-opening of that switch would permit the SPEED MAINTAINING sub-block 358 of Fig. 6 to resume its at-rest position.

1~471G6 In the` foregoing description of the operation of the paper curxency ~alidato~ b~ an authentic U.S.
one dollax bill, it was-assumed that the magnetic head 208, the ampli~ier 790 and the ~REQUENCY PETECTOR 792 applied two time-spaced "0's~ to the upper input o~
NOR gate 800, and thereby caused that NOR gate to apply two time-spaced "l's" to the clock input of COUNTER 804.
Also it was assumed that the magnetic head 210 coacted with amplifier 790 and FREQUENCY~DETECTOR 792 to apply two fuxther time-spaced"0's" to the upper input of NOR
gate 800, and thereby caused that NOR gate to apply two further time spaced"l's" to the clock input of that COUNTER. However1 because the pulses which are developed by the oscillator in the phase locked loop in the FREQUENCY DETECTOR 792 may randomly be in or out of phase with the amplified pulses from the FREQUENCY
DETECTOR 792, that phase locked loop may in a small percentage of instances respond to the four time-spaced amplified pulses from the amplifier 790 to apply just three time-spaced "0's" to the upper input of NOR gate 800 even though an authentic U.S. one dollar bill is being sensed. In that small percentage of instances, that NOR gate will be able to supply just three time-spaced "1's" to the clock input of the COUNTER 804;
but, as long as the mo~able cont~cts `808 and 810 axe in the lo~er positions shown by Fig. 4, that COUNTER will be able to xespond to those "Ils" to apply "l's" to both inputs of NAND gate 834.
If, at any time, one or more persons were able to cause a simulation of an authentic U.S. bill to 1~2.

~LQ4~66 make the. ma~netic heads 208 and 210~,the ~mplifier 790, the FREQUE~CY DET~CTOR.792~,and the NOR gate 800 apply three'but not four ~'l's" t~ the.~lock input o~ COUNTER 804, it would be a simple'matter to shift the movable contacts 808 and 810 to` their upper positions. Thereupon,,any such person or persons would be kept ~rom improperly eneryizing the relay coils 888 and 890. Specifically, when the ~ovable contacts 808 and 810 are shifted into their upper positions, the movable contact 808 will not apply a ~'1" to the upper input o~ NAND gate 834 until a "1" appears at the fourth output terminal of the COUNTER 804. Conseque~tly, any simulated bill which could cause the VALIDATING AND VENDING LOGIC block 784 of Fig~ 3C to apply three, but not four, time-spaced "l's"to the clock input of the CQUNTER 804 could not cause that counter to apply a "1" to the input of NAND gate 834. Consequently, the paper currency validator would keep the relay coils 888 and 890 un-energized and would subsequently reverse the motor 562.
In the event the phase locked loop in the FREQUENCY DETECTOR 792 were to respond to amplified pulses from the amplifier 790, which were one hundred and eighty degrees out o~ phase with the pulses generated by the oscillator of that phase locked loop, to cause that FREQUENCY DETECTOR to apply five time-spaced,"0ls" to the upper input o~ NOR gate 800, -- even though an authentic U,S. one dollar was being sensed -- that NOR
~ate would apply ~ive time-spaced "l's" to the clock input of COUNTER 804. If, at the time the fifth "1"
was applied 123.

61~

to the clock input of the COUNT~ 804, t~e contacts 808 and 810 were in the lower positions shown by Fig.
3C, the "1" at the output terminal 818 would cause inverter 819 to apply a "0" to the data input terminal of that COUNT~R. As a result, that Ei~th n 1~ would cause a "0" to appeax at output texminal one of that COUNTER;
but "1 t S ~I would continue to appear at output terminals three and four o~ that COUNTER. Consequently, NAND
gate 834 would continue to have ~ll's" applied to both inputs thereof, and would continue to apply "0's"
to the upper input of NOR gate and to the input of inverter 844.
I~ the movable contacts 808 and 810 had been in their upper positions, the ourth l'l" at the clock input o~ COUNTER 804 would have caused the "0" which inverter 819 was applying to the data input terminal of that COUNTER to appear at output terminal one. Then, as the fifth "1" was applied to that clock input, the llo1l on output terminal one would appear at output terminal two and the "0" which inverter 819 was applying to the data input.terminal of COUNTER 804 would appear at output terminal one. However, because contact 808 was connected to output texminal four rather than to output terminal two, and because contact 810 was energizing output terminal 828, the NAND gate 834 would continue to ha~e "l's" applied to both inputs thereof, and would continue to apply "0's" to the upper input o~ NOR gate and to the input o~ invertex 844.
All o~ this means that whether the movable contacts 124.

~47~66 808 and 810 are in the lower positions ~hown by ~ig. 3C
or are in their upper positions, the COUNT~R 804 will be a~le to respond to fi~e`"l's" at the clock input thereo to apply "l's" to both inputs o NAND gate 834.
Conse~uentl~, i, in responses to ampliied pulses that are derived from an authentic U.S. one dollar bill, the phase locked loop o~ the FREQU~NCY DETECTOR 792 pro-duces five rather than our time-spaced "0's", the paper currenc~ validator will accept that bill and will energize the relay coil 888.
However, if a sixth "1" is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their lower posi-tions, the "0" which appeared at output terminal one as a result of the fifth "1"
at the clock input would respond to the sixth "l" to appear at output terminal two. The resulting application by contact 808 of a "0" to the upper input of NAND gate 834 will change the "0's" at the upper input of NOR
gate 838 and at the input of inverter 844 to "l's".
I~ that sixth "1" is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their upper positions, the "0" which appeared at output terminal two as a result o the fith "1" at the clock input would respond to the sixth "1" to appear at output terminal three. The resulting application of a "0"
to the lower input o~ NAND gate 834, by the conductor which extends from the output terminal three to that lower input, will change the "0's" at the upper input o~ NOR gate 838 ~nd at the input of inverter 844~ ~o "l's".

125.

If a seventh "1" is applied to the clock input of COVNTER 804, while the contacts 808 and 810 are in their lower positions, the "0's" which appeared at out-put terminals one and two as a result of the sixth "1"
would respond to that seventh "1" to appear at output ter-minals two and three. The resulting application of "0's"
to both inputs of NAND gate 834 will change the "0's" at the upper input of NOR gate 838 and at the input of in-verter 844 to "l's". If that seventh "1" is appliecl to the clock input of COUNTER 804, while the contacts 808 and 810 are in their upper positions, the "0's" which appeared at output terminals two and three as a result of the sixth "1" would respond to the seventh "1" to appear at output terminals three and our. The result-ing application of "0's" to both inputs o~ NAND gate 834 will change the "0's" at the upper input of NOR gate 838 and at the input of inverter 844 to "l's".
All of this means that if an inserted bill or other object causes the VALIDATING AND VENDING LOGIC
block 784 to produce a count of two or less or to pro-duce a count of six or more, when the contacts 808 and 810 are in their lower positions, the paper currency validator will not energize either o the relay coils 888 and 890, and that paper currency validator will subsequently reverse the motor 562 and thereby move the inserted bill or object back out of the biIl transport 30. Further, it means that if an inserted bill or other object causes the VALIDATING AND VENDING
LOGIC block 784 to produce a count of ~ ~2i3 7~66 six or more, when the contacts 808 and 810 are in their upper positions, the paper currency validator will en-ergize neither of the relay coils 888 and 890, and that paper currency validator will subsequently reverse the motor 562 and thereby move the inserted bill or object back out of the bill transport 30.
The switches that are constituted by the mov-able contacts 820 and 822 and the stationary contacts 824, 826, 828 and 830 will coact with the COUNTER 806 to pro-vide comparable acceptance of five dollar bills and com-parable rejection of five dollar bills. Thus, when the contacts 820 and 822 are in their lower positions, auth-entic U.S. five dollar bills will be accepted if the VALIDATING AND VENDING LOGIC block 784 provides three, our or ive counts; but relay coil 890 will remain un-energized and motor 562 will reverse i that block pro-vides two or less or six or more counts. When the con-tacts 820 and 822 are in their upper positions, authentic U.S. five dollar bills will be accepted if the VALIDAT-ING AND VENDING LOGIC block 784 provides four or fivecounts; but relay coil 890 will remain un-energized and motor 5~2 will reverse if that block provides three or less or six or more counts.
Normally the movable contacts 808, 810, 820 and 822 will be set in their lower positions, because those contacts provide a higher acceptance rate for authentic U.S. bills when they are in those lower positions. However, those contacts will be set in their upper positions i any person or persons is able to cause a simulation of an authentic U.S. bill to make the magnet-ic heads 208 and 210, the amplifier 790, the FREQUENCY

~27 ~7~66 D~TECTOR 792 ox the ~REQUENCX D~T~CTOR 794 and t~e adjacent NOR ~ate apply thxee but not four "l's" to the clock input o~ t~e adiacent COUNTE~.
In the'at-xest condition o~ the paper cur-xency ~alidatox,,the dispenslng machine with which t~at paper currency ~alidator is associated will be applying a "1" to terminal 526 and a "1" to terminal 530 of the COUPLING block 524-in Fig. 3B. Diodes 536 and 538 will limit the voltages which can be applied to the opto-couplers 540 and 542, but those voltages will be sufficient to cause the light-emitting diodes of those opto-couplers to cause light to fall upon the light-sensitive elements of those opto-couplers. The resulting "0" at the input of diode 548 will ~orward bias that diode and thereby apply a "0" to the upper input of NAND gate 720 and to the input of inverter 724~.
The "0" at the upper input of NAND gate 720 will cause that NAND gate to apply "1" to the input of inverter 722, with consequent application of a "0" to the middle input of NOR gate 758. The "0" at the input of inverter 724 will causé that inverter to apply "1" to the lowermost input of NAND gate 728. The "0" at the output of opto-coupler 542 will forward bias diode 550 and thereby apply a "0" to the lower input of NAND gate 720 and to the input o~ invertex 726. The "0" at the lower input of ~AND gate 720 will not change the "1" at the output o~ that NAND gate. The "0" at the input of inVer,ter 726 will cause that inVerter to apply "1" to the lowermost input o~ NAND gate 730.

128.

~,~47~616 All of this means that as long as the dispens-ing machine applies "l's" to terminals 526 and 530 of the COUPLING block 524, that block will not cause the INHIBIT
LOGIC block 718 to apply inhibiting signals to the middle input of NOR gate 758 or re-setting signals to the re-set terminals of COUNTERS 804 and 806. However, if the dis-pensing machine becomes unable to supply change or pro-duct in response to the insertion of an authentic U.S.
five dollar bill into the bill transport 30, that dispens-ing machine will change the "1" at input terminal 530 ofthe COUPLING block 524 to a "0". Thereupon, the output of the opto-coupler 542 will become a "1", and the re-sulting back-biasing of diode 550 will cause a "1" to ap-pear at the lower input of NAND gate 720 and at the input of inverter 726. The "1" at the lower input of NAND gate 720 will not change the "1" at the output of that NAND
gate, but the "1" at the input of inverter 726 will causé
that inverter to apply a "0" to the lowermost input of NAND gate 730. The resulting "1" at the reset terminal of COUNTER 806 will effectively prevent that counter from responding to any signals from the FREQUENCY DETECTOR 794.
Consequently, even if an authentic U.S. five dollar bill is inserted in the bill transport 30 and causes the FRE-QUENCY DETECTOR 794 to develop four proper time-spaced signals, the relay coil 890 will remain un-energized and a "0" will continue to appear on conductor 850 and a "1"
will continue to appear on conductor 852. Approximately six hundred sixty-eight milliseconds after switch 156 was closed or as the trailing edge of the inwardly-moving bill permits switch 146 to re-open, whichever occurs first~ the motor 562 will be reversed.

. , .

71~;6 If the dispensing machine becomes unable to supply change or product in response to the insertion of an authentic U.S. one dollar bill, that dispensing machine will change the "1" at the input terminal 526 of the COUPLING block 524 to a "0". T:hereupon, the output of opto-coupler 540 will become a "1" and the re-sulting back biasing of diode 548 will cause a "1" to appear at the upper input of NAND gate 720 and at the input o inverter 724. If, at that time, the dispensing machine is applying a "l" to the terminal 530 of that COUPLING block, the application of the "l"~to the upper input of NAND gate 720 will not change the output of that NAND gate, because opto-coupler 542 and diode 550 will continue to apply "0" to the lower input of that NAND gate. However, the "l" at the input of inverter 724 will cause that inverter to apply a "0" to the lowermost input of NAND gate 728, with consequent re-setting of COUNTER 804. Consequently, even if an authentic U.S. one dollar bill is inserted in the bill transport 30 and causes the FREQUENCY DETECTOR 792 to apply four proper time-spaced signals to that COUNTER, the relay coil 888 will re-main un-energized and a "0" will continue to appear on con-ductor 850 and a "l" will continue to appear on conductor 852. Approximately six hundred and sixty milliseconds after switch 156 was closed or as the trailing edge of the inwardly-moving bill permits switch 146 to re-open, which-ever occurs first, the motor 562 will reverse.
If the dispensing machine is unable to dispense change or product in response to the in-sertion of an authentic U.S. five dollar billand also is unable to dispense change or 7~

product in response to the insextion o~ an authentic U.S. one dollar bill,: that dispensing machine will change the "l's" at the input terminals 526 and 530 of the COUPLING block ~24 to "0's". The resulting "l's"
at the output of optical-couplexs.-540 and 542 will back bias the diodes 548 and 550, and will thereby cause "l's" to appear at both inputs o NA~ID gate 720 and at the input of each of the inverters 724 and 726. The resulting "0" at the output of NAND gate 720 will cause inverter 722 to apply a "1" to the middle input of NOR
gate 758; and thereafter that NOR gate will apply a continuous "0" to conductor 764 and will cause the inverter 770 to apply a continuous "1" to conductor 776.
This means that even i~ a bill or other object is inserted in the blll transport 30 and closes the switch 146, the motor 562 will remain de-energized. Consequently, that bill transport will be wholly unable to accept and validate any U.S. one dollar or five dollar bills.

The "l's" at the inputs of inverters 724 and 726 will cause those inverters to apply "0's'l to the lowermost in-puts of NA~D gates 728 and 730; and those NAND gates will apply "l's" to the re-set terminals of COUNTERS
804 and 806. In this way the COUpLING block ma~es certain that the relay coils 888 and 890 will remain un-energized.
~he opto-couplers 540 and 542 are useful in isolating the voltages in the paper currency validator ~rom the voltages in the dispensing machine. As a result, that dispensing:~achine could be connected to the standard and usual one hundred and seventeen volt A.C. sockets which generally are provided in buildings, 131.

1~47166 and ~et the paper currenc~ ~alidatox can be powered by relatively low-.voltage. direct.current. ~urther,.those opto-couplers avoid th-e cost, bulk,. noise and electro-ma~netic radiation which .the use of. electromagnetic reIa~s, that could be u.sed in lieu of those opto-couplers would entail.
Persons have been known to insert an authentic U.S. bill in a paper currency validator and then manipu-late :the plug at the end of the electric cord of that paper curxency validator in the hope that such man:ipula-tion could cause the dispensin~ machine, associated with that paper.currency validator, to dispense change or a pxoduct. Specifically, such persons have been known to remove that plug from the socket therefor and then repeatedly and rapidly reinstate and remove that plug, thereby applying a succession o~ electrical impulses to the circuit of the paper currency validator. Such a prac-tice, which is known as "line cording" could not cause the paper currency validator of the present invention 20 to energize either of the relay coils 888 or 890. Also, any "line cording" which appreciably affected the voltage supplied to the paper currency validator would cause the motor 562 to start operating in the reverse direction and would reset the COUNTERS 80~ and 806.
Specifically, if "line cording" were to de-crease the twenty-four volts, that normally is supplied to the cathode of Zener diode 304 in the MOTOR REVERSE
LOGIC block 286, the tweI-~e volts at the upper terminal o~ resistor 3I2 would not decrease until the voltage at the cathode of that zener diode decreased to 132.

7~6 less than twelve ~olts. As the:non-regulated twenty-four.volts decreased to appxoxi~atel~ .thirkeen.volts, the Zener. diode 304 would become non-conductive,~ and hence the base o~ transis~or 30 wbuld tend to drop to ~round voltage. Thereupon, that transistor would become non-conductive; and the.voltage at the collector of that txansistor would start to increase. Capacitor 329 which coacts with resistox 312 to constitute an RC
network will retard the rate of increase of the co;Llector voltage of kransistox 302 and will thereby delay the application of a "1" to khe input of inverter 314. -This means that if the removals and re-insertions of the plug occurred at a rapid rate a~ter the transistor 302 had become non-conductive, but be~ore the voltage, that is applied to the paper currency ~alidator, fell below the level which is needed to enable the various transistors and gates of that paper currency validator to function, the capacitor would maintain a "0" at the input of in~
verter 314 and thereby prevent a premature and un-needed reversal of the motor 562. In addition, the capacitor 329 will prevent premature and un-needed reversal of the motor 562 if a voltage transient, which otherwise might render transistor 302 non-conductive, were to develop.
If the removals and re-insertions of the plug occurred at a slower rate and thereby permitted a "l"
to appear at the input o~ inve~ter 314l that inverter would apply a "0" to thè cathode of diode 318 and to the uppermost inputs o~ ~A~D gates 728 and 730. Those NAND gates would apply "l's": to the re-set ~ 133.

1~47~L~i6 input terminals of the COU~T~R~ 804 and 806 and would re-set those COUNTERS; and the diode 318 would become ~orward biased and thereb~ apply a "0" to the second lowermost input of NAND gate 3Z6. The resulting "1"
at the output of NAND gates 3~6 would effect the reversal of motor 562. ~11 o~ this means that if "line cording"
ever caused the twenty-~our volts at the cathode o~
Zener diode 304 to decrease below thirteen volts, transistor 302, inverter 314, and diode 318 would cause NAND gate 326 to initiate reversal of the motor 562 and to effect re-setting of the COUNTERS 804 and 806.
If the person who was attempting to "line cord" the paper currency validator of the present invention re-inserted the plug in the socket before the voltage, that is applied to the paper currency validator, fell below the level which is needed to enable the various transistors and gates of that paper currency validator to function, the motor 562 would operate in the reverse direction. That motor would continue to operate in reverse, and the COU~TERS 804 and 806 would continue to remain re~set, until the switch 146 re-opened as the inserted bill was moved back ouk of the bill transport 30.

133~.

1()47~
In the foregoing description o~ a "line cording" attempt, it was assumed that the pexson re-inserted the plug be~ore the ~oltage, which was applied to the papex currency validator, -~ell below the level which i5 needed ko enable the various transistors and gates o~ that paper ~urrency validator to function.
I~ that person had waited until that voltage had ~allen below that level and then re-inserted the plu~, the voltages at the upper terminals of resistors 312 and 320 and at the cathode of Zener diode 304, in the MOTOR
REV~RSE LOGIC block 286 of Fig. 3A, would have been below twelve volts. As those voltages responded to the re-insertion of the plug to increase, the transistors 302 would remain non-concluctive until the voltage at the cathode of Zener diode 304 reached thirteen volts --and, prior to that time, the voltage at the upper terminal o resistor 312 would apply a "1" to the input of inverter 314, and that inverter would again forward bias the diode 3I8 to again cause a "0" to be applied to the second lowermost input of NAND gate 326. There-upon, that NAND gate would again effect reversal of the motor 562 and re-setting o~ the COUNTERS 804 and 806.
It thus should be apparent that whether a person, who is attempting to "line cord" the paper currency vali-dator, remoYes and re-inserts the plug rapidly or slowly, the transistor 302, the Zener diode 304, the resistors 306, 308, 3I2 and 320, the inYerter 3I4, and the diode 318 will respond to that removal ~nd re-insertion to cause a "0" to appear at the second lowermost input of N~ND g~te 326. At such time, the motor 562 will reverse and the COUNTERS 804 and 806 will be re-set.

134.

~047~66 I~, in atte~ptin~ to "line cord" the papex currenc~ validator, a person left the plug out of the ~socket ~or moxe khan ei~hteen seconds, the ~C network, which is constituted by resistor 452 and capacitor 454 in the SPE~D MA~NTAIN~NG sub-block 358 of Fig. 5 would hàve to be rel'ied upon to re-start that motor. At the time that ~otor came to rest, in response to the "line cordin~", the NAND gate 251 would be applying a "1"
to the'interconnected inputs o~ NAND gate 434 in that SPEED MAINTAINING sub-block; and transistor 438 in that sub-block would be non-conductive, and NAND gate 448 would have a "1" applied to the upper input as well as to the lower input thereof. During the more than eighteen seconds while'no power was being supplied to the paper currency validator, the capacitor 458 would discharge through resistor 460; and hence, when the plu~ subse-quently was re-inserted in the socket, the NAND gate ~50 would have a "0" at the input thereof. The resulting "L" at the output o~ that NAND gate would render tran-sistor 466 conductive, and would thereby keep transistors 468, 480 and 482 and motor 562 non-conducti~e. If the "1" at the lower input of NAND gate 448 was continuous in nature, it would coact with the "1" which would re-appear at the upper input of that NAND gate, as the plug was re-inserted, to apply a "0" to the upper terminal of capacitor 458; and the resultin~ con-tinuous "0" at the lower input o~ NAND gate 450 would keep the motor 562 de-ener~ized. Howe~ex, the'"l" at the lower input of NAND gate 448 is not continuous in nature; and, for a few milliseconds after the 135.

~47~6 plug ~ould be re-insexted in the socket, the time. con-stant of the RC netwoxk:constit~ed b~ capacitor 454 and resistor 452, would le~e ~ "0" at the upper terminal o~ that capacitor -- and hence:at the lower input o~
NAND ~ate 448. The resultin~ "l!' at the output of that N~ND gate would permit capacitor 458 ~.o charge and re-apply a "1" to the lowex input to NAND gate 450 --with conse~uent rendering o~ transistor 466 non-conductive and o~ transistors 468 and 480 and 482 and of motor 562 conductive. In this ~ay, the resistor 452 and 454 make it possible to automatizally re-start the motor 562 if a "line cording" attempt has caused that motor to remain de-energized for more than eighteen seconds.
The resistor 452 and capacitor 454 also will be useful in automatically re-starting the motor 562 when a bill or other object is holding one of switches 146, 156 and 162 closed after a power interruption d,ue to a storm or to the blowing of a fuse. Even though NAND
gate 232, conductor 234, inverter 238, conductor 241, diode 245, NAND gate 251, conductor 253, NAND gate 434, transistor 438, and diode 444 will immediately re-apply a "1" to the upper input of NAND gate 448 as the power is restored, the resistor 452 and capacitor 454 will cause a "0" to be applied to the lower input of NAND gate 448 for a long: enough time to permit capacitor 45a to re-charge, and thereb~ e~ect xe-starting of the ~otor 562.
Conclusion: If desixed, each of the F~QuENcy DETECTOR~ 792 and 794 could utilize a limiter,,a tuned circuit 13~.

~47~6~i and a threshold devic~ of the type disclosed by Smith et al patent No. 3,245,534; and that tuned circuit would have a fixed frequency which would enablè that tuned circuit to respond to the spacing o~ the vertical grid lines on an authentic U. S. bill to supply four distinet signals to the threshold device. Alternatively, if desired, each of the FREQUENCY DETECl~ORS 792 and 79 eould utilize a squaring eircuit, a frequency-sensing eireuit, and a threshold detector of the type disclosed by the said Fishel et al applieation; and that frequeney-sensing eireuit would have a fixed frequeney which would enable that frequency-sensing circuit to responcl to the spacing of the vertieal grid lines on an authentic U. S.
bill to supply four distinet signals to the threshold deteetor. However, in the said preferred embodiment of the present invention, phase locked loops are used in the FREQUENCY DETECTORS 792 and 794 -- despite the faet that the oseillators of phase loeked loops ean, and do, ehange the frequencies of the signals generated thereby during the normal operation of those phase locked loops, and despite the faet that the frequencies of the signals generated by the oscillators of the phase loeked loops of the FREQUENCY DETECTORS are randomly in and out of~hase with the signals applied to those phase loeked loops. The present invention makes it possible to use phase loeked loops used in the FREQUENCY DETECTORS
792 and 794 by equipping those phase loeked loops with resistors and eapacitors which elosely limit the extents ~o:whieh the- center frequenc~ies-ofithe oseillato~s 137.

~0~L716~
of those phase locked loops can shift, and also by ap-plying the outputs of those FREQUENCY DETECTORS to counters which can validate bills that cause those FREQUENCY DETECTORS to provide numbers of counts which differ from the scheduled number of counts by just one count. Specifically, the present invention equips the phase locked loops of the FREQUENCY DETECTORS 792 and 794 with resistors and capacitors which limit the shift-ing of the center frequencies of the oscillators of those phase locked loops to plus or minus five percent of those center frequencies; and the COUNTERS 804 and 806 are made so they can validate bills which cause the magnetic heads 208 and 210, the ampli~ier 790, and either the FREQUENCY
DETECTOR 792 or the FREQUENCY DETECTOR 7~ to develop three and five, as well as four, time-spaced "0's". By using phase locked loops and COUNTERS rather than the limiters, the tun~dcircuits and the threshold devices of the said Smith et al patent or the squaring circuits, frequency-sensing circuits and threshold detectors of the said Fishel et al application, the present invention sub-stantially reduces the size and the cost of the frequency-detecting portion of the circuit of the paper currency validator -- because the inductors of those tuned circuits and of those frequency-sensing circuits are bulky, and becaus~e the capacitors and inductors of those tuned circuits and of those frequency-sensing circuits must have precise values and must have low temperature coefficients, and hence are expensive. Moreover, the center frequencies of phase locked loops can easily be changed by adjustments in the positions ~ 13~

7~616 of the movable contacts of shelf-type low temperature coefficient potentiometers. As a result, the speed of the motor 562 can be set to any desired value, and then the center frequencies of the phase locked loops in the FREQUENCY DETECTORS 804 and 806 can be set accordingly with ease and precision.
The BINARY COUNTER 254 in the TIMER block 244 and the various gates and inverters in the TIMER
LOGIC block 262 provide digitally-developed time intervals; and those time intervals are more precise than are the time intervals which can be developed by usual and customary RC networks. The six hundred and sixty-eight millisecond timé interval which is provided by that BINAR~ COUNTER and NAND gate 268 is made substantially longer than the time interval which nor-mally is required for an authentic U. S. bill to close switch 156 and then cause the appropriate FREQUENCY
DETECTOR, NOR gate, COUNTER, NAND gate and inverter to cause the EXCLUSIVE ~R gate 846 to apply "1" to con-ductor 850 and to cause converter 848 to apply a "O"
to conductor 852. Specifically, when the contacts 808, 810, 820 and 322 in the VALIDATING AND VENDING
LOGIC block 784 are in their lower positions, the EXCLUSIVE OR gate 846 should apply a "1" to conductor 850 and should cause inverter 848 to apply a "O" to conductor 852 approximately four hundred and seventy-two milliseconds after the switch 156 was closed.
However, when those contacts are in their upper positions, the EXCLUSIVE OR gate 846 should apply a "1" to conductor 850 and should cause inverter 848 to apply a "O" to conductor 852 approximately five hundred and - 13~

.

1~47~
thirty-two milliseconds after the switch 156 was closed.
The difference between the six hundred and sixty-eight milliseconds and the five hundred and thirty-two milliseconds was provided to permi.t different speeds to be set for the motor 562 ancl, -to a lesser extent, to compensate for variations i.n the amounts of travel of actuator 158 as it closes the switch 156.
The five hundred and thirty--flve millisecond time interval provided by BINARY COUNTER 254 and the NAND gate 270 is substantially longer than the three hundred millisecond time interval which normally is noted between the.closing of switch 156 and the closing of switch 162. However, that time interval was selected to permit different speeds to be set for the motor 562 and, to a lesser extent, to compensate for variations in the amounts of travel of the actuators 158 and 164, respectively, for the switches 156 and 162.
When the lower "runs" of the belt 198 and of its counterpart are moving at the rate of~ten inches per second, an authentic U.S. bill should close the switch 156 and then subsequently move beyond the actuator 158 of that switch, to permit re-opening o that switch, in less than the seven hundred and thirty-five milli-seconds provided by the BINARY COUNTER 254 and NAND
gate 272. However, that seven hundred and thirty-five millisecond time interval was selected to permit different speeds to be set for the motor 562 and, to a lesser extent, to compensate for variations in the amounts of travel of the actuator 158 as it closes, and then subsequently permits re-opening of, the switch 156.

1~47~66i ~ ot only do the BINARY COUNTER 254 and the NAND
gates 266, 268, 279 and 272 provide moxe precise timing than could any usual and customary RC network, but the time intervals which are provided by that BINARY COUNTER
and NA~D gates are virtually unaffected by changes in temperatuxes. Further, the size and cost of that BINARY
COUNTER and of those NAND gates are less than the cost and size of such RC networks.
The BORDER sub-block 516 uses capacitor 712 and resistor 710 to provide a sixty millisecond time interval and uses capacitor 716 and resistor 714 to provide a thirty millisecond time interval. If desired, that BORDER sub-block could be provided with a single sub-circuit which could provide a ninety milliseconcl time interval. However, the use of the two capacitors 712 and 716 and o the two resistors 710 and 714 has been found to be desirable from the point of view of cost and.size.
The structure ancl circuit disclosed herein are especially adapted for use in the sensing of paper currency; but that structure and circuit could be used to sense documents and other suitably-engraved or printed ob~ects. Consequently, where used hereinafter in the claims, the word "bill" will be understood to compr~hend paper currency, documents and other suitably-engraved or printed objects.
To make a simulated bill which coul~ be accepted by the paper currency validator of the present invention, a person would have to use a sheet of paper that had a length close to ~47~6~
the length o~ an authentic U.S. bill, would have to provide a leading border which was generally similar to the leading border on an authentic U~ S. bill, would have to provide four longitudinally-spaced and laterally-spaced groups of vertical li.nes that were in the same areas as the quadrants of the portrait background on an authentic U. S. bill, would have to provide intervals between the leading edges of the various lines in each of those groups of vertical lines which were essentially the same as the intervals between the leading edges of the various lines in the quadrants on an authentic U. S. bill, and would have to leave blank the area which is between our-~enths and five-tenths of an inch long and which immediately follows the leading border. Further, he would have to make the intensity of the magnetic material on that bill high enough to exceed the thresholds of transistor 682 in the BORDER sub-block 516~and of the phase locked loops in the FREQUENC~ DETECTORS 792 and 794 and yet be low enough to be below the threshold level of the transistor 338 in the OVERLEVEL SENSING sub-block 296 of Fig. 7. As a result, any such person would have an exceedingly difficult, virtually-impossible task.
Whereas the drawing and accompanying descrip-tion have shown and described a preferred embodiment of : the present invention, it should be apparent to those skilled in the art that various changes may be made in the form of the new invention without affecting the scope thereof.

Claims (14)

1. A validator for documents which comprises a sensor that can respond to relative move-ment between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a signal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit.

2. A validator as claimed in claim 1 wherein the first said sub-circuit includes a threshold detector, a timer and an output element, and wherein said output element can develop the first said output signal only when said threshold device does not receive signals from said sensor for a length of time controlled by said timer.

3. A validator as claimed in claim 1 wherein the first said sub-circuit includes an electronic "latch" which responds to the development of the first said output signal to become latched and thereby enables said first said sub-circuit to remain in its latched state even though a further signal is supplied to said first said sub-circuit.

4. A validator which comprises a sensor, means to provide relative movement between an authentic document and said sensor to enable said sensor to respond to markings on said authentic document to develop signals, a pattern detector which can develop a pattern signal as a given pattern, defined on said authentic document by some of said markings, is being sensed by said sensor, other of said markings on said document defining a border-like area which can cause said sensor to develop further signals, a sub-circuit that responds to said further signals which said sensor develops as said sensor senses said border-like area to develop a border signal, and means which responds to said border signal to enable utilization of said pattern signal, said means keeping said pattern signal from being utilized if said sub-circuit does not develop said border signal.

5. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a signal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output sig-nal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, an inhibit circuit which can respond to a given signal to permit operation of said means but to inhibit the utilization of signals from said second sub-circuit, and said inhibit circuit responding to a further signal to permit operation of said means but to inhibit the utilization of signals from the first said sub-circuit.

6. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further mark-ings are not sensed by said sensor within said predeter-mined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said out-put signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, said sensor be-ing a magnetic sensor, a reversing circuit which responds to actuation thereof to cause said means to reverse and thereby return said document to the person who inserted it, a switch that responds to the insertion of a document to initiate actuation of said means, a threshold device which responds to signals from said magnetic sensor to determine whether the intensity of the magnetic material in the ink on said document is great enough to be com-parable to that on an authentic document, and a second threshold device which will determine whether the amount of magnetic material in the ink on said document appre-ciably exceeds the amount on an authentic document, and said reversing circuit responding to a signal from said second threshold device or to the absence of a signal from the first said threshold device to become actuated and to reverse said means, and further means connecting the outputs of said threshold devices to said reversing circuit.

7. A validator for documents which comprises a sensor that can sense markings on a document to develop signals, said sensor responding to one group of markings on said document to develop one signal and responding to another group of markings on said document to develop an-other signal, a sub-circuit which responds to said one signal to develop an output signal but which delays the developing of said output signal for at least a predeter-mined minimum length of time after the termination of said one signal, a second sub-circuit which responds to said other signal to develop a utilizable output signal, and means which will enable utilization of said utilizable output signal only if the first said output signal is developed by the first said sub-circuit before said util-izable output signal is developed by said second sub-circuit, whereby said utilizable output signal will not be utilized if said sensor develops said other signal during the sensing of a document which does not have said one group of markings thereon in position to be sensed by said sensor before said sensor senses said other group of markings.

8. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, a second sensor that can respond to relative movement be-tween itself and markings on said document to develop sig-nals, means to provide relative movement between the first said sensor and said document and also to provide relative movement between said second sensor and said document to enable said first said sensor to respond to one group of markings on said document to develop a signal and there-after to respond to another group of markings on said document to develop another signal, said one group and said other group of markings being spaced apart and being sensed consecutively by said first said sensor, said rel-ative movement between said second sensor and said docu-ment enabling said second sensor to respond to a third group of markings on said document to develop a third signal and thereafter to respond to a fourth group of markings on said document to develop a fourth signal, said third and said fourth groups of markings being spaced apart and being sensed consecutively by said second sensor, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the develop-ment of the first said output signal to enable utiliza-tion of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, at least one area which includes one of said one group or of said other group of markings being physi-cally in register with at least one area which includes one of said third or of said fourth groups of markings, and said sensors being spaced longitudinally relative to each other to enable said sensors to develop time-spaced sequential signals during the sensing of said one areas which are physically in register with each other.

9. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further mark-ings are not sensed by said sensor within said predeter-mined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said out-put signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output sig-nal is developed by said second sub-circuit, an accept circuit, an inhibit circuit that is adapted to keep said accept circuit from developing an accept signal, and a further circuit which responds to signals developed by said sensor and which causes said inhibit circuit to inhibit said accept circuit if said further circuit re-ceives signals from said sensor while said sensor is sensing the area between said one group of markings and said other groups of markings on said document.

10. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if fur-ther markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is devel-oped by the first said sub-circuit before said second output signal is developed by said second sub-circuit, a "line cording" circuit that comprises a selectively-conductive device, an output sub-circuit that is con-nected to the output of said selectively-conductive device, and an input sub-circuit that is connected to the input of said selectively-conductive device, said input sub-circuit being connectable to a suitable vol-tage, said output sub-circuit being connectable to a lower voltage, said suitable voltage and said lower vol-tage responding to prolonged removal of power from said "line cording" circuit to decrease, and a voltage-dropping element in said input sub-circuit, said voltage-dropping element normally applying a voltage to the input of said selectively-conductive device which will tend to hold said selectively-conductive device in one state but said voltage-dropping element responding to reductions in said suitable voltage which can occur as power is removed from said "line cording" circuit to apply a different voltage to said input of said selectively-conductive device which will cause said selectively-conductive device to change to a different state, said voltage-dropping element applying said different voltage to said input of said selectively-conductive device be-fore any effective decrease could occur in said lower voltage as power is removed from said "line cording" cir-cuit, and said selectively-conductive device remaining in said different state if said lower voltage effective-ly decreases and continuing to remain in said different state until said lower voltage returns to its normal level.

11. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further mark-ings are not sensed by said sensor within said predeter-mined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second out-put signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, position-sensing means which develops a positional signal when a predetermined positional relationship occurs between said position-sensing means and said document, a timer that includes a pulse source, a counter, said timer responding to said positional signal from said position-sensing means to cause said counter to start counting, and means that will develop a non-accept signal if said position-sensing means is still providing said positional signal but said sensor has not provided said predetermined signal prior to the time the count in said counter reaches a predeter-mined value.

12. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further mark-ings are not sensed by said sensor within said predeter-mined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second out-put signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, the first said signal including a number of separate and distinct pulses, and a counter which receives and counts said pulses, said counter providing an output signal if the number of pulses provided by said sensor in response to said one group of markings equals, or differs by one from, said predetermined number of pulses.

13. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a sig-nal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if fur-ther markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is devel-oped by the first said sub-circuit before said second output signal is developed by said second sub-circuit, the first said signal having a predetermined frequency, and a phase locked loop which receives said first said signal and which responds to said first said signal to develop an output signal, said phase locked loop not responding to a signal from said sensor which has an appreciably different frequency.

14. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, a second sensor that can respond to relative movement be-tween itself and markings on said document to develop signals, means to provide relative movement between the first said sensor and said document and also to provide relative movement between said second sensor and said document to enable said first said sensor to respond to one group of markings on said document to develop a sig-nal and thereafter to respond to another group of mark-ings on said document to develop another signal, said relative movement between said second sensor and said document enabling said second sensor to respond to a third group of markings on said document to develop a third signal and thereafter to respond to a fourth group of markings on said document to develop a fourth signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predeter-mined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to de-velop a second output signal, means responsive to the de-velopment of the first said output signal to enable ut-ilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit, said document being a bill having a portrait and the background for said portrait including said other group of markings and said fourth group of markings, said first said sensor and said second sensor being magnetic sensors and being spaced apart longitud-inally of each other, the longitudinal spacing of said magnetic sensors locating the air gaps of said magnetic sensors so both of said air gaps can not simultaneously engage portions of said portrait background, whereby said magnetic sensors will respond to said relative movement to provide time-spaced signals.