CA1026868A - Memory write circuit - Google Patents

Memory write circuit

Info

Publication number
CA1026868A
CA1026868A CA159,657A CA159657A CA1026868A CA 1026868 A CA1026868 A CA 1026868A CA 159657 A CA159657 A CA 159657A CA 1026868 A CA1026868 A CA 1026868A
Authority
CA
Canada
Prior art keywords
write circuit
memory write
memory
circuit
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA159,657A
Other languages
English (en)
French (fr)
Other versions
CA159657S (en
Inventor
William L. Martino (Jr.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1026868A publication Critical patent/CA1026868A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
CA159,657A 1972-01-03 1972-12-21 Memory write circuit Expired CA1026868A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21597772A 1972-01-03 1972-01-03

Publications (1)

Publication Number Publication Date
CA1026868A true CA1026868A (en) 1978-02-21

Family

ID=22805158

Family Applications (1)

Application Number Title Priority Date Filing Date
CA159,657A Expired CA1026868A (en) 1972-01-03 1972-12-21 Memory write circuit

Country Status (7)

Country Link
US (1) US3747076A (en, 2012)
JP (1) JPS5733630B2 (en, 2012)
AU (1) AU466581B2 (en, 2012)
CA (1) CA1026868A (en, 2012)
DE (1) DE2300187C2 (en, 2012)
FR (1) FR2167584B1 (en, 2012)
GB (1) GB1390286A (en, 2012)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5223712B2 (en, 2012) * 1972-06-26 1977-06-25
US3796893A (en) * 1972-08-28 1974-03-12 Motorola Inc Peripheral circuitry for dynamic mos rams
US4011549A (en) * 1975-09-02 1977-03-08 Motorola, Inc. Select line hold down circuit for MOS memory decoder
US4048629A (en) * 1975-09-02 1977-09-13 Motorola, Inc. Low power mos ram address decode circuit
JPS58212518A (ja) * 1982-05-17 1983-12-10 Sumikin Coke Co Ltd 輸送物の二分割方法および装置
JPH0810550B2 (ja) * 1986-09-09 1996-01-31 日本電気株式会社 バツフア回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3594736A (en) * 1968-11-29 1971-07-20 Motorola Inc Mos read-write system
US3617772A (en) * 1969-07-09 1971-11-02 Ibm Sense amplifier/bit driver for a memory cell
US3651334A (en) * 1969-12-08 1972-03-21 American Micro Syst Two-phase ratioless logic circuit with delayless output
US3656118A (en) * 1970-05-01 1972-04-11 Cogar Corp Read/write system and circuit for semiconductor memories

Also Published As

Publication number Publication date
JPS5733630B2 (en, 2012) 1982-07-17
DE2300187A1 (de) 1973-07-26
AU4976772A (en) 1974-06-13
JPS4879940A (en, 2012) 1973-10-26
GB1390286A (en) 1975-04-09
US3747076A (en) 1973-07-17
FR2167584B1 (en, 2012) 1977-07-29
FR2167584A1 (en, 2012) 1973-08-24
AU466581B2 (en) 1975-10-30
DE2300187C2 (de) 1987-03-05

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