CA1017872A - Dynamic storage hierarchy system - Google Patents

Dynamic storage hierarchy system

Info

Publication number
CA1017872A
CA1017872A CA210,637A CA210637A CA1017872A CA 1017872 A CA1017872 A CA 1017872A CA 210637 A CA210637 A CA 210637A CA 1017872 A CA1017872 A CA 1017872A
Authority
CA
Canada
Prior art keywords
dynamic storage
storage hierarchy
hierarchy system
dynamic
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA210,637A
Other languages
English (en)
Other versions
CA210637S (en
Inventor
Gerold B. Hasler
Robert R. Fuqua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1017872A publication Critical patent/CA1017872A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA210,637A 1973-10-23 1974-10-03 Dynamic storage hierarchy system Expired CA1017872A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00408958A US3840863A (en) 1973-10-23 1973-10-23 Dynamic storage hierarchy system

Publications (1)

Publication Number Publication Date
CA1017872A true CA1017872A (en) 1977-09-20

Family

ID=23618458

Family Applications (1)

Application Number Title Priority Date Filing Date
CA210,637A Expired CA1017872A (en) 1973-10-23 1974-10-03 Dynamic storage hierarchy system

Country Status (7)

Country Link
US (1) US3840863A (de)
JP (1) JPS5322409B2 (de)
CA (1) CA1017872A (de)
DE (1) DE2445617C2 (de)
FR (1) FR2248577B1 (de)
GB (1) GB1488043A (de)
IT (1) IT1022435B (de)

Families Citing this family (39)

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US3958222A (en) * 1974-06-27 1976-05-18 Ibm Corporation Reconfigurable decoding scheme for memory address signals that uses an associative memory table
US4099230A (en) * 1975-08-04 1978-07-04 California Institute Of Technology High level control processor
US4035778A (en) * 1975-11-17 1977-07-12 International Business Machines Corporation Apparatus for assigning space in a working memory as a function of the history of usage
US4008460A (en) * 1975-12-24 1977-02-15 International Business Machines Corporation Circuit for implementing a modified LRU replacement algorithm for a cache
DE2605617A1 (de) * 1976-02-12 1977-08-18 Siemens Ag Schaltungsanordnung zum adressieren von daten
US4084230A (en) * 1976-11-29 1978-04-11 International Business Machines Corporation Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
GB2055233B (en) * 1977-12-22 1982-11-24 Honeywell Inf Systems Data processing system including a cache store
US4214303A (en) * 1977-12-22 1980-07-22 Honeywell Information Systems Inc. Word oriented high speed buffer memory system connected to a system bus
DE2842288A1 (de) * 1978-09-28 1980-04-17 Siemens Ag Datentransferschalter mit assoziativer adressauswahl in einem virtuellen speicher
US4268907A (en) * 1979-01-22 1981-05-19 Honeywell Information Systems Inc. Cache unit bypass apparatus
JPS5619575A (en) * 1979-07-25 1981-02-24 Fujitsu Ltd Data processing system having hierarchy memory
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4441155A (en) * 1981-11-23 1984-04-03 International Business Machines Corporation Page controlled cache directory addressing
US4430712A (en) * 1981-11-27 1984-02-07 Storage Technology Corporation Adaptive domain partitioning of cache memory space
IT1153611B (it) * 1982-11-04 1987-01-14 Honeywell Inf Systems Procedimento di mappatura della memoria in sistema di elaborazione dati
US4631660A (en) * 1983-08-30 1986-12-23 Amdahl Corporation Addressing system for an associative cache memory
US4916603A (en) * 1985-03-18 1990-04-10 Wang Labortatories, Inc. Distributed reference and change table for a virtual memory system
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
JPH0673114B2 (ja) * 1987-03-31 1994-09-14 日本電気株式会社 キヤツシユ制御装置
US5155834A (en) * 1988-03-18 1992-10-13 Wang Laboratories, Inc. Reference and change table storage system for virtual memory data processing system having a plurality of processors accessing common memory
CA1301367C (en) * 1988-03-24 1992-05-19 David James Ayers Pseudo set-associative memory cacheing arrangement
US5257395A (en) * 1988-05-13 1993-10-26 International Business Machines Corporation Methods and circuit for implementing and arbitrary graph on a polymorphic mesh
US5060136A (en) * 1989-01-06 1991-10-22 International Business Machines Corp. Four-way associative cache with dlat and separately addressable arrays used for updating certain bits without reading them out first
US5455775A (en) * 1993-01-25 1995-10-03 International Business Machines Corporation Computer design system for mapping a logical hierarchy into a physical hierarchy
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5388247A (en) * 1993-05-14 1995-02-07 Digital Equipment Corporation History buffer control to reduce unnecessary allocations in a memory stream buffer
US6026470A (en) * 1997-04-14 2000-02-15 International Business Machines Corporation Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
US5983322A (en) * 1997-04-14 1999-11-09 International Business Machines Corporation Hardware-managed programmable congruence class caching mechanism
GB2368415B (en) * 1998-07-21 2002-10-30 Seagate Technology Llc Improved memory system apparatus and method
US6205511B1 (en) * 1998-09-18 2001-03-20 National Semiconductor Corp. SDRAM address translator
US6728823B1 (en) * 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
US7080207B2 (en) * 2002-04-30 2006-07-18 Lsi Logic Corporation Data storage apparatus, system and method including a cache descriptor having a field defining data in a cache block
WO2008010146A2 (en) * 2006-07-14 2008-01-24 Nxp B.V. Dual interface memory arrangement and method
KR100764052B1 (ko) * 2006-08-03 2007-10-08 삼성전자주식회사 유동적 어드레스 바운더리를 갖는 플래시 메모리 장치 및그것의 프로그램 방법
US20110321052A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Mutli-priority command processing among microcontrollers
US20140189244A1 (en) * 2013-01-02 2014-07-03 Brian C. Grayson Suppression of redundant cache status updates
US20220404975A1 (en) * 2014-04-24 2022-12-22 Executive Advisory Firm Llc Apparatus, system, and method of byte addressable and block addressable storage and retrieval of data to and from non-volatile storage memory
US10235103B2 (en) * 2014-04-24 2019-03-19 Xitore, Inc. Apparatus, system, and method of byte addressable and block addressable storage and retrival of data to and from non-volatile storage memory
US10592414B2 (en) * 2017-07-14 2020-03-17 International Business Machines Corporation Filtering of redundantly scheduled write passes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing

Also Published As

Publication number Publication date
FR2248577B1 (de) 1976-10-22
JPS5322409B2 (de) 1978-07-08
GB1488043A (en) 1977-10-05
US3840863A (en) 1974-10-08
DE2445617C2 (de) 1983-01-20
DE2445617A1 (de) 1975-04-30
FR2248577A1 (de) 1975-05-16
IT1022435B (it) 1978-03-20
JPS5068748A (de) 1975-06-09

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