BR9902725A - Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers - Google Patents

Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers

Info

Publication number
BR9902725A
BR9902725A BR9902725A BR9902725A BR9902725A BR 9902725 A BR9902725 A BR 9902725A BR 9902725 A BR9902725 A BR 9902725A BR 9902725 A BR9902725 A BR 9902725A BR 9902725 A BR9902725 A BR 9902725A
Authority
BR
Brazil
Prior art keywords
memorization
instructions
reuse
formation
dynamic
Prior art date
Application number
BR9902725A
Other languages
Portuguese (pt)
Inventor
Felipe Maia Galvao Franca
Original Assignee
Coppe Ufrj
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Coppe Ufrj filed Critical Coppe Ufrj
Priority to BR9902725A priority Critical patent/BR9902725A/en
Priority to AU57990/00A priority patent/AU5799000A/en
Priority to PCT/BR2000/000074 priority patent/WO2001004746A1/en
Publication of BR9902725A publication Critical patent/BR9902725A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Patente de Invenção "PROCESSO DE FORMAçãO, MEMORIZAçãO E REUSO, EM TEMPO DE EXECUçãO, DE SEQuêNCIAS DE INSTRUçõES DINâMICAS EM COMPUTADORES'' Trata-se de um processo para a formação, memorização e reuso, em tempo de execução, de seq³ências de instruções dinâmicas com o objetivo de reduzir o número de instruções dinâmicas executadas por um programa, de forma a eliminar a necessidade de reexecução de instruções redundantes (instruções que reutilizam mais de uma vez os mesmos valores para seus operandos de entrada) inclusas na seq³ência quando esta apresentar como argumentos de entrada valores já observados anteriormente e registrados em tabelas de memorização. Este processo não necessita efetuar invalidações em entradas das tabelas de memorização ou possui seu uso limitado a cadeias de instruções dependentes. O processo reduz o número de instruções dinâmicas que devam ser executadas pelo programa alvo, reduzindo desta forma o tempo total de execução do dado programa e mantendo-se a correção dos resultados. A invenção refere-se também a um dispositivo eletrónico para a realização do processo.Invention Patent "FORMATION, MEMORIZATION AND REUSE PROCESS, IN TIME OF EXECUTION, OF DYNAMIC INSTRUCTIONS ON COMPUTERS" It is a process for the formation, memorization and reuse, in execution time, of dynamic instruction sequences in order to reduce the number of dynamic instructions executed by a program, in order to eliminate the need to re-execute redundant instructions (instructions that reuse the same values for its input operands more than once) included in the sequence when it presents as input arguments values already observed previously and recorded in memorization tables. This process does not need to make invalidations in memorization table entries or has its use limited to chains of dependent instructions. The process reduces the number of dynamic instructions that must be executed by the target program, thereby reducing the total time and execution of the given program and maintaining the correction of the results. The invention also relates to an electronic device for carrying out the process.

BR9902725A 1999-07-13 1999-07-13 Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers BR9902725A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
BR9902725A BR9902725A (en) 1999-07-13 1999-07-13 Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers
AU57990/00A AU5799000A (en) 1999-07-13 2000-07-12 Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers
PCT/BR2000/000074 WO2001004746A1 (en) 1999-07-13 2000-07-12 Process of formation, memorization and reuse, in execution time, of sequences of dynamic instructions in computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BR9902725A BR9902725A (en) 1999-07-13 1999-07-13 Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers

Publications (1)

Publication Number Publication Date
BR9902725A true BR9902725A (en) 2001-03-06

Family

ID=4072777

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9902725A BR9902725A (en) 1999-07-13 1999-07-13 Process of formation, memorization and reuse, in execution time, of dynamic instruction sequences in computers

Country Status (3)

Country Link
AU (1) AU5799000A (en)
BR (1) BR9902725A (en)
WO (1) WO2001004746A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9286043B2 (en) 2013-03-15 2016-03-15 Microsoft Technology Licensing, Llc Software build optimization
US9679342B2 (en) * 2013-07-12 2017-06-13 Arm Limited Result data stream coding for repeating workloads
US10540178B2 (en) * 2016-09-14 2020-01-21 Intel Corporation Eliminating redundant stores using a protection designator and a clear designator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463973A3 (en) * 1990-06-29 1993-12-01 Digital Equipment Corp Branch prediction in high performance processor
US5619662A (en) * 1992-11-12 1997-04-08 Digital Equipment Corporation Memory reference tagging
JPH06348595A (en) * 1993-06-07 1994-12-22 Hitachi Ltd Cache device
US5704053A (en) * 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
US5649178A (en) * 1995-06-07 1997-07-15 International Business Machines, Corporation Apparatus and method for storing and initializing branch prediction with selective information transfer
US5845103A (en) * 1997-06-13 1998-12-01 Wisconsin Alumni Research Foundation Computer with dynamic instruction reuse

Also Published As

Publication number Publication date
AU5799000A (en) 2001-01-30
WO2001004746A1 (en) 2001-01-18

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