BR9901215B1 - Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução - Google Patents

Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução

Info

Publication number
BR9901215B1
BR9901215B1 BRPI9901215-4B1A BR9901215A BR9901215B1 BR 9901215 B1 BR9901215 B1 BR 9901215B1 BR 9901215 A BR9901215 A BR 9901215A BR 9901215 B1 BR9901215 B1 BR 9901215B1
Authority
BR
Brazil
Prior art keywords
decoding
instruction
instruction code
appliance
coding
Prior art date
Application number
BRPI9901215-4B1A
Other languages
English (en)
Other versions
BR9901215A (pt
Inventor
Srinivas Chennupaty
Lance Hacking
Thomas Huff
Patrice L Roussel
Shreekant S Thakkar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9901215A publication Critical patent/BR9901215A/pt
Publication of BR9901215B1 publication Critical patent/BR9901215B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
BRPI9901215-4B1A 1998-03-31 1999-03-30 Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução BR9901215B1 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/053,391 US6014735A (en) 1998-03-31 1998-03-31 Instruction set extension using prefixes

Publications (2)

Publication Number Publication Date
BR9901215A BR9901215A (pt) 2000-01-11
BR9901215B1 true BR9901215B1 (pt) 2013-12-24

Family

ID=21983905

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI9901215-4B1A BR9901215B1 (pt) 1998-03-31 1999-03-30 Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução

Country Status (7)

Country Link
US (1) US6014735A (pt)
EP (1) EP0947919B1 (pt)
BR (1) BR9901215B1 (pt)
DE (1) DE69925410T2 (pt)
HK (1) HK1024962A1 (pt)
SG (1) SG77229A1 (pt)
TW (1) TW445431B (pt)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6189090B1 (en) * 1997-09-17 2001-02-13 Sony Corporation Digital signal processor with variable width instructions
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US6253309B1 (en) 1998-09-21 2001-06-26 Advanced Micro Devices, Inc. Forcing regularity into a CISC instruction set by padding instructions
US6275927B2 (en) 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes
US6339822B1 (en) 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6240506B1 (en) * 1998-10-02 2001-05-29 Advanced Micro Devices, Inc. Expanding instructions with variable-length operands to a fixed length
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US6763452B1 (en) 1999-01-28 2004-07-13 Ati International Srl Modifying program execution based on profiling
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US8127121B2 (en) * 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8065504B2 (en) * 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US6981132B2 (en) * 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US7089368B2 (en) * 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7000081B2 (en) * 2002-02-12 2006-02-14 Ip-First, Llc Write back and invalidate mechanism for multiple cache lines
US7080211B2 (en) 2002-02-12 2006-07-18 Ip-First, Llc Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7080210B2 (en) 2002-02-12 2006-07-18 Ip-First, Llc Microprocessor apparatus and method for exclusive prefetch of a cache line from memory
US7089371B2 (en) * 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory
US7315921B2 (en) * 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7395412B2 (en) 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7111125B2 (en) 2002-04-02 2006-09-19 Ip-First, Llc Apparatus and method for renaming a data block within a cache
US7185180B2 (en) 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7380103B2 (en) * 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
JP3769249B2 (ja) * 2002-06-27 2006-04-19 富士通株式会社 命令処理装置および命令処理方法
EP1387256B1 (en) * 2002-07-31 2018-11-21 Texas Instruments Incorporated Program counter adjustment based on the detection of an instruction prefix
EP1387252B1 (en) * 2002-07-31 2019-02-13 Texas Instruments Incorporated Instruction prefix to indicate system commands
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
TWI230899B (en) * 2003-03-10 2005-04-11 Sunplus Technology Co Ltd Processor and method using parity check to proceed command mode switch
US7103754B2 (en) * 2003-03-28 2006-09-05 International Business Machines Corporation Computer instructions for having extended signed displacement fields for finding instruction operands
US7188215B2 (en) 2003-06-19 2007-03-06 Ip-First, Llc Apparatus and method for renaming a cache line
US7139900B2 (en) * 2003-06-23 2006-11-21 Intel Corporation Data packet arithmetic logic devices and methods
US7917734B2 (en) * 2003-06-30 2011-03-29 Intel Corporation Determining length of instruction with multiple byte escape code based on information from other than opcode byte
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
US9311085B2 (en) * 2007-12-30 2016-04-12 Intel Corporation Compiler assisted low power and high performance load handling based on load types
US8028153B2 (en) * 2008-08-14 2011-09-27 International Business Machines Corporation Data dependent instruction decode
US9201801B2 (en) * 2010-09-15 2015-12-01 International Business Machines Corporation Computing device with asynchronous auxiliary execution unit
GB2484489A (en) * 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.
CN103959239B (zh) * 2011-11-30 2017-12-29 英特尔公司 对使用前缀的isa指令的条件执行支持
US9600286B2 (en) 2014-06-30 2017-03-21 International Business Machines Corporation Latent modification instruction for transactional execution
US9448939B2 (en) 2014-06-30 2016-09-20 International Business Machines Corporation Collecting memory operand access characteristics during transactional execution
US9348643B2 (en) 2014-06-30 2016-05-24 International Business Machines Corporation Prefetching of discontiguous storage locations as part of transactional execution
US9336047B2 (en) 2014-06-30 2016-05-10 International Business Machines Corporation Prefetching of discontiguous storage locations in anticipation of transactional execution
US9710271B2 (en) 2014-06-30 2017-07-18 International Business Machines Corporation Collecting transactional execution characteristics during transactional execution
US10761852B2 (en) 2015-09-30 2020-09-01 International Business Machines Corporation Extending data range addressing
US10394568B2 (en) 2015-09-30 2019-08-27 International Business Machines Corporation Exception handling for applications with prefix instructions
US10877759B2 (en) 2015-09-30 2020-12-29 International Business Machines Corporation Managing the capture of information in applications with prefix instructions
US9870305B2 (en) 2015-09-30 2018-01-16 International Business Machines Corporation Debugging of prefixed code
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
US11263014B2 (en) * 2019-08-05 2022-03-01 Arm Limited Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5353420A (en) * 1992-08-10 1994-10-04 Intel Corporation Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor
US5572206A (en) * 1994-07-06 1996-11-05 Microsoft Corporation Data compression method and system
US5768553A (en) * 1995-10-30 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to define DSP instructions
AU1406997A (en) * 1995-12-15 1997-07-14 Intel Corporation Instruction encoding techniques for microcontroller architecture
US5822559A (en) * 1996-01-02 1998-10-13 Advanced Micro Devices, Inc. Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions
US5845102A (en) * 1997-03-03 1998-12-01 Advanced Micro Devices, Inc. Determining microcode entry points and prefix bytes using a parallel logic technique

Also Published As

Publication number Publication date
TW445431B (en) 2001-07-11
DE69925410T2 (de) 2006-05-11
BR9901215A (pt) 2000-01-11
DE69925410D1 (de) 2005-06-30
EP0947919A2 (en) 1999-10-06
EP0947919A3 (en) 2000-09-13
SG77229A1 (en) 2000-12-19
EP0947919B1 (en) 2005-05-25
HK1024962A1 (en) 2000-10-27
US6014735A (en) 2000-01-11

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