BR9901215A - Extensão de conjunto de instruções usando prefixos. - Google Patents

Extensão de conjunto de instruções usando prefixos.

Info

Publication number
BR9901215A
BR9901215A BR9901215-4A BR9901215A BR9901215A BR 9901215 A BR9901215 A BR 9901215A BR 9901215 A BR9901215 A BR 9901215A BR 9901215 A BR9901215 A BR 9901215A
Authority
BR
Brazil
Prior art keywords
code
prefixes
instruction
instruction set
set extension
Prior art date
Application number
BR9901215-4A
Other languages
English (en)
Other versions
BR9901215B1 (pt
Inventor
Srinivas Chennupaty
Lance Hacking
Thomas Huff
Patrice L Roussel
Shreekant S Thakkar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9901215A publication Critical patent/BR9901215A/pt
Publication of BR9901215B1 publication Critical patent/BR9901215B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Patente de Invenção:<B>"EXTENSãO DE CONJUNTO DE INSTRUçõES USANDO PREFIXOS"<D>. A presente invenção descreve-se um metódo e aparelho para codificar uma instrução em um conjunto de instruções que usam um código de prefixo para qualificar um código op de uma instrução existente. Um código op e um código de escapamento são selecionados. O código de escapamento é selecionado tal que ele é diferente do código de prefixo e do código op existente. O código op, o código de escapamento e o código de prefixo são combinados para gerar um código de instrução que representa univocamente a operação realizada pela instrução.
BRPI9901215-4B1A 1998-03-31 1999-03-30 Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução BR9901215B1 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/053,391 US6014735A (en) 1998-03-31 1998-03-31 Instruction set extension using prefixes

Publications (2)

Publication Number Publication Date
BR9901215A true BR9901215A (pt) 2000-01-11
BR9901215B1 BR9901215B1 (pt) 2013-12-24

Family

ID=21983905

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI9901215-4B1A BR9901215B1 (pt) 1998-03-31 1999-03-30 Método para codificar uma primeira instrução em um conjunto de instruções, método para decodificar um código de instrução e aparelho para decodificar um código de instrução

Country Status (7)

Country Link
US (1) US6014735A (pt)
EP (1) EP0947919B1 (pt)
BR (1) BR9901215B1 (pt)
DE (1) DE69925410T2 (pt)
HK (1) HK1024962A1 (pt)
SG (1) SG77229A1 (pt)
TW (1) TW445431B (pt)

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US7089368B2 (en) * 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory
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US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
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US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
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EP1387252B1 (en) * 2002-07-31 2019-02-13 Texas Instruments Incorporated Instruction prefix to indicate system commands
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US7917734B2 (en) * 2003-06-30 2011-03-29 Intel Corporation Determining length of instruction with multiple byte escape code based on information from other than opcode byte
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Also Published As

Publication number Publication date
SG77229A1 (en) 2000-12-19
HK1024962A1 (en) 2000-10-27
DE69925410T2 (de) 2006-05-11
BR9901215B1 (pt) 2013-12-24
EP0947919A2 (en) 1999-10-06
EP0947919B1 (en) 2005-05-25
DE69925410D1 (de) 2005-06-30
EP0947919A3 (en) 2000-09-13
US6014735A (en) 2000-01-11
TW445431B (en) 2001-07-11

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Legal Events

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B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

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B12B Appeal against refusal [chapter 12.2 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 24/12/2013, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

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B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

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