BR8207967A - Circuito integrado em escala de placa com espirais ramificadas - Google Patents

Circuito integrado em escala de placa com espirais ramificadas

Info

Publication number
BR8207967A
BR8207967A BR8207967A BR8207967A BR8207967A BR 8207967 A BR8207967 A BR 8207967A BR 8207967 A BR8207967 A BR 8207967A BR 8207967 A BR8207967 A BR 8207967A BR 8207967 A BR8207967 A BR 8207967A
Authority
BR
Brazil
Prior art keywords
spirals
branched
integrated plate
scale circuit
scale
Prior art date
Application number
BR8207967A
Other languages
English (en)
Inventor
John Terence Chamberlain
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of BR8207967A publication Critical patent/BR8207967A/pt

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511Wafer Test
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
BR8207967A 1981-12-02 1982-11-18 Circuito integrado em escala de placa com espirais ramificadas BR8207967A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB08136339A GB2114782B (en) 1981-12-02 1981-12-02 Branched-spiral wafer-scale integrated circuit
PCT/GB1982/000328 WO1983002019A1 (en) 1981-12-02 1982-11-18 Branched-spiral wafer-scale integrated circuit

Publications (1)

Publication Number Publication Date
BR8207967A true BR8207967A (pt) 1983-10-04

Family

ID=10526329

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8207967A BR8207967A (pt) 1981-12-02 1982-11-18 Circuito integrado em escala de placa com espirais ramificadas

Country Status (7)

Country Link
US (1) US4519035A (pt)
EP (1) EP0080834B1 (pt)
JP (1) JPS58502077A (pt)
BR (1) BR8207967A (pt)
DE (1) DE3269020D1 (pt)
GB (1) GB2114782B (pt)
WO (1) WO1983002019A1 (pt)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2111267B (en) * 1981-12-08 1985-10-16 Burroughs Corp Constant-distance structure polycellular very large scale integrated circuit
WO1983002163A1 (en) * 1981-12-18 1983-06-23 Burroughs Corp Branched labyrinth wafer scale integrated circuit
GB8403229D0 (en) * 1984-02-07 1984-03-14 Standard Telephones Cables Ltd Wafer scale integrated circuit
DE3681463D1 (de) * 1985-01-29 1991-10-24 Secr Defence Brit Verarbeitungszelle fuer fehlertolerante matrixanordnungen.
GB2174518B (en) * 1985-04-15 1989-06-21 Sinclair Res Ltd Wafer scale integrated circuit
GB2177825B (en) * 1985-07-12 1989-07-26 Anamartic Ltd Control system for chained circuit modules
GB2181280B (en) * 1985-09-30 1989-09-06 Anamartic Ltd Improvements relating to wafer scale integrated circuits
GB2181870B (en) * 1985-10-14 1988-11-23 Anamartic Ltd Control circuit for chained circuit modules
GB2185836B (en) * 1986-01-28 1988-11-16 Anamartic Ltd Improvements relating to wafer scale integrated circuits
EP0424979A3 (en) 1986-03-18 1991-07-03 Anamartic Limited Random address system for circuit modules
GB8612454D0 (en) * 1986-05-22 1986-07-02 Inmos Ltd Redundancy scheme for multi-stage apparatus
US5287345A (en) * 1988-02-04 1994-02-15 The City University Data handling arrays
GB8825780D0 (en) * 1988-11-03 1988-12-07 Microcomputer Tech Serv Digital computer
US5020059A (en) * 1989-03-31 1991-05-28 At&T Bell Laboratories Reconfigurable signal processor
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
GB2244826A (en) * 1990-06-08 1991-12-11 Anamartic Ltd Linking circuit modules
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5399505A (en) * 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
US5594273A (en) * 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
US6577148B1 (en) 1994-08-31 2003-06-10 Motorola, Inc. Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
WO2007099181A1 (es) * 2006-02-28 2007-09-07 Intel Corporation Mejora de la fiabilidad de un procesador de muchos nucleos
US9470760B2 (en) * 2011-04-01 2016-10-18 International Business Machines Corporation Functional ASIC verification using initialization microcode sequence

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665406A (en) * 1970-04-13 1972-05-23 Bunker Ramo Automatic polling systems
US4060713A (en) * 1971-06-23 1977-11-29 The Perkin-Elmer Corporation Analysis of images
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US3794983A (en) * 1973-04-17 1974-02-26 K Sahin Communication method and network system
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4020469A (en) * 1975-04-09 1977-04-26 Frank Manning Programmable arrays
US4037205A (en) * 1975-05-19 1977-07-19 Sperry Rand Corporation Digital memory with data manipulation capabilities
US4191996A (en) * 1977-07-22 1980-03-04 Chesley Gilman D Self-configurable computer and memory system
US4215401A (en) * 1978-09-28 1980-07-29 Environmental Research Institute Of Michigan Cellular digital array processor

Also Published As

Publication number Publication date
WO1983002019A1 (en) 1983-06-09
GB2114782B (en) 1985-06-05
US4519035A (en) 1985-05-21
DE3269020D1 (en) 1986-03-20
JPS58502077A (ja) 1983-12-01
EP0080834B1 (en) 1986-02-05
EP0080834A2 (en) 1983-06-08
EP0080834A3 (en) 1983-07-13
GB2114782A (en) 1983-08-24

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)