BR8200486A - Metodo para atribuir dinamicamente memoria supervisionada por lru/mru entre processos sequenciais concorrentes - Google Patents

Metodo para atribuir dinamicamente memoria supervisionada por lru/mru entre processos sequenciais concorrentes

Info

Publication number
BR8200486A
BR8200486A BR8200486A BR8200486A BR8200486A BR 8200486 A BR8200486 A BR 8200486A BR 8200486 A BR8200486 A BR 8200486A BR 8200486 A BR8200486 A BR 8200486A BR 8200486 A BR8200486 A BR 8200486A
Authority
BR
Brazil
Prior art keywords
mru
lru
supervised
competing
sequential processes
Prior art date
Application number
BR8200486A
Other languages
English (en)
Portuguese (pt)
Inventor
Richard Lewis Mattson
Antenor Rodriguez Rosell Juan
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8200486A publication Critical patent/BR8200486A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR8200486A 1981-02-19 1982-01-29 Metodo para atribuir dinamicamente memoria supervisionada por lru/mru entre processos sequenciais concorrentes BR8200486A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23580681A 1981-02-19 1981-02-19

Publications (1)

Publication Number Publication Date
BR8200486A true BR8200486A (pt) 1982-11-30

Family

ID=22886982

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8200486A BR8200486A (pt) 1981-02-19 1982-01-29 Metodo para atribuir dinamicamente memoria supervisionada por lru/mru entre processos sequenciais concorrentes

Country Status (6)

Country Link
EP (1) EP0058846B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS57138080A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU544005B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BR (1) BR8200486A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1169572A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3278772D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048553A (ja) * 1983-08-25 1985-03-16 Fujitsu Ltd ディスクキャッシュの性能評価方式
JPH02123269U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1989-03-24 1990-10-09
JPH03184572A (ja) * 1989-12-13 1991-08-12 Kawaguchi Giken:Kk ゴルフスイング練習用具
TW212840B (en) * 1992-04-22 1993-09-11 Ibm Multi-bit vector for page aging
US5761739A (en) * 1993-06-08 1998-06-02 International Business Machines Corporation Methods and systems for creating a storage dump within a coupling facility of a multisystem enviroment
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange

Also Published As

Publication number Publication date
EP0058846A3 (en) 1986-03-19
AU544005B2 (en) 1985-05-16
EP0058846A2 (en) 1982-09-01
JPS6136668B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-08-19
CA1169572A (en) 1984-06-19
AU7942182A (en) 1982-08-26
EP0058846B1 (en) 1988-07-13
DE3278772D1 (en) 1988-08-18
JPS57138080A (en) 1982-08-26

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