BR8005974A - Dispositivo de controle em um computador eletronico de dados para a execucao de operacaoes forcadas - Google Patents

Dispositivo de controle em um computador eletronico de dados para a execucao de operacaoes forcadas

Info

Publication number
BR8005974A
BR8005974A BR8005974A BR8005974A BR8005974A BR 8005974 A BR8005974 A BR 8005974A BR 8005974 A BR8005974 A BR 8005974A BR 8005974 A BR8005974 A BR 8005974A BR 8005974 A BR8005974 A BR 8005974A
Authority
BR
Brazil
Prior art keywords
control device
electronic data
data computer
performing forced
forced operations
Prior art date
Application number
BR8005974A
Other languages
English (en)
Inventor
D Bock
D Bazlen
J Hajdu
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=6081213&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=BR8005974(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Ibm filed Critical Ibm
Publication of BR8005974A publication Critical patent/BR8005974A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
BR8005974A 1979-09-19 1980-09-18 Dispositivo de controle em um computador eletronico de dados para a execucao de operacaoes forcadas BR8005974A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2937777A DE2937777C2 (de) 1979-09-19 1979-09-19 Steuereinrichtung in einer elektronischen Datenverarbeitungsanlage zur Programmunterbrechung und für die Durchführung erzwungener Operationen

Publications (1)

Publication Number Publication Date
BR8005974A true BR8005974A (pt) 1981-03-31

Family

ID=6081213

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8005974A BR8005974A (pt) 1979-09-19 1980-09-18 Dispositivo de controle em um computador eletronico de dados para a execucao de operacaoes forcadas

Country Status (5)

Country Link
US (1) US4398247A (pt)
EP (1) EP0025855B1 (pt)
JP (1) JPS5647844A (pt)
BR (1) BR8005974A (pt)
DE (2) DE2937777C2 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441153A (en) * 1981-04-03 1984-04-03 International Business Machines Corp. Instruction register content modification using plural input gates and a data flow register
US4646269A (en) * 1984-09-18 1987-02-24 Monolithic Memories, Inc. Multiple programmable initialize words in a programmable read only memory
KR900003591B1 (ko) * 1985-04-08 1990-05-26 가부시기 가이샤 히다찌 세이사꾸쇼 데이터 처리장치
JPS61269734A (ja) * 1985-05-23 1986-11-29 Hitachi Ltd マイクロプログラム制御方式
US5226127A (en) * 1989-04-07 1993-07-06 Intel Corporation Method and apparatus providing for conditional execution speed-up in a computer system through substitution of a null instruction for a synchronization instruction under predetermined conditions
DE69127992T2 (de) * 1990-04-20 1998-06-04 Hitachi Ltd Mikroprozessor zur Buszykluseinfügung zwecks Informationslieferung für eine Emulation
JPH0474229A (ja) * 1990-07-17 1992-03-09 Toshiba Corp 情報処理装置
US5619408A (en) * 1995-02-10 1997-04-08 International Business Machines Corporation Method and system for recoding noneffective instructions within a data processing system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL254346A (pt) * 1959-07-30
US3422404A (en) * 1966-02-23 1969-01-14 David E Ferguson Apparatus and method for decoding operation codes in digital computers
US3718912A (en) * 1970-12-22 1973-02-27 Ibm Instruction execution unit
US3889242A (en) * 1971-10-04 1975-06-10 Burroughs Corp Modifiable computer function decoder
FR2226079A5 (pt) * 1973-04-13 1974-11-08 Honeywell Bull Soc Ind
US3938104A (en) * 1974-01-07 1976-02-10 Texas Instruments Incorporated System for modifying a logic controller instruction set
JPS5245232A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Micro program modification circuit
US4063081A (en) * 1976-06-08 1977-12-13 Honeywell Computer apparatus
US4064554A (en) * 1976-08-16 1977-12-20 Texas Instruments Incorporated Microcomputer with code conversion
US4142246A (en) * 1976-12-23 1979-02-27 Fuji Electric Company, Ltd. Sequence controller with dynamically changeable program
US4291371A (en) * 1979-01-02 1981-09-22 Honeywell Information Systems Inc. I/O Request interrupt mechanism
US4306289A (en) * 1980-02-04 1981-12-15 Western Electric Company, Inc. Digital computer having code conversion apparatus for an encrypted program

Also Published As

Publication number Publication date
DE2937777C2 (de) 1982-04-08
DE3072139D1 (en) 1989-02-02
DE2937777A1 (de) 1981-03-26
EP0025855A3 (en) 1981-09-16
JPS638493B2 (pt) 1988-02-23
EP0025855A2 (de) 1981-04-01
EP0025855B1 (de) 1988-12-28
US4398247A (en) 1983-08-09
JPS5647844A (en) 1981-04-30

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