BR112023026704A2 - Arquitetura de computação em memória (cim) e fluxo de dados que suportam uma rede neural convolucional de profundidade (cnn) - Google Patents

Arquitetura de computação em memória (cim) e fluxo de dados que suportam uma rede neural convolucional de profundidade (cnn)

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Publication number
BR112023026704A2
BR112023026704A2 BR112023026704A BR112023026704A BR112023026704A2 BR 112023026704 A2 BR112023026704 A2 BR 112023026704A2 BR 112023026704 A BR112023026704 A BR 112023026704A BR 112023026704 A BR112023026704 A BR 112023026704A BR 112023026704 A2 BR112023026704 A2 BR 112023026704A2
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BR
Brazil
Prior art keywords
cim
neural network
cnn
architecture
memory computing
Prior art date
Application number
BR112023026704A
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English (en)
Inventor
Ren Li
Original Assignee
Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023026704A2 publication Critical patent/BR112023026704A2/pt

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G06F17/153—Multidimensional correlation or convolution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Biophysics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Image Analysis (AREA)

Abstract

arquitetura de computação em memória (cim) e fluxo de dados que suportam uma rede neural convolucional de profundidade (cnn). certos aspectos fornecem um aparelho para processamento de sinal em uma rede neural. o aparelho inclui, de modo geral, um primeiro conjunto de células de computação em memória (cim) configurado como um primeiro kernel para uma computação de rede neural, sendo que o primeiro conjunto de células de cim compreende uma ou mais primeiras colunas e uma primeira pluralidade de fileiras de uma matriz de cim, e um segundo conjunto de células de cim configurado como um segundo kernel para a computação de rede neural, sendo que o segundo conjunto de células de cim compreende uma ou mais segundas colunas e uma segunda pluralidade de fileiras da matriz de cim. em alguns aspectos, a uma ou mais primeiras colunas são diferentes da uma ou mais segundas colunas e a primeira pluralidade de fileiras é diferente da segunda pluralidade de fileiras.
BR112023026704A 2021-06-29 2022-06-28 Arquitetura de computação em memória (cim) e fluxo de dados que suportam uma rede neural convolucional de profundidade (cnn) BR112023026704A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/361,784 US20220414444A1 (en) 2021-06-29 2021-06-29 Computation in memory (cim) architecture and dataflow supporting a depth-wise convolutional neural network (cnn)
PCT/US2022/073230 WO2023279002A1 (en) 2021-06-29 2022-06-28 Computation in memory (cim) architecture and dataflow supporting a depth- wise convolutional neural network (cnn)

Publications (1)

Publication Number Publication Date
BR112023026704A2 true BR112023026704A2 (pt) 2024-03-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023026704A BR112023026704A2 (pt) 2021-06-29 2022-06-28 Arquitetura de computação em memória (cim) e fluxo de dados que suportam uma rede neural convolucional de profundidade (cnn)

Country Status (7)

Country Link
US (1) US20220414444A1 (pt)
EP (1) EP4364047A1 (pt)
KR (1) KR20240025523A (pt)
CN (1) CN117546178A (pt)
BR (1) BR112023026704A2 (pt)
TW (1) TW202324210A (pt)
WO (1) WO2023279002A1 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114298297A (zh) * 2021-11-04 2022-04-08 清华大学 存内计算装置、芯片及电子设备
US11935586B2 (en) * 2022-02-11 2024-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method for computing-in-memory (CIM)
CN117494651A (zh) * 2023-11-14 2024-02-02 合芯科技(苏州)有限公司 基于机器学习的sram位单元的优化设计方法、装置、介质及终端

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11202110769RA (en) * 2019-03-28 2021-10-28 Agency Science Tech & Res A system for mapping a neural network architecture onto a computing core and a method of mapping a neural network architecture onto a computing core
WO2021050590A1 (en) * 2019-09-09 2021-03-18 Qualcomm Incorporated Systems and methods for modifying neural networks for binary processing applications
US11562205B2 (en) * 2019-09-19 2023-01-24 Qualcomm Incorporated Parallel processing of a convolutional layer of a neural network with compute-in-memory array

Also Published As

Publication number Publication date
US20220414444A1 (en) 2022-12-29
WO2023279002A1 (en) 2023-01-05
CN117546178A (zh) 2024-02-09
EP4364047A1 (en) 2024-05-08
TW202324210A (zh) 2023-06-16
KR20240025523A (ko) 2024-02-27

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