BR112023026172A2 - Computação em arquitetura de acelerador de aprendizado de máquina baseado em memória - Google Patents

Computação em arquitetura de acelerador de aprendizado de máquina baseado em memória

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Publication number
BR112023026172A2
BR112023026172A2 BR112023026172A BR112023026172A BR112023026172A2 BR 112023026172 A2 BR112023026172 A2 BR 112023026172A2 BR 112023026172 A BR112023026172 A BR 112023026172A BR 112023026172 A BR112023026172 A BR 112023026172A BR 112023026172 A2 BR112023026172 A2 BR 112023026172A2
Authority
BR
Brazil
Prior art keywords
machine learning
computing
memory
based machine
accelerator architecture
Prior art date
Application number
BR112023026172A
Other languages
English (en)
Inventor
Ren Li
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023026172A2 publication Critical patent/BR112023026172A2/pt

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Mathematical Optimization (AREA)
  • Neurology (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Stored Programmes (AREA)

Abstract

computação em arquitetura de acelerador de aprendizado de máquina baseado em memória. certos aspectos da presente revelação fornecem técnicas para processar dados de modelo de aprendizado de máquina com um acelerador de tarefa de aprendizado de máquina, incluindo: configurar uma ou mais unidades de processamento de sinal (spus) do acelerador de tarefa de aprendizado de máquina para processar um modelo de aprendizado de máquina; fornecer dados de entrada de modelo para uma ou mais spus; processar os dados de entrada de modelo com o modelo de aprendizado de máquina com o uso da uma ou mais spus configuradas; e receber dados de saída da uma ou mais spus configuradas.
BR112023026172A 2021-06-25 2022-06-24 Computação em arquitetura de acelerador de aprendizado de máquina baseado em memória BR112023026172A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/359,297 US20220414443A1 (en) 2021-06-25 2021-06-25 Compute in memory-based machine learning accelerator architecture
PCT/US2022/073154 WO2022272303A1 (en) 2021-06-25 2022-06-24 Compute in memory-based machine learning accelerator architecture

Publications (1)

Publication Number Publication Date
BR112023026172A2 true BR112023026172A2 (pt) 2024-03-05

Family

ID=82656589

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023026172A BR112023026172A2 (pt) 2021-06-25 2022-06-24 Computação em arquitetura de acelerador de aprendizado de máquina baseado em memória

Country Status (7)

Country Link
US (1) US20220414443A1 (pt)
EP (1) EP4360002A1 (pt)
KR (1) KR20240026450A (pt)
CN (1) CN117651952A (pt)
BR (1) BR112023026172A2 (pt)
TW (1) TW202307739A (pt)
WO (1) WO2022272303A1 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114298297A (zh) * 2021-11-04 2022-04-08 清华大学 存内计算装置、芯片及电子设备
US11935586B2 (en) * 2022-02-11 2024-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method for computing-in-memory (CIM)
CN117616419A (zh) * 2022-04-29 2024-02-27 微软技术许可有限责任公司 语音识别中的定制显示后处理

Also Published As

Publication number Publication date
WO2022272303A1 (en) 2022-12-29
KR20240026450A (ko) 2024-02-28
CN117651952A (zh) 2024-03-05
US20220414443A1 (en) 2022-12-29
TW202307739A (zh) 2023-02-16
EP4360002A1 (en) 2024-05-01

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