BR112023017122A2 - Textura em looping intraonda - Google Patents

Textura em looping intraonda

Info

Publication number
BR112023017122A2
BR112023017122A2 BR112023017122A BR112023017122A BR112023017122A2 BR 112023017122 A2 BR112023017122 A2 BR 112023017122A2 BR 112023017122 A BR112023017122 A BR 112023017122A BR 112023017122 A BR112023017122 A BR 112023017122A BR 112023017122 A2 BR112023017122 A2 BR 112023017122A2
Authority
BR
Brazil
Prior art keywords
thread
subgroups
group
intrawave
looping
Prior art date
Application number
BR112023017122A
Other languages
English (en)
Inventor
evan gruber Andrew
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023017122A2 publication Critical patent/BR112023017122A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)

Abstract

textura em looping intraonda. a presente revelação refere-se aos métodos e dispositivos para processamento gráfico incluindo um aparelho, por exemplo, uma gpu. o aparelho pode determinar se deve dividir um grupo de threads em uma pluralidade de subgrupos de threads, cada thread do grupo de threads sendo associado a um programa shader. o aparelho também pode dividir, ao determinar a divisão do grupo de threads na pluralidade de subgrupos de threads, o grupo de threads na pluralidade de subgrupos de threads. além disso, o aparelho pode executar, ao dividir o grupo de threads na pluralidade de subgrupos de threads, uma subseção do programa shader para cada subgrupo de threads da pluralidade de subgrupos de threads.
BR112023017122A 2021-03-03 2022-02-04 Textura em looping intraonda BR112023017122A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/191,439 US11640647B2 (en) 2021-03-03 2021-03-03 Methods and apparatus for intra-wave texture looping
PCT/US2022/015336 WO2022186948A1 (en) 2021-03-03 2022-02-04 Intra-wave texture looping

Publications (1)

Publication Number Publication Date
BR112023017122A2 true BR112023017122A2 (pt) 2023-09-26

Family

ID=80446190

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023017122A BR112023017122A2 (pt) 2021-03-03 2022-02-04 Textura em looping intraonda

Country Status (7)

Country Link
US (1) US11640647B2 (pt)
EP (1) EP4302181A1 (pt)
KR (1) KR20230130157A (pt)
CN (1) CN116940922A (pt)
BR (1) BR112023017122A2 (pt)
TW (1) TW202301116A (pt)
WO (1) WO2022186948A1 (pt)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7542043B1 (en) 2005-05-23 2009-06-02 Nvidia Corporation Subdividing a shader program
US9648325B2 (en) * 2007-06-30 2017-05-09 Microsoft Technology Licensing, Llc Video decoding implementations for a graphics processing unit
US9648299B2 (en) * 2013-01-04 2017-05-09 Qualcomm Incorporated Indication of presence of texture and depth views in tracks for multiview coding plus depth
US9652284B2 (en) * 2013-10-01 2017-05-16 Qualcomm Incorporated GPU divergence barrier
US9799094B1 (en) * 2016-05-23 2017-10-24 Qualcomm Incorporated Per-instance preamble for graphics processing
US10558460B2 (en) 2016-12-14 2020-02-11 Qualcomm Incorporated General purpose register allocation in streaming processor
US10325341B2 (en) * 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
US11442795B2 (en) * 2018-09-11 2022-09-13 Nvidia Corp. Convergence among concurrently executing threads
US11816500B2 (en) * 2019-03-15 2023-11-14 Intel Corporation Systems and methods for synchronization of multi-thread lanes
US11016774B1 (en) * 2019-11-26 2021-05-25 Arm Limited Issuing execution threads in a data processor

Also Published As

Publication number Publication date
WO2022186948A1 (en) 2022-09-09
US11640647B2 (en) 2023-05-02
TW202301116A (zh) 2023-01-01
CN116940922A (zh) 2023-10-24
US20220284537A1 (en) 2022-09-08
KR20230130157A (ko) 2023-09-11
EP4302181A1 (en) 2024-01-10

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