BR112023003044A2 - Agendamento vinculado à memória - Google Patents
Agendamento vinculado à memóriaInfo
- Publication number
- BR112023003044A2 BR112023003044A2 BR112023003044A BR112023003044A BR112023003044A2 BR 112023003044 A2 BR112023003044 A2 BR 112023003044A2 BR 112023003044 A BR112023003044 A BR 112023003044A BR 112023003044 A BR112023003044 A BR 112023003044A BR 112023003044 A2 BR112023003044 A2 BR 112023003044A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- modified
- topological
- generating
- nodes
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/43—Checking; Contextual analysis
- G06F8/433—Dependency analysis; Data or control flow analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
AGENDAMENTO VINCULADO À MEMÓRIA. Em determinados aspectos, a presente invenção refere-se a técnicas para a geração de cronogramas de execução, compreendendo receber um gráfico de fluxo de dados para um processo, em que o gráfico de fluxo de dados compreende uma pluralidade de nós e uma pluralidade de arestas; gerar uma ordenação topológica para o gráfico de fluxo de dados com base, pelo menos em parte, no uso da memória do processo; gerar uma primeira ordenação topológica modificada inserindo, à ordenação topológica, um ou mais novos nós correspondentes ao acesso à memória com base em uma capacidade de memória predefinida; alocar unidades de memória na memória com base na primeira ordenação topológica modificada; e gerar uma segunda ordenação topológica modificada reorganizando um ou mais nós na primeira ordenação topológica modificada, em que a segunda ordenação topológica modificada permite maior uso paralelo de uma pluralidade de componentes de hardware.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202063073269P | 2020-09-01 | 2020-09-01 | |
US17/463,393 US20220066834A1 (en) | 2020-09-01 | 2021-08-31 | Memory-bound scheduling |
PCT/US2021/048745 WO2022051422A1 (en) | 2020-09-01 | 2021-09-01 | Memory-bound scheduling |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112023003044A2 true BR112023003044A2 (pt) | 2023-03-21 |
Family
ID=80357696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112023003044A BR112023003044A2 (pt) | 2020-09-01 | 2021-09-01 | Agendamento vinculado à memória |
Country Status (6)
Country | Link |
---|---|
US (1) | US20220066834A1 (pt) |
EP (1) | EP4208786A1 (pt) |
KR (1) | KR20230058621A (pt) |
CN (1) | CN115968467A (pt) |
BR (1) | BR112023003044A2 (pt) |
WO (1) | WO2022051422A1 (pt) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116957170B (zh) * | 2023-09-20 | 2023-12-22 | 中国南方电网有限责任公司 | 一种电力系统优化问题的约束集约减方法及系统 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010044850A1 (en) * | 1998-07-22 | 2001-11-22 | Uri Raz | Method and apparatus for determining the order of streaming modules |
US7844959B2 (en) * | 2006-09-29 | 2010-11-30 | Microsoft Corporation | Runtime optimization of distributed execution graph |
US20090327195A1 (en) * | 2008-06-27 | 2009-12-31 | Microsoft Corporation | Root cause analysis optimization |
KR20120134549A (ko) * | 2011-06-02 | 2012-12-12 | 삼성전자주식회사 | Simd 프로세서를 이용한 병렬 연산 처리 장치 및 방법 |
US20130055091A1 (en) * | 2011-08-23 | 2013-02-28 | Cisco Technology, Inc. | Graph-Based Virtual Data Center Requests |
US8938599B2 (en) * | 2012-03-15 | 2015-01-20 | Hewlett-Packard Development Company, L. P. | Distributed graph storage system |
US9411558B2 (en) * | 2012-10-20 | 2016-08-09 | Luke Hutchison | Systems and methods for parallelization of program code, interactive data visualization, and graphically-augmented code editing |
US20150254130A1 (en) * | 2013-12-03 | 2015-09-10 | Kabushiki Kaisha Toshiba | Error correction decoder |
US10956050B2 (en) * | 2014-03-31 | 2021-03-23 | Sandisk Enterprise Ip Llc | Methods and systems for efficient non-isolated transactions |
US10089056B2 (en) * | 2015-06-07 | 2018-10-02 | Apple Inc. | Device, method, and graphical user interface for collaborative editing in documents |
US10664757B2 (en) * | 2015-09-16 | 2020-05-26 | International Business Machines Corporation | Cognitive operations based on empirically constructed knowledge graphs |
CN111247513B (zh) * | 2017-04-17 | 2021-10-08 | 迪普西格有限公司 | 无线电信号处理数据流操作的放置与调度 |
US10515431B2 (en) * | 2017-12-12 | 2019-12-24 | Intel Corporation | Global optimal path determination utilizing parallel processing |
US20190286973A1 (en) * | 2018-03-14 | 2019-09-19 | Microsoft Technology Licensing, Llc | Hardware accelerated neural network subgraphs |
US10868728B2 (en) * | 2018-08-22 | 2020-12-15 | Hewlett Packard Enterprise Development Lp | Graph-based network management |
US11861464B2 (en) * | 2019-10-31 | 2024-01-02 | Adobe Inc. | Graph data structure for using inter-feature dependencies in machine-learning |
-
2021
- 2021-08-31 US US17/463,393 patent/US20220066834A1/en active Pending
- 2021-09-01 WO PCT/US2021/048745 patent/WO2022051422A1/en unknown
- 2021-09-01 EP EP21786300.0A patent/EP4208786A1/en active Pending
- 2021-09-01 BR BR112023003044A patent/BR112023003044A2/pt unknown
- 2021-09-01 CN CN202180051645.6A patent/CN115968467A/zh active Pending
- 2021-09-01 KR KR1020237006310A patent/KR20230058621A/ko unknown
Also Published As
Publication number | Publication date |
---|---|
KR20230058621A (ko) | 2023-05-03 |
US20220066834A1 (en) | 2022-03-03 |
CN115968467A (zh) | 2023-04-14 |
EP4208786A1 (en) | 2023-07-12 |
WO2022051422A1 (en) | 2022-03-10 |
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