BR112022015064A2 - MULTIPLE CHIPS HEAT DISSIPATION PACKAGING STRUCTURE AND PACKAGING METHOD. - Google Patents

MULTIPLE CHIPS HEAT DISSIPATION PACKAGING STRUCTURE AND PACKAGING METHOD.

Info

Publication number
BR112022015064A2
BR112022015064A2 BR112022015064A BR112022015064A BR112022015064A2 BR 112022015064 A2 BR112022015064 A2 BR 112022015064A2 BR 112022015064 A BR112022015064 A BR 112022015064A BR 112022015064 A BR112022015064 A BR 112022015064A BR 112022015064 A2 BR112022015064 A2 BR 112022015064A2
Authority
BR
Brazil
Prior art keywords
concave
heat dissipation
substrate
chip
packaging
Prior art date
Application number
BR112022015064A
Other languages
Portuguese (pt)
Inventor
Dong Wang
Qi Zheng
Quan Cao
Rongyao Tang
Original Assignee
Fiberhome Telecommunication Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fiberhome Telecommunication Tech Co Ltd filed Critical Fiberhome Telecommunication Tech Co Ltd
Publication of BR112022015064A2 publication Critical patent/BR112022015064A2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

ESTRUTURA DE EMBALAGEM DE DISSIPAÇÃO DE CALOR DE MÚLTIPLOS CHIPS E MÉTODO DE EMBALAGEM. A presente invenção se refere ao campo técnico de embalagem de semicondutor e fornece uma estrutura de embalagem de dissipação de calor de múltiplos chips e um método de embalagem. Na estrutura, um chip invertido é disposto em uma parte de fundo côncava de um substrato de pré-embalagem côncavo, em que a parte de fundo côncava do substrato de pré-embalagem côncavo é dotada de um primeiro conjunto de blocos, e o primeiro conjunto de blocos é usado para se conectar eletricamente aos pinos de um chip formal invertido; o primeiro conjunto de blocos transfere, por meio de uma parede lateral côncava do substrato de pré-embalagem côncavo, características elétricas para uma região de parte de extremidade da parede lateral côncava com a finalidade de facilitar a conexão elétrica entre o chip invertido e o substrato quando o substrato de pré-embalagem côncavo é colocado de cabeça para baixo em uma placa base; uma montagem de dissipação de calor é adicionalmente fornecida na superfície externa da parte de fundo côncava do substrato de pré-embalagem côncavo, e a montagem de dissipação de calor é acoplada à parte de fundo do chip invertido e é usada para dissipar calor produzido quando o chip invertido está em operação; um chip formal normal é disposto na placa base, e a dissipação de calor é executada por meio da placa base e uma cavidade de embalagem. A presente invenção alcança a dissipação de calor eficiente de chips e assegura a operação normal dos chips.MULTIPLE CHIPS HEAT DISSIPATION PACKAGING STRUCTURE AND PACKAGING METHOD. The present invention relates to the technical field of semiconductor packaging and provides a multi-chip heat dissipation packaging structure and packaging method. In the structure, an inverted chip is disposed in a concave bottom portion of a concave prepackaging substrate, wherein the concave bottom portion of the concave prepackaging substrate is provided with a first set of blocks, and the first set of blocks is used to electrically connect to the pins of an inverted formal chip; the first set of blocks transfers, via a concave sidewall of the concave prepackaging substrate, electrical characteristics to an end portion region of the concave sidewall for the purpose of facilitating the electrical connection between the inverted chip and the substrate when the concave prepackaging substrate is placed upside down on a base plate; a heat dissipation assembly is additionally provided on the outer surface of the concave bottom part of the concave prepackaging substrate, and the heat dissipation assembly is attached to the bottom part of the inverted chip and is used to dissipate heat produced when the inverted chip is in operation; a normal formal chip is arranged on the baseboard, and heat dissipation is performed through the baseplate and a packaging cavity. The present invention achieves efficient heat dissipation of chips and ensures normal operation of chips.

BR112022015064A 2020-04-13 2020-08-28 MULTIPLE CHIPS HEAT DISSIPATION PACKAGING STRUCTURE AND PACKAGING METHOD. BR112022015064A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010283622.5A CN113539989B (en) 2020-04-13 2020-04-13 Multi-chip heat dissipation packaging structure and packaging method
PCT/CN2020/111972 WO2021208322A1 (en) 2020-04-13 2020-08-28 Multi-chip heat-dissipating packaging structure and packaging method

Publications (1)

Publication Number Publication Date
BR112022015064A2 true BR112022015064A2 (en) 2022-12-06

Family

ID=78083705

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022015064A BR112022015064A2 (en) 2020-04-13 2020-08-28 MULTIPLE CHIPS HEAT DISSIPATION PACKAGING STRUCTURE AND PACKAGING METHOD.

Country Status (3)

Country Link
CN (1) CN113539989B (en)
BR (1) BR112022015064A2 (en)
WO (1) WO2021208322A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115662965A (en) * 2022-12-15 2023-01-31 成都华兴大地科技有限公司 Novel high-power-consumption chip packaging structure and packaging method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650593A (en) * 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
JPH0982826A (en) * 1995-09-18 1997-03-28 Nippon Telegr & Teleph Corp <Ntt> Semiconductor element sealing package and package structure of circuit device using the same
KR100266637B1 (en) * 1997-11-15 2000-09-15 김영환 Stackable ball grid array semiconductor package and a method thereof
KR20020039010A (en) * 2000-11-20 2002-05-25 윤종용 Double die package having heat spreaders
CN1187805C (en) * 2001-11-02 2005-02-02 全懋精密科技股份有限公司 Application of heat radiator with support effect for circuit board with chip
JP5197961B2 (en) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド Multi-chip package module and manufacturing method thereof
JP5023604B2 (en) * 2006-08-09 2012-09-12 富士電機株式会社 Semiconductor device
JP6366627B2 (en) * 2016-03-25 2018-08-01 デクセリアルズ株式会社 Electromagnetic wave absorbing heat conducting sheet, method for producing electromagnetic wave absorbing heat conducting sheet, and semiconductor device
CN105789154A (en) * 2016-04-20 2016-07-20 广东工业大学 Inverted chip module group
US11088047B2 (en) * 2018-08-03 2021-08-10 Texas Instruments Incorporated Ceramic package opening, heat sink, vias coupled to conductive pad
CN109346442B (en) * 2018-10-10 2020-05-15 常熟市华通电子有限公司 Chip packaging structure easy to dissipate heat and packaging method thereof

Also Published As

Publication number Publication date
WO2021208322A1 (en) 2021-10-21
CN113539989B (en) 2023-07-21
CN113539989A (en) 2021-10-22

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