BR112019005235A2 - gerenciamento flexível de sistemas de memória heterogêneos usando marcação de qualidade de serviço (qos) espacial nos sistemas com base em processador - Google Patents
gerenciamento flexível de sistemas de memória heterogêneos usando marcação de qualidade de serviço (qos) espacial nos sistemas com base em processadorInfo
- Publication number
- BR112019005235A2 BR112019005235A2 BR112019005235A BR112019005235A BR112019005235A2 BR 112019005235 A2 BR112019005235 A2 BR 112019005235A2 BR 112019005235 A BR112019005235 A BR 112019005235A BR 112019005235 A BR112019005235 A BR 112019005235A BR 112019005235 A2 BR112019005235 A2 BR 112019005235A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- qos
- processor
- qosid
- heterogeneous
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
Abstract
o documento revela o gerenciamento flexível de sistemas de memória heterogêneos usando marcação de qualidade de serviço - quality of service (qos) espacial em sistemas com base em processador. em um aspecto, um sistema de memória heterogêneo de um sistema com base em processador inclui uma primeira memória e uma segunda memória. o sistema de memória heterogêneo é dividido em uma pluralidade de regiões de memória, cada uma associada a um identificador de qos (qosid), que pode ser definido e atualizado por software. um controlador de memória do sistema de memória heterogêneo fornece uma tabela de políticas de qos, que opera para associar cada qosid a um estado de política de qos e que também pode ser configurável por software. ao receber uma solicitação de acesso à memória incluindo um endereço de memória de uma região de memória, o controlador de memória identifica um qosid configurável por software associado ao endereço de memória e associa o qosid a um estado de política de qos usando a tabela de políticas de qos. em seguida, o controlador de memória aplica o estado da política de qos para realização da operação de acesso à memória.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/272,951 US10055158B2 (en) | 2016-09-22 | 2016-09-22 | Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems |
PCT/US2017/048561 WO2018057231A1 (en) | 2016-09-22 | 2017-08-25 | Providing flexible management of heterogeneous memory systems using spatial quality of service (qos) tagging in processor-based systems |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112019005235A2 true BR112019005235A2 (pt) | 2019-06-04 |
Family
ID=59762104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112019005235A BR112019005235A2 (pt) | 2016-09-22 | 2017-08-25 | gerenciamento flexível de sistemas de memória heterogêneos usando marcação de qualidade de serviço (qos) espacial nos sistemas com base em processador |
Country Status (9)
Country | Link |
---|---|
US (1) | US10055158B2 (pt) |
EP (1) | EP3516523B1 (pt) |
JP (1) | JP7116047B2 (pt) |
KR (1) | KR102545726B1 (pt) |
CN (1) | CN109690500B (pt) |
BR (1) | BR112019005235A2 (pt) |
CA (1) | CA3034273A1 (pt) |
TW (1) | TWI655545B (pt) |
WO (1) | WO2018057231A1 (pt) |
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US11314753B2 (en) | 2016-09-26 | 2022-04-26 | Splunk Inc. | Execution of a query received from a data intake and query system |
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US11593377B2 (en) | 2016-09-26 | 2023-02-28 | Splunk Inc. | Assigning processing tasks in a data intake and query system |
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-
2016
- 2016-09-22 US US15/272,951 patent/US10055158B2/en active Active
-
2017
- 2017-08-17 TW TW106127867A patent/TWI655545B/zh not_active IP Right Cessation
- 2017-08-25 BR BR112019005235A patent/BR112019005235A2/pt unknown
- 2017-08-25 CA CA3034273A patent/CA3034273A1/en active Pending
- 2017-08-25 JP JP2019514121A patent/JP7116047B2/ja active Active
- 2017-08-25 EP EP17761422.9A patent/EP3516523B1/en active Active
- 2017-08-25 WO PCT/US2017/048561 patent/WO2018057231A1/en unknown
- 2017-08-25 KR KR1020197007982A patent/KR102545726B1/ko active IP Right Grant
- 2017-08-25 CN CN201780054540.XA patent/CN109690500B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CA3034273A1 (en) | 2018-03-29 |
US10055158B2 (en) | 2018-08-21 |
CN109690500A (zh) | 2019-04-26 |
US20180081579A1 (en) | 2018-03-22 |
KR102545726B1 (ko) | 2023-06-19 |
TWI655545B (zh) | 2019-04-01 |
CN109690500B (zh) | 2023-06-20 |
JP7116047B2 (ja) | 2022-08-09 |
TW201814539A (zh) | 2018-04-16 |
JP2019532412A (ja) | 2019-11-07 |
EP3516523B1 (en) | 2021-09-15 |
WO2018057231A1 (en) | 2018-03-29 |
EP3516523A1 (en) | 2019-07-31 |
KR20190049742A (ko) | 2019-05-09 |
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