BR112014015051A2 - sistema e método para a liberação inteligente de dados de um processador para um subsistema de memória - Google Patents
sistema e método para a liberação inteligente de dados de um processador para um subsistema de memóriaInfo
- Publication number
- BR112014015051A2 BR112014015051A2 BR112014015051A BR112014015051A BR112014015051A2 BR 112014015051 A2 BR112014015051 A2 BR 112014015051A2 BR 112014015051 A BR112014015051 A BR 112014015051A BR 112014015051 A BR112014015051 A BR 112014015051A BR 112014015051 A2 BR112014015051 A2 BR 112014015051A2
- Authority
- BR
- Brazil
- Prior art keywords
- processor
- data
- memory
- address range
- pcm
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
Abstract
resumo "sistema e método para a liberação inteligente de dados de um processador para um subsistema de memória". são descritos um sistema e um método para a liberação inteligente de dados de um cache de processador. por exemplo, um sistema de acordo com uma modalidade da invenção, compreende: um processador que tem um cache a partir do qual os dados são descarregados, os dados associados com determinado intervalo de endereços de sistema; e um controlador de memória pcm para gerenciar o acesso aos dados armazenados em um dispositivo de memória pcm correspondente a determinado intervalo de endereços de sistema; o processador determinando se as dicas de liberação de memória estão habilitadas para o intervalo de endereços de sistema especificado, em que se as dicas de liberação de memória estão habilitadas para o intervalo de endereços de sistema especificado então o processador envia uma dica de liberação de memória para um controlador de memória pcm do dispositivo de memória pcm, e em que o controlador de memória pcm utiliza a dica de liberação de memória para determinar se os dados descarregados devem ser salvos no dispositivo de memória pcm.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2011/066492 WO2013095437A1 (en) | 2011-12-21 | 2011-12-21 | System and method for intelligently flushing data from a processor into a memory subsystem |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112014015051A2 true BR112014015051A2 (pt) | 2017-06-13 |
BR112014015051B1 BR112014015051B1 (pt) | 2021-05-25 |
Family
ID=48669089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112014015051-6A BR112014015051B1 (pt) | 2011-12-21 | 2011-12-21 | método e sistema para utilizar dicas de liberação de memória dentro de um sistema de computador |
Country Status (7)
Country | Link |
---|---|
US (1) | US9269438B2 (pt) |
KR (1) | KR101636634B1 (pt) |
CN (1) | CN104115129B (pt) |
BR (1) | BR112014015051B1 (pt) |
DE (1) | DE112011106013T5 (pt) |
GB (1) | GB2514023B (pt) |
WO (1) | WO2013095437A1 (pt) |
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2011
- 2011-12-21 KR KR1020147017885A patent/KR101636634B1/ko active IP Right Grant
- 2011-12-21 WO PCT/US2011/066492 patent/WO2013095437A1/en active Application Filing
- 2011-12-21 DE DE112011106013.0T patent/DE112011106013T5/de active Pending
- 2011-12-21 CN CN201180076401.XA patent/CN104115129B/zh active Active
- 2011-12-21 BR BR112014015051-6A patent/BR112014015051B1/pt active IP Right Grant
- 2011-12-21 GB GB1411389.8A patent/GB2514023B/en active Active
- 2011-12-21 US US13/994,723 patent/US9269438B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
GB2514023A (en) | 2014-11-12 |
GB2514023B (en) | 2019-07-03 |
WO2013095437A1 (en) | 2013-06-27 |
BR112014015051B1 (pt) | 2021-05-25 |
US9269438B2 (en) | 2016-02-23 |
GB201411389D0 (en) | 2014-08-13 |
CN104115129A (zh) | 2014-10-22 |
US20140297919A1 (en) | 2014-10-02 |
KR20140098220A (ko) | 2014-08-07 |
CN104115129B (zh) | 2017-09-08 |
DE112011106013T5 (de) | 2014-10-02 |
KR101636634B1 (ko) | 2016-07-05 |
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Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 21/12/2011, OBSERVADAS AS CONDICOES LEGAIS. |