BR102012010971A2 - Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral - Google Patents

Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral Download PDF

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Publication number
BR102012010971A2
BR102012010971A2 BRBR102012010971-9A BR102012010971A BR102012010971A2 BR 102012010971 A2 BR102012010971 A2 BR 102012010971A2 BR 102012010971 A BR102012010971 A BR 102012010971A BR 102012010971 A2 BR102012010971 A2 BR 102012010971A2
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BR
Brazil
Prior art keywords
module
modular
mod
result
operands
Prior art date
Application number
BRBR102012010971-9A
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English (en)
Portuguese (pt)
Inventor
Marc Joye
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Thomson Licensing
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Publication of BR102012010971A2 publication Critical patent/BR102012010971A2/pt

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7261—Uniform execution, e.g. avoiding jumps, or using formulae with the same power profile

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Storage Device Security (AREA)
  • Error Detection And Correction (AREA)
BRBR102012010971-9A 2011-05-11 2012-05-09 Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral BR102012010971A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP11305568 2011-05-11
EP11176404A EP2523096A1 (en) 2011-05-11 2011-08-03 Modular exponentiation and device resistant against side-channel attacks

Publications (1)

Publication Number Publication Date
BR102012010971A2 true BR102012010971A2 (pt) 2013-11-12

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ID=44546155

Family Applications (1)

Application Number Title Priority Date Filing Date
BRBR102012010971-9A BR102012010971A2 (pt) 2011-05-11 2012-05-09 Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral

Country Status (7)

Country Link
US (1) US8984040B2 (cg-RX-API-DMAC10.html)
EP (2) EP2523096A1 (cg-RX-API-DMAC10.html)
JP (1) JP5977996B2 (cg-RX-API-DMAC10.html)
CN (1) CN102779022B (cg-RX-API-DMAC10.html)
BR (1) BR102012010971A2 (cg-RX-API-DMAC10.html)
CA (1) CA2775325A1 (cg-RX-API-DMAC10.html)
MX (1) MX2012005408A (cg-RX-API-DMAC10.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9645794B2 (en) * 2014-09-23 2017-05-09 Texas Instruments Incorporated Homogeneous atomic pattern for double, add, and subtract operations for digital authentication using elliptic curve cryptography
CN104811297B (zh) * 2015-04-23 2018-06-12 成都信息工程学院 针对RSA之M-ary实现模乘余数输入侧信道攻击
CN106571916B (zh) * 2015-10-12 2020-06-30 瑞昱半导体股份有限公司 解密装置、方法及电路
EP3559811B1 (en) 2016-12-21 2024-04-24 Cryptography Research, Inc. Protecting parallel multiplication operations from external monitoring attacks
EP3447509B1 (en) * 2017-08-21 2021-05-26 Eshard Method of testing the resistance of a circuit to a side channel analysis
US11895230B2 (en) * 2019-01-24 2024-02-06 Nec Corporation Information processing apparatus, secure computation method, and program
CN112260818B (zh) * 2020-10-19 2022-09-20 中国人民解放军战略支援部队信息工程大学 侧信道曲线的增强方法、侧信道攻击方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175850B1 (en) * 1997-02-03 2001-01-16 Nippon Telegraph And Telephone Corporation Scheme for carrying out modular calculations based on redundant binary calculation
EP1994465A1 (fr) * 2006-03-16 2008-11-26 Gemplus Procede de securisation d'un calcul d'une exponentiation ou d'une multiplication par un scalaire dans un dispositif electronique
EP1840732A1 (en) * 2006-03-31 2007-10-03 Axalto SA Protection against side channel attacks
FR2949925A1 (fr) * 2009-09-09 2011-03-11 Proton World Int Nv Protection d'une generation de nombres premiers contre des attaques par canaux caches

Also Published As

Publication number Publication date
EP2523096A1 (en) 2012-11-14
CN102779022B (zh) 2017-03-01
US8984040B2 (en) 2015-03-17
CN102779022A (zh) 2012-11-14
EP2523097A1 (en) 2012-11-14
EP2523097B1 (en) 2016-01-20
JP2012239171A (ja) 2012-12-06
US20120290634A1 (en) 2012-11-15
CA2775325A1 (en) 2012-11-11
MX2012005408A (es) 2012-11-21
JP5977996B2 (ja) 2016-08-24
HK1176423A1 (en) 2013-07-26

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B03A Publication of an application: publication of a patent application or of a certificate of addition of invention
B08F Application fees: dismissal - article 86 of industrial property law
B08K Lapse as no evidence of payment of the annual fee has been furnished to inpi (acc. art. 87)