BR0317846A - Método e aparelho para corrigir codigos e dados residentes em uma memória - Google Patents

Método e aparelho para corrigir codigos e dados residentes em uma memória

Info

Publication number
BR0317846A
BR0317846A BR0317846-3A BR0317846A BR0317846A BR 0317846 A BR0317846 A BR 0317846A BR 0317846 A BR0317846 A BR 0317846A BR 0317846 A BR0317846 A BR 0317846A
Authority
BR
Brazil
Prior art keywords
code
address
memory
resident
codes
Prior art date
Application number
BR0317846-3A
Other languages
English (en)
Inventor
John Oakley
Kevin Traylor
Glen Zoerner
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BR0317846A publication Critical patent/BR0317846A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/26Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262Arrangements for next microinstruction selection
    • G06F9/268Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

"MéTODO E APARELHO PARA CORRIGIR CODIGOS E DADOS RESIDENTES EM UMA MEMóRIA". Um método e um aparelho para aplicar correções a um código ou dado residente em um dispositivo de memória não-volátil são ilustrados. Um código residente em uma primeira localização na memória não-volátil pode ser substituído por códigos residentes em uma segunda localização no mapa de memória. O dispositivo de correção compara um primeiro endereço de um primeiro código com um endereço identificado por uma instrução de pré-aquisição. Se o primeiro endereço combinar com o endereço identificado pela instrução de pré-aquisição, o cancelamento da pré-aquisição é emitido para facilitar a substituição do código ruim residente no primeiro endereço por um código bom. O código bom pode ser apontado por um vetor na tabela de vetores onde o endereço dos vetores é dinamicamente carregado dentro de um contador de programa.
BR0317846-3A 2002-12-31 2003-12-09 Método e aparelho para corrigir codigos e dados residentes em uma memória BR0317846A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/334,260 US6931477B2 (en) 2002-12-31 2002-12-31 Method and apparatus for patching code and data residing on a memory
PCT/US2003/039383 WO2004061585A2 (en) 2002-12-31 2003-12-09 Method and apparatus for patching code and data residing on a memory

Publications (1)

Publication Number Publication Date
BR0317846A true BR0317846A (pt) 2005-12-06

Family

ID=32654995

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0317846-3A BR0317846A (pt) 2002-12-31 2003-12-09 Método e aparelho para corrigir codigos e dados residentes em uma memória

Country Status (5)

Country Link
US (1) US6931477B2 (pt)
CN (1) CN1732443B (pt)
AU (1) AU2003297866A1 (pt)
BR (1) BR0317846A (pt)
WO (1) WO2004061585A2 (pt)

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US7062598B1 (en) * 2003-04-29 2006-06-13 Advanced Micro Devices, Inc. Bypass custom array and related method for implementing ROM fixes in a data processor
TW200513850A (en) * 2003-10-13 2005-04-16 Design Technology Inc G Patch and expansion method of memory program for digital signal processor
US7596721B1 (en) * 2004-01-09 2009-09-29 Maxtor Corporation Methods and structure for patching embedded firmware
US7424570B2 (en) * 2004-04-08 2008-09-09 Incard Sa Method for patching ROM instructions in an electronic embedded system including at least a further memory portion
EP1686467B1 (en) * 2005-01-31 2008-03-12 STMicroelectronics S.r.l. Method and system for correcting errors in read-only memory devices, and computer program product therefor
US7464248B2 (en) * 2005-04-25 2008-12-09 Mediatek Incorporation Microprocessor systems and bus address translation methods
TW200719142A (en) * 2005-11-08 2007-05-16 Mstar Semiconductor Inc Content correction method of an ROM build-in program code
US7739469B2 (en) * 2005-11-08 2010-06-15 Freescale Semiconductor, Inc. Patching ROM code
US7984432B2 (en) * 2006-05-30 2011-07-19 Infineon Technologies Ag Method for patching a read-only memory and a data processing system comprising a means of patching the read-only memory based on patch contexts
JP2008198060A (ja) * 2007-02-15 2008-08-28 Seiko Epson Corp 情報処理装置、パッチコード実装システム、電子機器及びパッチコードの実装方法
US8266597B2 (en) * 2008-06-16 2012-09-11 International Business Machines Corporation Dynamically patching computer code using breakpoints
JP2010140167A (ja) * 2008-12-10 2010-06-24 Toshiba Corp 半導体集積回路
EP2224334A1 (en) * 2009-02-28 2010-09-01 Research In Motion Limited Methods and tools for creation of read-only-memory software binary images and corresponding software patches
US9536090B2 (en) * 2013-05-26 2017-01-03 Check Point Software Technologies Ltd. Method of defending a computer from malware
US10496410B2 (en) * 2014-12-23 2019-12-03 Intel Corporation Instruction and logic for suppression of hardware prefetchers
CN106354524B (zh) 2015-07-17 2021-01-01 恩智浦美国有限公司 实时更新固件的系统和方法
GB2551523B (en) 2016-06-20 2019-07-03 Imagination Tech Ltd Livelock recovery circuit
US10831393B2 (en) 2018-02-08 2020-11-10 Micron Technology, Inc. Partial save of memory
CN112231136A (zh) * 2020-11-04 2021-01-15 炬芯科技股份有限公司 SoC芯片、获取修复信息的方法、存储介质及电子设备
CN113485948B (zh) * 2021-06-29 2023-11-14 成都忆芯科技有限公司 Nvm坏块管理方法与控制部件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5551033A (en) * 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US6463549B1 (en) * 2000-09-28 2002-10-08 Motorola, Inc. Device and method for patching code residing on a read only memory module utilizing a random access memory for storing a set of fields, each field indicating validity of content of a group, and for receiving an address of a memory portion of the read only memory
US6865667B2 (en) * 2001-03-05 2005-03-08 Freescale Semiconductors, Inc. Data processing system having redirecting circuitry and method therefor

Also Published As

Publication number Publication date
CN1732443B (zh) 2010-04-28
AU2003297866A1 (en) 2004-07-29
WO2004061585A3 (en) 2005-05-19
AU2003297866A8 (en) 2004-07-29
US6931477B2 (en) 2005-08-16
US20040128471A1 (en) 2004-07-01
WO2004061585A2 (en) 2004-07-22
CN1732443A (zh) 2006-02-08

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Legal Events

Date Code Title Description
B25D Requested change of name of applicant approved

Owner name: MOTOROLA SOLUTIONS, INC. (US)

B25A Requested transfer of rights approved

Owner name: MOTOROLA MOBILITY, INC. (US)

B25E Requested change of name of applicant rejected

Owner name: MOTOROLA MOBILITY, INC. (US)

Free format text: INDEFERIDO O PEDIDO DE ALTERACAO DE NOME CONTIDO NA PETICAO 20130041091 DE 15/05/2013, DEVIDO A AUSENCIA DE GUIA DE RECOLHIMENTO RELATIVA AO SERVICO.

B25G Requested change of headquarter approved

Owner name: MOTOROLA MOBILITY, INC. (US)

B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B25D Requested change of name of applicant approved

Owner name: MOTOROLA MOBILITY LLC (US)

B25A Requested transfer of rights approved

Owner name: GOOGLE TECHNOLOGY HOLDINGS LLC (US)

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ART .8O COMBINADO COM ART. 13 DA LPI

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.