BE827243A - Retardement de lecture de la memoire dans les ordinateurs - Google Patents

Retardement de lecture de la memoire dans les ordinateurs

Info

Publication number
BE827243A
BE827243A BE154817A BE154817A BE827243A BE 827243 A BE827243 A BE 827243A BE 154817 A BE154817 A BE 154817A BE 154817 A BE154817 A BE 154817A BE 827243 A BE827243 A BE 827243A
Authority
BE
Belgium
Prior art keywords
computers
memory reading
reading delay
delay
memory
Prior art date
Application number
BE154817A
Other languages
English (en)
Inventor
C P Dahlberg
D A Peterson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE827243A publication Critical patent/BE827243A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Pulse Circuits (AREA)
BE154817A 1974-04-15 1975-03-27 Retardement de lecture de la memoire dans les ordinateurs BE827243A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/460,823 US3984812A (en) 1974-04-15 1974-04-15 Computer memory read delay

Publications (1)

Publication Number Publication Date
BE827243A true BE827243A (fr) 1975-07-16

Family

ID=23830204

Family Applications (1)

Application Number Title Priority Date Filing Date
BE154817A BE827243A (fr) 1974-04-15 1975-03-27 Retardement de lecture de la memoire dans les ordinateurs

Country Status (3)

Country Link
US (1) US3984812A (fr)
BE (1) BE827243A (fr)
GB (1) GB1477236A (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153941A (en) * 1976-11-11 1979-05-08 Kearney & Trecker Corporation Timing circuit and method for controlling the operation of cyclical devices
GB1561961A (en) * 1977-04-20 1980-03-05 Int Computers Ltd Data processing units
EP0082903B1 (fr) * 1981-12-29 1987-05-13 International Business Machines Corporation Unité de commande pouvant être connectée à deux mémoires de vitesses différentes
US4727491A (en) * 1984-06-27 1988-02-23 Compaq Computer Corporation Personal computer having normal and high speed execution modes
US4835681A (en) * 1984-06-27 1989-05-30 Compaq Computer Corporation Personal computer having normal and high speed execution modes
EP0238090B1 (fr) * 1986-03-20 1997-02-05 Nec Corporation Micro-ordinateur capable d'accéder à une mémoire interne à un temps d'accès variable désiré
US4884198A (en) * 1986-12-18 1989-11-28 Sun Microsystems, Inc. Single cycle processor/cache interface
US4837730A (en) * 1987-02-06 1989-06-06 Scientific Computer Systems Corporation Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations
US5325513A (en) * 1987-02-23 1994-06-28 Kabushiki Kaisha Toshiba Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode
US5305452A (en) * 1987-10-23 1994-04-19 Chips And Technologies, Inc. Bus controller with different microprocessor and bus clocks and emulation of different microprocessor command sequences
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
CA2066542A1 (fr) * 1991-05-24 1992-11-25 Richard Bealkowski Methode et dispositif pour accroitre la capacite de la memoire adressable physique
JP2551338B2 (ja) * 1993-07-23 1996-11-06 日本電気株式会社 情報処理装置
GB2281421B (en) * 1993-08-23 1998-04-01 Advanced Risc Mach Ltd Integrated circuit
US5504877A (en) * 1994-11-29 1996-04-02 Cordata, Inc. Adaptive DRAM timing set according to sum of capacitance valves retrieved from table based on memory bank size
US5987581A (en) * 1997-04-02 1999-11-16 Intel Corporation Configurable address line inverter for remapping memory
US7231537B2 (en) * 2003-07-03 2007-06-12 Micron Technology, Inc. Fast data access mode in a memory device
US9367450B1 (en) * 2013-10-07 2016-06-14 Altera Corporation Address arithmetic on block RAMs

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444528A (en) * 1966-11-17 1969-05-13 Martin Marietta Corp Redundant computer systems
GB1265006A (fr) * 1968-11-08 1972-03-01
GB1245072A (en) * 1969-02-17 1971-09-02 Automatic Telephone & Elect Improvements in or relating to checking and fault indicating arrangements
US3651475A (en) * 1970-04-16 1972-03-21 Ibm Address modification by main/control store boundary register in a microprogrammed processor
US3681758A (en) * 1970-04-29 1972-08-01 Northrop Corp Data acquisition unit with memory
US3660646A (en) * 1970-09-22 1972-05-02 Ibm Checking by pseudoduplication
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US3725870A (en) * 1970-12-24 1973-04-03 Pitney Bowes Alpex Parallel-access data file system
US3810119A (en) * 1971-05-04 1974-05-07 Us Navy Processor synchronization scheme
US3763474A (en) * 1971-12-09 1973-10-02 Bell Telephone Labor Inc Program activated computer diagnostic system

Also Published As

Publication number Publication date
GB1477236A (en) 1977-06-22
US3984812A (en) 1976-10-05

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: BURROUGHS CORP.

Effective date: 19910331