BE717007A - - Google Patents
Info
- Publication number
- BE717007A BE717007A BE717007DA BE717007A BE 717007 A BE717007 A BE 717007A BE 717007D A BE717007D A BE 717007DA BE 717007 A BE717007 A BE 717007A
- Authority
- BE
- Belgium
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1967P0042436 DE1285538C2 (de) | 1967-06-23 | 1967-06-23 | Dekadisch aufgebauter Frequenzteiler zur Erzeugung von Teilimpulsfolgen mit einer feinstufig dekadisch einstellbaren Anzahl moeglichst gleichmaessig ueber die Zeit verteilter Impulse |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BE717007A true BE717007A (en:Method) | 1968-12-23 |
Family
ID=7378622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BE717007D BE717007A (en:Method) | 1967-06-23 | 1968-06-21 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3568070A (en:Method) |
| JP (1) | JPS499253B1 (en:Method) |
| BE (1) | BE717007A (en:Method) |
| DE (1) | DE1285538C2 (en:Method) |
| FR (1) | FR1569478A (en:Method) |
| GB (1) | GB1188909A (en:Method) |
| SE (1) | SE358526B (en:Method) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3875377A (en) * | 1972-12-29 | 1975-04-01 | Alsthom Cgee | Noise generator |
| US8552957B2 (en) * | 2009-02-02 | 2013-10-08 | Apple Inc. | Liquid crystal display reordered inversion |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL135894C (en:Method) * | 1963-10-24 | 1900-01-01 | ||
| GB1041143A (en) * | 1964-03-18 | 1966-09-01 | Marconi Co Ltd | Improvements in or relating to frequency dividers |
| US3351778A (en) * | 1964-10-08 | 1967-11-07 | Motorola Inc | Trailing edge j-k flip-flop |
| US3401343A (en) * | 1966-05-23 | 1968-09-10 | Sperry Rand Corp | High speed binary counter employing j-k flip-flops |
-
1967
- 1967-06-23 DE DE1967P0042436 patent/DE1285538C2/de not_active Expired
-
1968
- 1968-04-05 US US719035A patent/US3568070A/en not_active Expired - Lifetime
- 1968-06-20 SE SE08454/68A patent/SE358526B/xx unknown
- 1968-06-20 GB GB29466/68A patent/GB1188909A/en not_active Expired
- 1968-06-20 JP JP43042297A patent/JPS499253B1/ja active Pending
- 1968-06-21 BE BE717007D patent/BE717007A/xx unknown
- 1968-06-24 FR FR1569478D patent/FR1569478A/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1285538C2 (de) | 1973-08-09 |
| FR1569478A (en:Method) | 1969-05-30 |
| GB1188909A (en) | 1970-04-22 |
| SE358526B (en:Method) | 1973-07-30 |
| DE1285538B (de) | 1968-12-19 |
| US3568070A (en) | 1971-03-02 |
| JPS499253B1 (en:Method) | 1974-03-02 |