BE623250A - - Google Patents

Info

Publication number
BE623250A
BE623250A BE623250DA BE623250A BE 623250 A BE623250 A BE 623250A BE 623250D A BE623250D A BE 623250DA BE 623250 A BE623250 A BE 623250A
Authority
BE
Belgium
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of BE623250A publication Critical patent/BE623250A/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
BE623250D 1961-10-05 BE623250A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3590861A GB945528A (en) 1961-10-05 1961-10-05 Improvements in or relating to multiplying circuits

Publications (1)

Publication Number Publication Date
BE623250A true BE623250A (de)

Family

ID=10382886

Family Applications (2)

Application Number Title Priority Date Filing Date
BE623250D BE623250A (de) 1961-10-05
BE612106D BE612106A (de) 1961-10-05

Family Applications After (1)

Application Number Title Priority Date Filing Date
BE612106D BE612106A (de) 1961-10-05

Country Status (3)

Country Link
BE (2) BE612106A (de)
DE (1) DE1167567B (de)
GB (1) GB945528A (de)

Also Published As

Publication number Publication date
DE1167567B (de) 1964-04-09
GB945528A (en) 1964-01-02
BE612106A (de)

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