GB945528A - Improvements in or relating to multiplying circuits - Google Patents
Improvements in or relating to multiplying circuitsInfo
- Publication number
- GB945528A GB945528A GB3590861A GB3590861A GB945528A GB 945528 A GB945528 A GB 945528A GB 3590861 A GB3590861 A GB 3590861A GB 3590861 A GB3590861 A GB 3590861A GB 945528 A GB945528 A GB 945528A
- Authority
- GB
- United Kingdom
- Prior art keywords
- relating
- multiplying circuits
- multiplying
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BE623250D BE623250A (en) | 1961-10-05 | ||
BE612106D BE612106A (en) | 1961-10-05 | ||
GB3590861A GB945528A (en) | 1961-10-05 | 1961-10-05 | Improvements in or relating to multiplying circuits |
DEJ22456A DE1167567B (en) | 1961-10-05 | 1962-10-03 | Circuit arrangement for multiplying binary numbers |
FR911411A FR82419E (en) | 1961-10-05 | 1962-10-05 | Binary multiplication circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB3590861A GB945528A (en) | 1961-10-05 | 1961-10-05 | Improvements in or relating to multiplying circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
GB945528A true GB945528A (en) | 1964-01-02 |
Family
ID=10382886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3590861A Expired GB945528A (en) | 1961-10-05 | 1961-10-05 | Improvements in or relating to multiplying circuits |
Country Status (3)
Country | Link |
---|---|
BE (2) | BE612106A (en) |
DE (1) | DE1167567B (en) |
GB (1) | GB945528A (en) |
-
0
- BE BE623250D patent/BE623250A/xx unknown
- BE BE612106D patent/BE612106A/xx unknown
-
1961
- 1961-10-05 GB GB3590861A patent/GB945528A/en not_active Expired
-
1962
- 1962-10-03 DE DEJ22456A patent/DE1167567B/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE1167567B (en) | 1964-04-09 |
BE612106A (en) | |
BE623250A (en) |
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