BE520677A - - Google Patents

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Publication number
BE520677A
BE520677A BE520677DA BE520677A BE 520677 A BE520677 A BE 520677A BE 520677D A BE520677D A BE 520677DA BE 520677 A BE520677 A BE 520677A
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BE
Belgium
Prior art keywords
conductivity
type
germanium
transistron
zones
Prior art date
Application number
Other languages
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of BE520677A publication Critical patent/BE520677A/fr
Priority claimed from US596943A external-priority patent/US2994018A/en
Priority claimed from US603531A external-priority patent/US2999195A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Description

       

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  PROCEDE DE   PREPARATION   DE DISPOSITIFS UTILISANT DES COUCHES DE TRANSITION ENTRE SEMI-CONDUCTEURS DES TYPES P & N. 



   Le présent perfectionnement concerne l'utilisation des couches de jonction entre semi-conducteurs de conductibilité des types P & N, préparés suivant le procédé objet du brevet principal et de ses perfectionnements. pour la réalisation de transistrons de structure nouvelle. 



   Le brevet principal concerne un mode de fabrication des éléments   semi-conducteurs   comportant dans la masse au moins une couche de jonction entre une zone présentant la conductibilité du type P et une zone présentant la conductibilité du type N; les éléments   semi-conducteurs   ainsi réalisés servent à fabriquer des redresseurs et des amplificateurs à transistrons. 



   Conformément au présent   perfectionnement,,,   on réalise des transistrons de structure nouvelle dont les caractéristiques sont améliorées par rapport à celles des appareils construits suivant Part antérieur. En particulier, le coefficient   [alpha]   d'amplification du   courante   défini comme la dérivée partielle du courant de collecteur par rapport ou courant d'émetteur est sensiblement plus élevé. 



  En outre.le transistron décrit fonctionne de façon satisfaisante en haute fréquence et la densité des courants traversant les couches de jonction est uniforme sur toute leur surface. 



   Les transistrons construits conformément à 1?invention comprennent une plaquette mince de germanium mono-cristallin d'un type de conductibilité donné sur les grandes faces duquel on fixe des sphérules ou des baguettes d'impuretés d'un type de conductibilité   opposée   l'épaisseur de la   zone   de ger-   manium   ayant conservé sa conductibilité initiale étant faible par rapport à la dimension transversale de la zone de diffusion des impuretés. 

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   Pour mieux faire comprendre les caractéristiques techniques et les avantages de l'invention, on vane décrire un exemple de réalisation, étant entendu que celui-ci n'a aucun caractère limitatif quant aux modes de mise en oeuvre de l'invention et aux applications qu'on peut en faire. 



   - Les figures 1 & 2 sont respectivement des vues en élévation coupée et en plan   d'un   transistron conforme à l'invention. 



   - La figure 3 représente une vue en coupe partielle d'un transistron conforme à l'invention muni de radiateurs; des transistrons analogues à ceux des figures 1 & 2, sauf en ce qui concerne la forme des surfaces de dif-   fusion,   sont représentés sur les figures 4 & 5. 



   - Le dispositif des figures 6 & 7 est analogue à celui des figures 4 & 5, mais il comporte une électrode de collecteur de grande dimension et plusieurs électrodes d'émetteur. 



   .Afin de simplifier la description des types de transistron réalisés selon l'invention, on supposera que le semi-conducteur mono-cristallin utilisé est du germanium de conductibilité du type N et que l'impureté du type accepteur, qui permet de créer des zones de conductibilité du type P, est de l'indium de préférence; l'emploi de ce dernier élément étant avantageux dans le cas d'une production importante. 



   Il est évident que le transistron type jonction conforme à l'invention, peut être du type N - P - N. 



   Sur les figures 1 & 2, on a représenté un transistron type jonction selon   l'invention,   comprenant un mono-cristal de germanium de conductibilité du type N ayant la forme d'une plaquette carrée 1 dont l'épaisseur est inférieure à 0,1 millimètre et de préférence comprise entre   0,012   et   0,036   mm 
Les zones 2 & 3 de conductibilité du type P sont formées sur les grandes faces opposées de la plaquette, la couche de germanium de conductibilité du type N qui les sépare étant mince; son épaisseur est très inférieure à la dimension transversale des zones de conductibilité du type P, c'est-à-dire à leur dimaétre, lorsqu'elles sont circulaires. On utilise de préférence pour la constitution des zones 2 & 3, les procédés de diffusion des impuretés décrits dans le brevet principal. 



   Suivant cette méthode,qui permet de déterminer avec précision la disposition relative des zônes de différentes   conductibilités.,   la profondeur de pénétration des impuretés est contrôlée par réglage de la température et de la durée du phénomène de diffusion. 



   Les zônes de conductibilité du type P de la plaquette 1 sont obtenues en disposant sur chacune de ces grandes-faces des sphérules d'indium 4 & 5 dont on provoque la diffusion contrôlée selon la méthode citée plus haut. 



  Des fils de connexion 6 & 7 peuvent être fixés., par soudure,aux sphérules 4 & 5 au cours du processus de diffusion$ ces deux fils constituent les conducteurs de sortie d'émetteur et de collecteur. 



   Le dispositif représenté comporte une électrode de base constituée   d'une   feuille rectangulaire 8 de métal ou d'un alliage métallique convenable tel le   fernico.   La feuille 8 est percée en son centre d'une ouverture circulaire 9 de diamètre supérieur à celui de la sphérule d'indium qu'elle entoure. 



  L'électrode de base 8 est fixée à la plaquette de germanium 1 au moyen d'une soudure convenable 10. Cette dernière doit permettre d'établir entre les éléments 1 & 8 un contact franc, de faible résistance., qui ne modifie pas les caractéristiques de conductibilité de la plaquette 1. Celle-ci ayant. dans 

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 le dispositif décrit, la conductibilité de type N, on peut utiliser une sou- dure contenant une impureté du type "donneur" tel l'antimoine. 



   L'examen de la figure 1 montre que la zone 11 de conductibilité initiale. du type N, est d'épaisseur faible par rapport aux deux z8nes de conductibilité du type P. Lorsque les zones de diffusion d'impuretés sont circulaires, comme dans le cas des figures 1 & 2, l'épaisseur de la zone 11 peut être comprise entre le 1/10e et le   1/100e   du diamètre de ces deux 2ô- nes; dans le cas du transistron décrit; elle est de l'ordre de 2,5/100 mm. 



   Par suite de la méthode de fabrication employée, les régions 4 &
5 dites "émetteur" et "collecteur" ont une faible   résistivité.   Il en résulte qu'un courant d'intensité suffisante traverse l'électrode d'émetteur et qu'un assez grand nombre de porteurs de charges est fourni à la base. Il en résulte également que, dans la région dite collecteur,l'augmentation du nombre des trous positifs ou lacunes lorsque la température croît est évitée. Grâce à I' homogénéité des zones de conductibilité N & P et la forme des couches de jonc- tion entre semi-conducteurs de différents types de conductibilité, le disposi- tif décrit a des caractéristiques satisfaisantes en haute fréquence puisque tous les porteurs de charge parcourent, de l'émetteur au collecteur, des trajectoires de longueur équivalente.

   La connexion de le'électrode de base dans un circuit d'utilisation peut être réalisée par soudure sur le bord de la plaquette ou, sur ses grandes faces, en leurs parties éloignées des couches de jonction entre semi-conducteurs de type de conductibilité différents, de façon à ne pas provoquer de modification de ces jonctions P-N, ni de perturbation des trajectoires de charges électriques entre émetteur et collecteur. 



   La figure 3 représente un transistron conforme à l'invention équipé d'un système de refroidissement; il comporte plusieurs éléments identiques à ceux du dispositif de la figure 1, lesquels sont repérés par les mêmes numéros. 



  Des disques à rebord 12 qui servent de radiateurs, sont fixés par soudure aux sphérules 4 & 5 et comportent en leur centre une saillie à symétrie circulaire 13 qui facilite l'exécution des soudures. Les dimensions des radiateurs peuvent être importantes; ceux-ci peuvent faire partie de l'enveloppe; on obtient alors un ensemble analogue à celui décrit dans le premier perfectionnement -N  513.934 du   4/9/52-   au brevet principal. 



   Sur les figures 4 & 5, on a représenté respectivement en plan et en élévation un transistron analogue à celui de la figure 1, mais dont les zones de diffusion ne sont plus circulaires mais de forme allongée. Dans ce but. les sphérules 4 à 5 ont été remplacées par des bâtonnets d'impuretés du type accepteur. 



   Le dispositif des figures 6 & 7 est une polyode à jonctions; il comporte une plaquette constituée de germanium mono-cristallin 17; l'électrode de collecteur est formée par un dépôt d'impuretés de grande surface (16) tandis que plusieurs électrodes d'émetteur constituées par des bâtonnets 18 sont fixées sur la face opposée de la plaquette 17. Entre les bâtonnets 18 un ensemble d'éléments conducteurs .19.. qui peuvent être connectés par la barre 20, forment l'électrode de base. Les conducteurs 19 peuvent être en fernico; ils sont soudés à la plaquette 17 par une soudure convenable 21 dans les mêmes conditions que l'électrode 9 et la plaquette 1 de la figure 1. 



  Le dispositif des figures 6 & 7 comporte une électrode de collecteur de grande dimension qui peut être facilement refroidie par un radiateur ou un liquide réfrigérant. Puisque la dissipation de chaleur de l'électrode de collecteur est toujours relativement importante, ce montage est tout-à-fait   satisfai-   sant. 



   Bien que l'on ait décrit et représenté plusieurs formes de réalisation de   l'invention,   il est évident qu'on ne désire pas se limiter à ces formes particulières données à titres d'exemples et sans aucun carac- 

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  PROCESS FOR PREPARING DEVICES USING TRANSITION LAYERS BETWEEN SEMICONDUCTORS OF P & N TYPES.



   The present improvement relates to the use of junction layers between conductivity semiconductors of the P & N types, prepared according to the process which is the subject of the main patent and of its improvements. for the realization of transistrons of new structure.



   The main patent relates to a method of manufacturing semiconductor elements comprising in the mass at least one junction layer between an area exhibiting P-type conductivity and a region exhibiting N-type conductivity; the semiconductor elements thus produced are used to manufacture rectifiers and transistron amplifiers.



   In accordance with the present improvement ,,, transistrons of a new structure are produced, the characteristics of which are improved compared to those of the devices built according to the prior art. In particular, the current amplification coefficient [alpha] defined as the partial derivative of the collector current with respect to or emitter current is appreciably higher.



  Furthermore, the transistron described operates satisfactorily at high frequency and the density of the currents passing through the junction layers is uniform over their entire surface.



   The transistrons constructed in accordance with the invention comprise a thin wafer of mono-crystalline germanium of a given conductivity type on the large faces of which spherules or rods of impurities of a type of conductivity opposite the thickness of the germanium zone having retained its initial conductivity being low compared to the transverse dimension of the impurity diffusion zone.

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   In order to better understand the technical characteristics and the advantages of the invention, we will describe an exemplary embodiment, it being understood that the latter is in no way limiting as regards the embodiments of the invention and the applications which 'we can do it.



   - Figures 1 & 2 are respectively sectional elevation and plan views of a transistron according to the invention.



   - Figure 3 shows a partial sectional view of a transistron according to the invention provided with radiators; transistrons similar to those of Figures 1 & 2, except for the shape of the diffusing surfaces, are shown in Figures 4 & 5.



   - The device of Figures 6 & 7 is similar to that of Figures 4 & 5, but it comprises a large collector electrode and several emitter electrodes.



   In order to simplify the description of the types of transistron produced according to the invention, it will be assumed that the mono-crystalline semiconductor used is germanium of N-type conductivity and that the acceptor-type impurity, which makes it possible to create zones of type P conductivity, is preferably indium; the use of the latter element being advantageous in the case of significant production.



   It is obvious that the junction type transistron according to the invention can be of the N - P - N type.



   In FIGS. 1 & 2, a junction-type transistron has been shown according to the invention, comprising a germanium mono-crystal of N-type conductivity having the shape of a square plate 1, the thickness of which is less than 0.1 millimeter and preferably between 0.012 and 0.036 mm
The P-type conductivity zones 2 & 3 are formed on the large opposite sides of the wafer, the layer of N-type conductivity germanium which separates them being thin; its thickness is much less than the transverse dimension of the P-type conductivity zones, that is to say their size, when they are circular. For the constitution of zones 2 & 3, the impurity diffusion processes described in the main patent are preferably used.



   According to this method, which makes it possible to determine with precision the relative arrangement of the zones of different conductivity., The depth of penetration of the impurities is controlled by adjusting the temperature and the duration of the diffusion phenomenon.



   The P-type conductivity zones of the wafer 1 are obtained by placing indium 4 & 5 spherules on each of these large faces, the controlled diffusion of which is caused by the method mentioned above.



  Lead wires 6 & 7 may be attached by soldering to spherules 4 & 5 during the diffusion process - these two wires constitute the emitter and collector output conductors.



   The device shown comprises a base electrode made of a rectangular sheet 8 of metal or of a suitable metal alloy such as fernico. The sheet 8 is pierced in its center with a circular opening 9 of diameter greater than that of the indium spherule which it surrounds.



  The base electrode 8 is fixed to the germanium plate 1 by means of a suitable solder 10. The latter must make it possible to establish between the elements 1 & 8 a clear contact, of low resistance., Which does not modify the conductivity characteristics of the wafer 1. The latter having. in

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 With the device described, the N-type conductivity, it is possible to use a solder containing an impurity of the "donor" type such as antimony.



   Examination of Figure 1 shows that the zone 11 has initial conductivity. of type N, is thin compared to the two conductivity z8nes of type P. When the impurity diffusion zones are circular, as in the case of Figures 1 & 2, the thickness of the zone 11 can be between 1 / 10th and 1 / 100th of the diameter of these two 2ones; in the case of the transistron described; it is of the order of 2.5 / 100 mm.



   Due to the manufacturing method employed, regions 4 &
So-called "emitter" and "collector" have low resistivity. As a result, a current of sufficient magnitude flows through the emitter electrode and a sufficient number of charge carriers are supplied to the base. It also results from this that, in the region called collector, the increase in the number of positive holes or vacancies when the temperature increases is avoided. Thanks to the homogeneity of the N & P conductivity zones and the shape of the junction layers between semiconductors of different types of conductivity, the device described has satisfactory characteristics at high frequency since all the charge carriers run through. , from the emitter to the collector, trajectories of equivalent length.

   The connection of the base electrode in a circuit of use can be carried out by soldering on the edge of the wafer or, on its large faces, in their parts remote from the junction layers between semiconductors of different conductivity type, so as not to cause any modification of these PN junctions, nor any disturbance of the trajectories of electric charges between emitter and collector.



   FIG. 3 represents a transistron in accordance with the invention equipped with a cooling system; it comprises several elements identical to those of the device of FIG. 1, which are identified by the same numbers.



  Flanged discs 12 which serve as radiators, are fixed by welding to the spherules 4 & 5 and have in their center a circularly symmetrical projection 13 which facilitates the execution of the welds. The dimensions of the radiators can be important; these can be part of the envelope; we then obtain an assembly similar to that described in the first improvement -N 513,934 of 4/9 / 52- to the main patent.



   In Figures 4 & 5, there is shown respectively in plan and in elevation a transistron similar to that of Figure 1, but whose diffusion zones are no longer circular but elongated. For this purpose. spherules 4 to 5 have been replaced by rods of impurities of the acceptor type.



   The device of Figures 6 & 7 is a polyode with junctions; it comprises a wafer made of mono-crystalline germanium 17; the collector electrode is formed by a deposit of impurities of large surface (16) while several emitter electrodes constituted by rods 18 are fixed on the opposite face of the wafer 17. Between the rods 18 a set of conductive elements .19 .. which can be connected by bar 20, form the base electrode. Conductors 19 can be in fernico; they are welded to the plate 17 by a suitable solder 21 under the same conditions as the electrode 9 and the plate 1 of FIG. 1.



  The device of Figures 6 & 7 has a large collector electrode which can be easily cooled by a radiator or coolant. Since the heat dissipation of the collector electrode is always relatively large, this arrangement is quite satisfactory.



   Although several embodiments of the invention have been described and shown, it is obvious that we do not wish to limit ourselves to these particular forms given by way of example and without any character.

 <Desc / Clms Page number 4>

Claims (1)

tére restrictif et que,, par conséquent toutes les variantes ayant même principe et même objet que les dispositions indiquées ci-dessus rentreraient comme elles dans le cadre de l'inventiono- RESUME. being restrictive and that, consequently, all the variants having the same principle and the same object as the arrangements indicated above would come within the scope of the invention. Transistrons de structure nouvelle et de caractéristiques améliorées comprenant une plaquette mince de germanium mono-cristallin d'un type de conductibilité donné, sur les grandes faces de laquelle on fixe des sphérules ou des baguettes d'impuretés d'un type de conductibilité opposé, l' épaisseur de la zone de germanium ayant conservé sa conductibilité- initiale étant faible par rapport à la dimension transversale de la zone de diffu- sion des impuretéso Transistrons of new structure and improved characteristics comprising a thin wafer of mono-crystalline germanium of a given conductivity type, on the large faces of which spherules or rods of impurities of an opposite conductivity type are fixed, l 'thickness of the germanium zone having retained its initial conductivity being small compared to the transverse dimension of the impurity diffusion zone
BE520677D 1950-09-29 BE520677A (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US18749050A 1950-09-29 1950-09-29
US18747850A 1950-09-29 1950-09-29
US29356852A 1952-06-14 1952-06-14
US748845XA 1952-10-25 1952-10-25
US596943A US2994018A (en) 1950-09-29 1956-07-10 Asymmetrically conductive device and method of making the same
US603531A US2999195A (en) 1952-06-14 1956-08-13 Broad area transistors

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1032409B (en) * 1954-10-15 1958-06-19 Sylvania Electric Prod Transistor base connection
DE1041161B (en) * 1954-08-30 1958-10-16 Gen Electric Area transistor arrangement
DE1092131B (en) * 1956-08-24 1960-11-03 Philips Nv Transistor and process for its manufacture
DE1106876B (en) * 1957-10-04 1961-05-18 Siemens Ag Process for the production of semiconductor devices
US3087098A (en) * 1954-10-05 1963-04-23 Motorola Inc Transistor
DE1167986B (en) * 1955-10-29 1964-04-16 Siemens Ag Flat transistor with a disk-shaped semiconductor body and with strip-shaped base and emitter electrodes

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1041161B (en) * 1954-08-30 1958-10-16 Gen Electric Area transistor arrangement
US3087098A (en) * 1954-10-05 1963-04-23 Motorola Inc Transistor
DE1032409B (en) * 1954-10-15 1958-06-19 Sylvania Electric Prod Transistor base connection
DE1167986B (en) * 1955-10-29 1964-04-16 Siemens Ag Flat transistor with a disk-shaped semiconductor body and with strip-shaped base and emitter electrodes
DE1092131B (en) * 1956-08-24 1960-11-03 Philips Nv Transistor and process for its manufacture
DE1106876B (en) * 1957-10-04 1961-05-18 Siemens Ag Process for the production of semiconductor devices

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