AUPQ234099A0 - Routing interfaces into a backplane - Google Patents

Routing interfaces into a backplane

Info

Publication number
AUPQ234099A0
AUPQ234099A0 AUPQ2340A AUPQ234099A AUPQ234099A0 AU PQ234099 A0 AUPQ234099 A0 AU PQ234099A0 AU PQ2340 A AUPQ2340 A AU PQ2340A AU PQ234099 A AUPQ234099 A AU PQ234099A AU PQ234099 A0 AUPQ234099 A0 AU PQ234099A0
Authority
AU
Australia
Prior art keywords
backplane
routing interfaces
routing
interfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AUPQ2340A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to AUPQ2340A priority Critical patent/AUPQ234099A0/en
Publication of AUPQ234099A0 publication Critical patent/AUPQ234099A0/en
Priority to AU45068/00A priority patent/AU4506800A/en
Priority to PCT/FI2000/000697 priority patent/WO2001015361A1/fr
Priority to AU65740/00A priority patent/AU6574000A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1641—Hierarchical systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13003—Constructional details of switching devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13076—Distributing frame, MDF, cross-connect switch
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13204—Protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13216—Code signals, frame structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13292—Time division multiplexing, TDM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1332—Logic circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AUPQ2340A 1999-08-19 1999-08-19 Routing interfaces into a backplane Abandoned AUPQ234099A0 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AUPQ2340A AUPQ234099A0 (en) 1999-08-19 1999-08-19 Routing interfaces into a backplane
AU45068/00A AU4506800A (en) 1999-08-19 2000-07-04 Routing interfaces into a backplane
PCT/FI2000/000697 WO2001015361A1 (fr) 1999-08-19 2000-08-17 Interfaces d'acheminement en fonds de panier
AU65740/00A AU6574000A (en) 1999-08-19 2000-08-17 Routing interfaces into a backplane

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AUPQ2340A AUPQ234099A0 (en) 1999-08-19 1999-08-19 Routing interfaces into a backplane

Publications (1)

Publication Number Publication Date
AUPQ234099A0 true AUPQ234099A0 (en) 1999-09-09

Family

ID=3816515

Family Applications (1)

Application Number Title Priority Date Filing Date
AUPQ2340A Abandoned AUPQ234099A0 (en) 1999-08-19 1999-08-19 Routing interfaces into a backplane

Country Status (2)

Country Link
AU (1) AUPQ234099A0 (fr)
WO (1) WO2001015361A1 (fr)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2545670B1 (fr) * 1983-05-04 1985-07-05 Billy Jean Claude Multiplexeur, demultiplexeur et equipement de multiplexage-demultiplexage a trames reconfigurables
GB2182228A (en) * 1985-10-02 1987-05-07 Gen Electric Plc Signal handling device
AU627953B2 (en) * 1989-11-15 1992-09-03 Digital Equipment Corporation Integrated communications link having dynamically allocatable bandwidth and a protocol for transmission or allocation information over the link
JPH05276584A (ja) * 1991-09-26 1993-10-22 Fujitsu Ltd 多重化装置におけるタイムスロット並び換え装置
US5495426A (en) * 1994-01-26 1996-02-27 Waclawsky; John G. Inband directed routing for load balancing and load distribution in a data communication network
EP0722237A1 (fr) * 1994-12-20 1996-07-17 International Business Machines Corporation Procédé pour transmettre des signaux vocaux dans un réseau de commutation de paquets
US6061358A (en) * 1997-02-13 2000-05-09 Mcdata Corporation Data communication system utilizing a scalable, non-blocking, high bandwidth central memory controller and method
US5905385A (en) * 1997-04-01 1999-05-18 Advanced Micro Devices, Inc. Memory bits used to couple look up table inputs to facilitate increased availability to routing resources particularly for variable sized look up tables for a field programmable gate array (FPGA)

Also Published As

Publication number Publication date
WO2001015361A1 (fr) 2001-03-01

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