AU8076591A - Universal galois field multiplier - Google Patents

Universal galois field multiplier

Info

Publication number
AU8076591A
AU8076591A AU80765/91A AU8076591A AU8076591A AU 8076591 A AU8076591 A AU 8076591A AU 80765/91 A AU80765/91 A AU 80765/91A AU 8076591 A AU8076591 A AU 8076591A AU 8076591 A AU8076591 A AU 8076591A
Authority
AU
Australia
Prior art keywords
universal
galois field
field multiplier
multiplier
galois
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU80765/91A
Inventor
Edoardo Mastrovito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU8076591A publication Critical patent/AU8076591A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
AU80765/91A 1990-06-15 1991-05-31 Universal galois field multiplier Abandoned AU8076591A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9002124A SE466822B (en) 1990-06-15 1990-06-15 DEVICE FOR MULTIPLICATION OF TWO ELEMENTS IN A GALOIC BODY
SE9002124 1990-06-15

Publications (1)

Publication Number Publication Date
AU8076591A true AU8076591A (en) 1992-01-07

Family

ID=20379773

Family Applications (1)

Application Number Title Priority Date Filing Date
AU80765/91A Abandoned AU8076591A (en) 1990-06-15 1991-05-31 Universal galois field multiplier

Country Status (3)

Country Link
AU (1) AU8076591A (en)
SE (1) SE466822B (en)
WO (1) WO1991020028A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768168A (en) * 1996-05-30 1998-06-16 Lg Semicon Co., Ltd. Universal galois field multiplier
GB9622539D0 (en) * 1996-10-30 1997-01-08 Discovision Ass Galois field multiplier for reed-solomon decoder
GB9627069D0 (en) * 1996-12-30 1997-02-19 Certicom Corp A method and apparatus for finite field multiplication
JP3833412B2 (en) * 1999-04-09 2006-10-11 富士通株式会社 Expression data generation apparatus and method in finite field operation
US6662346B1 (en) 2001-10-03 2003-12-09 Marvell International, Ltd. Method and apparatus for reducing power dissipation in finite field arithmetic circuits
JPWO2004001701A1 (en) * 2002-06-20 2005-10-20 株式会社日立製作所 Sign arithmetic unit
EP2434650A1 (en) * 2010-09-23 2012-03-28 Panasonic Corporation Reed-Solomon encoder with simplified Galois field multipliers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805037A (en) * 1972-02-22 1974-04-16 J Ellison N{40 th power galois linear gate
US4251875A (en) * 1979-02-12 1981-02-17 Sperry Corporation Sequential Galois multiplication in GF(2n) with GF(2m) Galois multiplication gates
JPH0680491B2 (en) * 1983-12-30 1994-10-12 ソニー株式会社 Finite field arithmetic circuit

Also Published As

Publication number Publication date
WO1991020028A1 (en) 1991-12-26
SE9002124D0 (en) 1990-06-15
SE9002124L (en) 1991-12-16
SE466822B (en) 1992-04-06

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