AU766009B2 - A voltage monitor for a power line - Google Patents

Description

P/00/0 1 1 28/5/9 1 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT IF, ';-:eciro n.s Y4j i aU-4 Australian Protcct'v' Beetrcr-ic3 Pty Ltd Name of Applicant: Actual Inventor Address for service is: WiAlly NeIlse WRAY ASSOCIATES 239 Adelaide Terrace Perth, WA 6000 Attorney code: WR Invention Title: "A Voltage Monitor For A Power Line" The following statement is a full description of this invention, including the best method of performing it known to me:- -2-

TITLE

"A Voltage Monitor For A Power Line" FIELD OF THE INVENTION This invention relates to a voltage monitor for a power line. The invention is concerned with the protection of appliances from fluctuations in the voltage on the power line.

BACKGROUND ART oooo Appliances relying on electrical power can be damaged by the supplied voltage deviating below the expected voltage (referred to as a brown-out) or by the 10 supplied voltage exceeding the expected voltage, referred to as a voltage spike.

Brown-outs and voltage spikes can cause damage to sensitive electronic equipment and also to inductive devices such as motors and pumps which can be burnt out.

In order to address this situation, voltage monitors of various types have been devised.

Australian Patent 579,383 discloses an appliance plug with a built-in circuit breaker which is arranged to disconnect the power line from the connected appliance in the event of a voltage spike. The invention disclosed in patent 579,383 does not provide protection in the event of a brown-out.

US Patent 5,319,514 describes a digital voltage and phase monitor for an AC power line in which the AC voltage is monitored for both voltage spikes and brown-outs. In the event of either of these conditions, the AC power line is disconnected from any appliance connected to the digital voltage and phase monitor. In order to prevent oscillation of the circuit disclosed in US Patent 5,319,514, the circuit provides in-built delay between the power being disconnected and being reconnected in order to allow any oscillations present in the voltage and phase monitor to attenuate. The AC power line voltage is monitored during this delay period to ensure it remains within an acceptable voltage range prior to the power being reconnected.

Although the monitor described in US Patent 5,319,514 is useful when protecting most appliances, inductive loads such as motors and pumps present special problems. In particular, when power is reconnected, a motor or pump can draw a significant current which in turn can temporarily result in a reduction of the AC power line voltage. In some circumstances, this can cause the monitor to retrigger because the monitor believes a brown-out has occurred. This can result in a hammer effect, with the monitor switching on and then switching off whenever power is reapplied. This hammer effect can strain and damage the motor or pump connected to the circuit.

15 DISCLOSURE OF THE INVENTION In accordance with one aspect of this invention, there is provided a voltage "monitor for a power line, comprising: switching means provided in-line with the power line; a control circuit responsive to the power line to produce a signal corresponding to the voltage on the power line; the control circuit including comparison means arranged to determine if the signal is within a prescribed range of acceptable signal values; the control circuit being in communication with the switching means to control the operation thereof, the control circuit arranged to control the switching means to disconnect the power line if the signal is not within the prescribed range of acceptable signal values; the control circuit further including first delay means providing, upon disconnection of the power line, a first prescribed delay between the signal returning within the prescribed range of acceptable values and the control circuit controlling the switching means to reconnect the power line, and second delay means providing, upon reconnection -4of the power line, a second prescribed delay before the control circuit will again disconnect the power line.

Preferably, the switching means comprises a relay.

More preferably, the relay is arranged to be in the normally-open state in the absence of power being applied thereto.

Preferably, said voltage monitor is provided in a housing including a plug for connection to a mains power outlet, and a socket for receiving a plug of an appliance to be protected.

oooo Preferably, the control circuit is responsive to the signal during the first delay, wherein if the signal moves outside of the allowable range during the first delay, the first delay is reset.

Preferably, the voltage monitor further includes a status indicator for indicating whether the voltage on the power line is within the acceptable range, or high or low.

oo Preferably, said control circuit includes processor means.

More preferably, the first delay and the second delay are achieved using a counting loop or timer in the processor means.

Preferably, the processor means is arranged to flash the status indicator for a prescribed time prior to the expiry of the first delay.

Preferably, the first delay is selectable from a first list of prescribed delays.

More preferably, the first list includes delays of O, 1, 3 and 5 minutes.

Preferably, the second delay is selectable from a second list of prescribed delays.

More preferably, the second list includes delays of Os or 800ms.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described, with reference to two embodiments thereof and the accompanying drawings, in which: Figures 1 and 2 show a housing for the apparatus of the embodiments; Figure 3 is a schematic circuit of the first preferred embodiment; and Figure 4 is a schematic drawing of the second embodiment of the invention.

BEST MODE(S) FOR CARRYING OUT THE INVENTION The embodiments of the invention are directed towards voltage monitors for use 10 with AC power lines, although it should be appreciated that the invention is equally applicable to DC power lines.

Figures 1 and 2 show a housing 10 common to both of the embodiments. The housing 10 has a socket 12 and a plug 14 provided thereon. The plug 14 has pins 16 arranged to be received within a mains power socket. The configuration 15 of the pins 16 is shown for Australian use, although it should be appreciated that the pins 16 can be configured for use in other countries without departing from the invention.

The socket 2 includes apertures 18 arranged to receive pins from the plug of an appliance to be connected to the voltage monitor. Again, the arrangement of the apertures are in accordance with Australian conditions, although this can be altered for other countries without departing from the invention.

The first embodiment is shown in figure 3 and comprises a voltage monitor shown generally at 20. Three power lines 22', 22" and 22"' are shown, each extending -6from a pin 16 through to a corresponding aperture 18. In the embodiment shown in figure 3, the power line 22' corresponds with the active power line, the power line 22" corresponds with the neutral line and the power line 22"' corresponds with the earth line.

The voltage monitor 20 comprises a switching means in the form of a relay 24 and a control circuit including a microprocessor 26.

The control circuit includes a power supply composed of an AC capacitor 28 and a positive temperature coefficient resistor 30 arranged to act as a fuse connected in series to the active power line 22'. A 24 Volt zener diode 32 extends between 10 the resistor 30 and the neutral power line 22". Diode 34 and capacitor 36 o. provides half-wave rectification and smoothing, respectively to provide a 24 Volt o: DC supply. A 5 Volt voltage regulator 38 is connected to the 24 Volt DC supply "by resistor 40 to provide a 5 Volt power rail at 42.

.The relay 24 is connected to the 24 Volt supply via a LED 44, which acts as a status indicator when the relay 24 is active. A diode 46 is placed in reverse bias :across the relay 24 and LED 44 to reduce the effects of EMF resulting from the switching of the relay 24. The relay 24 is also connected to transistor 48, which is controlled by the microprocessor 26 via resistor By the microprocessor 26 switching the transistor 48 on or off, the relay 24 can be switched so as to connect or disconnect the active power line 22'. When the transistor 48 is switched on, power will flow through the relay 24 via the diode 44 to connect the active power line 22'. Accordingly, the LED 44 acts as a status indicator for when the power line 22' is connected. The relay 24 is normally open to provide fail-safe operation, in that the power line 22' will be disconnected until the voltage monitor is repaired or replaced.

The control circuit further includes a voltage divider formed of three resistors 52, 54 and 56 and diode 60 provided in series between the active power line 22' and -7the neutral power line 22". A 12 Volt zener diode 58 is provided in parallel across the diode 60 and resistor 56 to limit the voltage input to the microprocessor as will be described hereinafter. By selecting the values of the resistors 52, 54 and 56 the voltage appearing across the resistor 56 will be a proportion of the voltage -on the active power line 22'.

Diode 60 provides half-wave rectification to provide at the output thereof of voltage proportional to the voltage on the active power line 22' during the positive cycle. The output from the diode 60 is connected to a t-network composed of two tantalium capacitors 62 and 64 and resistor 66. The capacitor 62 and 64 and 10 the resistor 66 provide smoothing of the voltage output from the diode 60. The voltage across the capacitor 64 is input to an analog-to-digital input port of the microprocessor 26 via a buffer resistor 68.

The voltage presented to the analog-to-digital port of the microprocessor 26 via S. the buffer resistor 68 forms a signal corresponding to the voltage on the active power line 22.

A range of acceptable signal values are provided by means of potentiometers .*"and 72 each connected between the 5 Volt power rail 42 and the neutral power °;4"line 22". The variable output of the potentiometers 70 and 72 are input to the microprocessor 26 via two further analog-to-digital input ports through buffer resistors 74 and 76 respectively. The potentiometer 70 provides a signal corresponding to the upper-most acceptable value for the signal and the potentiometer 72 provides the lower most acceptable value for the signal.

Three LEDs 78, 80 and 82 are connected to outputs of the microprocessors 26 via resistors 84, 86 and 88, respectively. The LEDs 78, 80 and 82 provide status indicators corresponding to a high voltage present on the active power line 22', a low voltage present on the active power line 22', and delay-mode operation of the voltage monitor 20, respectively as will be described below.

The voltage monitor 20 further includes a first delay selector 90 and a second delay selector 92. In the embodiment, the delay selectors 90 and 92 are provided as links on a printed circuit board, although in other embodiments switches may be provided, such as DIP switches.

In use, the microprocessor 26 monitors the voltage on the active power line 22' via the signal and compares the signal with the reference signals received from the potentiometers 70 and 72. If the signal is between the values of the reference signals, the voltage is considered to be acceptable and monitoring continues.

If the signal is above the reference signal provided from the potentiometer 70 or 10 below the reference signal provided by the potentiometer 72, a voltage spike or brown-out condition exists, respectively. In this situation, the microprocessor 26 switches off the transistor 48 which in turn removes power from the relay 24 which reverts to its normally-open condition. Any appliances connected to the :socket 18 are thereby disconnected from the active power line 22'. The 15 corresponding LED 78 or 80, respectively is also powered to provide a status indicator.

Next, the microprocessor 26 continues to monitor the voltage on the active power line 22 via the signal. When the signal falls within the acceptable range of values according to the signals from the potentiometers 70 and 72, a first delay period is started. The length of the delay period is determined according to the delay selector 90, which can be altered between 0 seconds (no delay), 1 minute, 3 minutes and 5 minutes. The LEDs 78 and 80 are then switched off.

If the first delay period indicated by the delay selector 90 is zero, then the microprocessor 26 switches the transistor 48 on as soon as the voltage on the power line 22' falls within the acceptable range.

Otherwise, the LED 82 is powered to indicate that the microprocessor 26 is in delay period. During this first delay period, the transistor 48 and relay 24 are still off and the microprocessor 26 monitors the voltage on the active power line 22'.

If the voltage on the active power line 22' stays within the acceptable range of values for the entire first delay period, the delay period is ended and the transistor 48 switched on to activate the relay 24 and reconnect the active power line 22'.

Toward the end of the first delay period, the microprocessor 26 flashes the LED 82 to provide warning to the user. When the delay period is ended, power is removed from the LED 82.

When the transistor 48 is switched on at the end of a first delay period to activate the relay 24 and reconnect the active power line 22', the microprocessor 26 enters a second delay period. The length of the second delay period is *.**.determined according to the second delay selector 92, which can select between either 0 seconds or 800 milliseconds. During the second delay period, the microprocessor 26 will not disconnect the power line 22' by switching the S°transistor 48 off, irrespective of the voltage level appearing on the active power 15 line 22'. This feature is intended for use with inductive loads such as motors and pumps to prevent the voltage monitor from immediately disconnecting the active power line 22' after having reconnected it due to the voltage drop caused from the "°.•excessive current drawn by the inductive load. At the end of the second delay period, operation of the microprocessor returns to normal, monitoring the voltage 20 on the active power line 22' as described above.

In this regard, it is to be noted that the capacitors 62 and 64 provide a slight delay between voltages appearing on the active power line 22' and the signal reaching the microprocessor 26. Because of the active control of the microprocessor 26 it is referred that this delay is very small in this embodiment.

The second embodiment is shown in figure 4, with like reference numerals denoting like parts to those used in relation to the first embodiment. The principal difference between the first and second embodiments is that the microprocessor 26 in the first embodiment has been replaced with operational amplifiers in the second embodiment.

Operational amplifier 100 performs a comparison between the signal via resistor 68' and the reference signal provided from potentiometer 70. Operational amplifier 102 performs a comparison between the signal via resistor 68" and the reference signal from potentiometer 72. Feedback resistors 104, 106 provide to positive feedback the operational amplifiers 100 and 102.

The outputs of the operational amplifiers 100 and 102 are connected together via buffer resistors 108 and 110, respectively to form the non-inverting input of operational amplifier 112. A pull-up resistor 114 is also connected to the noninverting input of the operational amplifier 112. The inverting input of the 10 operational amplifier 112 consists of a voltage divider formed from resistors 116 and 118. The output of operational amplifier 112 is connected to the resistor to control the switching of the transistor 48. When the voltage on the active *°:*•power line 22' is within the acceptable region set by the potentiometers 70 and 72, the outputs of the operational amplifiers 100 and 102 are high. As a result, 15 the output of the operational amplifier 112 will also be high and the transistor 48 S•will be switched on.

The first delay period is provided by operational amplifier 120, the output of which is connected to the non-inverting input of operational amplifier 112 via resistor 122. The output of the operational amplifier 120 is connected to the inverting 20 input thereof via resistor 124, diode 126 and resistor 128. A capacitor 130 and resistor 132 are provided in parallel and connected to the junction of diode 126 and resistor 128. When the voltage on the active power line 22' is in the allowable region determined by the potentiometers 70 and 72, the capacitor 130 is charged via resistor 124 and diode 126. The non-inverting input of the operational amplifier 102 is connected to the 24 Volt power supply via resistor 134 and to the output of the operational amplifier 120 via resistor 136. The output of the operational amplifier 112 is connected to the non-inverting input of the operational amplifier 120 via capacitor 138 and diode 140 in reverse bias. A resistor 142 extends between the 24 Volt power supply and the junction of the diode 140 and the capacitor 138.

-11 In the second embodiment, the 5 Volt voltage regulator has been replaced with a 12 Volt voltage regulator 144.

In use, the voltage on the active power line 22' is monitored via the operational amplifiers 100 and 102. If the voltage on the active power line 22' is within the allowable region as determined by the potentiometer 70 and 72, the output to the operation amplifiers 100 and 102 are high. In turn, the capacitor 130 connected to the inverting input of operational amplifier 120 is charged via diode 126 and resistor 124. The output of the operational amplifier 112 is high and the transistor 48 is thereby switched on, energising the relay 24 and connecting the power line 22'.

oooo the voltage on the power line 22' rises above the upper tolerance set by the potentiometer 70 or falls below the lower tolerance set by the potentiometer 72, °C•the output of the corresponding operational amplifier 100 and 102 will be low.

The corresponding diode 78 or 80 will then be lit and the output of the operational amplifier will be pulled low, thereby switching the transistor 48 off and deenergising the relay 24 to disconnect the active power line 22'. When the output of the operational amplifier 112 switches from high to low, a pulse is sent to the non-inverting input of operational amplifier 120 via capacitor 138, which switches the output of the operational amplifier 120 low. The output of the operational S 20 amplifier 120 will remain low until the capacitor 130 is discharged via the resistor 132. Accordingly, the operational amplifier 120, the capacitor 130 and the resistor 132 and associated bias circuitry provide the first delay period.

The second delay period is provided by the capacitor 64 having a sufficient value to provide the desired delay period. This manner of providing the second delay period is less preferable then that described in relation to the first embodiment, and accordingly the first embodiment is preferred to the second embodiment.

It should be appreciated that the scope of this invention is not limited to the particular embodiment described above.

-12- Throughout the specification, unless the context requires otherwise, the word "comprise" or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers.

Claims (1)

13- THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS 1. A voltage monitor for a power line, comprising: switching means provided in- line with the power line; a control circuit responsive to the power line to produce a signal corresponding to the voltage on the power line; the control circuit including comparison means arranged to determine if the signal is within a prescribed range of acceptable signal values; the control circuit being in communication with the switching means to control the operation thereof, the control circuit arranged to control the switching means to disconnect the power line if the signal is not within the prescribed range of acceptable signal values; 10 the control circuit further including first delay means providing, upon ~disconnection of the power line, a first prescribed delay between the signal °ego returning within the prescribed range of acceptable values and the control circuit controlling the switching means to reconnect the power line, and second delay means providing, upon reconnection of the power line, a second 15 prescribed delay before the control circuit will again disconnect the power line. 2. A voltage monitor as claimed in claim 1, wherein the control circuit is responsive to the signal during the first delay, whereby if the signal moves outside of the allowable range during the first delay, the first delay is reset. 3. A voltage monitor as claimed in any one of the preceding claims, further comprising a status indicator for indicating whether the voltage on the power line is within the acceptable range, or high or low. 4. A voltage monitor as claimed in any one of the preceding claims, wherein said control circuit includes processor means. A voltage monitor as claimed in claim 4, wherein the first delay and the second delay are achieved using a counting loop or timer in the processor means. LI -14- 6. A voltage monitor as claimed in claim 4 or 5, wherein the processor means is arranged to flash the status indicator for a prescribed time prior to the expiry of the first delay. 7. A voltage monitor as claimed in any one of the preceding claims, wherein the first delay is selectable from a first list of prescribed delays. 8. A voltage monitor as claimed in claim 7, wherein said first list includes a delay of 0 seconds, 1 minute, 3 minutes and 5 minutes. 9. A voltage monitor as claimed in any one of the preceding claims, wherein the second delay is selectable from a second list of prescribed delays. 10 10.A voltage monitor as claimed in claim 9, wherein the second list includes delays of Os or 800ms. 11.A voltage monitor as claimed in any one of the preceding claims, wherein the switching means comprises a relay. 12.A voltage monitor as claimed in claim 11, wherein the relay is arranged to be in the normally-open state in the absence of power being applied thereto. 13.A voltage monitor as claimed in any one of the preceding claims, wherein said voltage monitor is provided in a housing including a plug for connection to a mains power outlet, and a socket for receiving a plug of an appliance to be protected. Dated this 18th day of September 1998. Australian Protective Electronics Pty Ltd Wray Associates Perth, Western Australia Patent Attorneys for the Applicant