AU733785B2

AU733785B2 - Method and apparatus for decoding a video signal

Info

Publication number: AU733785B2
Application number: AU20104/97A
Authority: AU
Inventors: Robert John Milland; Kalimin Sunardi
Original assignee: Individual
Current assignee: Individual
Priority date: 1996-05-08
Filing date: 1997-05-07
Publication date: 2001-05-24
Anticipated expiration: 2017-05-07
Also published as: AU2010497A

Description

-1- P/00/01 1 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT oo oooo oooo o o oooo Invention Title: Method and Apparatus for Decoding A Video Signal The following statement is a full description of this invention, including the best method of performing it known to us: GH REF: P24908-A/PJT:MB -2- METHOD AND APPARATUS FOR DECODING A VIDEO SIGNAL Field of the Invention The present invention relates to the field of decoding of video signals as distributed by a pay TV distributor or the like.

Background of the Invention Providers of pay TV channel services often utilise various methods to encode or encrypt their transmitted signals so that customers are unable to receive a decode version of the signal without a valid decoder so as to reverse the encoding of the signal.

In any transmitted signal, various methods are utilised to encode the signal. These methods can include various manipulations of the video signal including inverting the signal, utilising an transmitted signal which regularly shifts in amplitude, modulating the signal with various other signals including sine waves etc., eliminating or suppressing the synchronisation signals, inverting or rotating the synchronisation signals and modulating the signals intensity.

Summary of the Invention Preferably, the present invention provides for a video signal decoder which is able to decode encrypted video •c signals which utilise an arbitrary combination of the ego• 25 aforementioned techniques.

In accordance with a first aspect of the present invention, there is provided an apparatus for decoding an *..encoded video signal to produce a normal video signal, said normal video signal including a sync signal and a video 30 information signal, said encoded video signal being encoded ee. by at least intermittently inverting a normal video signal :and by at least intermittently omitting sync pulses from a sync signal of the normal video signal, said apparatus comprising: tuner means for selecting a desired video signal from a video signal input; -3signal processing means connected to said tuner means for eliminating unwanted transients in said desired video signal so as to produce a filtered video signal; video buffer means connected to said signal processing means and adapted to produce a non-inverted video signal and an inverted video signal from said filtered video signal; sync extraction means connected to said video buffer means for extracting a non-inverted sync signal from the non-inverted video signal and for extracting an inverted sync signal from the inverted video signal; sync drop out detection means connected to said sync extraction means for determining when sync pulses are missing from the non-inverted sync signal and the inverted sync signal, for producing a first dropout pulse signal when a sync pulse is missing from the non-inverted sync signal, and for producing a second dropout pulse signal when a sync pulse is missing from the inverted sync signal; signal selection means, the signal selection means 20 including an output, and the signal selection means being arranged to receive the non-inverted video signal and the inverted video signal from the video buffer means and to transfer the non-inverted video signal to the output when •c the video information signal in the non-inverted video 25 signal is of a positive polarity, and to transfer the inverted video signal to the output when the video information signal in the inverted video signal is of a positive polarity; oo ~video information signal extraction means for 30 extracting a video information signal from the output of the signal selection means; ego• sync signal reconstitution means arranged to generate a reconstituted sync signal using the non-inverted sync signal extracted by the sync extraction means, the inverted sync signal extracted by the sync extraction means, the first dropout pulse signal and the second dropout pulse signal; -3asignal combining means arranged to combine the video information signal extracted by the video information signal extraction means with the reconstituted sync signal generated by the sync signal reconstitution means to thereby produce a decoded video signal having a decoded sync signal and a decoded video information signal; and switching buffer means adapted to detect whether said desired video signal is in an encoded or non-encoded form using said first and second dropout pulse signals and to select said filtered video signal or said decoded video signal for output using said detection as to whether said desired video signal is in an encoded or non-encoded form.

Preferably signal processing means includes a sample and hold circuit which samples an inputted signal over a first interval of time (sampling time) and outputs the sampled signal for a second interval of time (holding time.

Further preferably sample and hold circuit outputs a substantially constant signal during said holding time and, during said sampling time, outputs a signal that starts at a previous holding time value and changes at a predetermined rate so as to reduce the difference between :the circuit output value and circuit input value until either the end of the sampling period or the output value is substantially equal to the input period preferably the 25 rate is substantially constant.

The apparatus can further provide a second sample and hold circuit utilised to filter said desired video signal to produce an output utilised by an automatic gain control circuit so as to maintain automatic gain control.

3 a.* -4- Brief Description of the Drawings Notwithstanding any other forms which may fall within the scope of the present invention, preferred forms of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Fig. 1 illustrates a first portion of the preferred embodiment; Fig. 2 illustrates the operation of the sample and hold processing circuit as utilised in the preferred embodiment; Fig. 3 illustrates a further portion of the preferred embodiment.

Fig. 4 illustrates one form of implementation of the sample and hold circuit of Fig. 1; Fig. 5 illustrates one form of circuit for producing normal and inverted video outputs; Fig 6 illustrates a circuit for detection of sync dropouts; Fig. 7 illustrates one form of circuit for automatic 20 encrypted signal detection and activation of a switching buffer; and Fig. 8 illustrates one form of implementation of the circuit as depicted in Fig. 3.

Description of Preferred and Other Embodiments 25 In Fig. 1, there is illustrated of first portion of the preferred embodiment. The preferred embodiment operates in generally under the control of a microcontroller 11 which is a CPU unit which acts in conjunction with memory 12 to control the preferred environment which includes utilisation of keypad 13, infrared LED sensor 14, and display LED 16 driven by driver unit 15. The operation of these units provides a standard interface whose operation is well known in the art and hence will not be described further hereinafter.

The CPU 11 also acts to control the selection of an input signal from a TV antennae 18, or a microwave antennae 19.

The preferred embodiment can also be readily adapted to Spec:24908a url U* u. imu±' jL i u rzitA ILl ova#~ 009I 1 utilise other forms of input signals such as satellite input and cable TV input as required.

The microwave antennae is operated by power on/off unit 22 and an antennae selector unit 23 operates to select which antennae signal will be sent to a tuner block 24 which outputs the desired select signal under the control of CPU unit 11.

A video audio VIF unit 26 is provided for conversion of an input signal to a corresponding output which removes various undesirable signal fluctuations. The VIF unit 26 utilises the two pulsating sample and hold circuits 28, The operation of the sample and hold circuit will now be described with reference to F'ig.2. The pulsating sample and hold circuit operates during a regular (or alternatively random) clock interval to sample 42 an input signal 41. The samples are held for a holding period 43 before -re-samnpling is activated. During the re-sample period eg. 44 the previous sample value is utilised and the difference between the current input value 41 and the sample value eg. 46 is integrated 47 over the sampling period 44 to produce a final output sample value 49 which is held until the next sampling interval. This process is then continued during subsequent sample intervals with the sample output eg. 50 tracking the input signal eg. 41. The sample output 50 therefore acts to eliminate any high frequency spikes in the input signal 41 and provides a stable output signal while still tracking the input signal 41.

Returning to Fig. 1, the two pulsating sample and hold circuits 28, 30 act to replace their corresponding input signals with the first circuit 28 being utilised for the video output and a second uAGCO pulsating sample and hold circuit 30 being utilised for automatic gain control.

Further, the pulsating sample and hold circuit output is also utilised for input to an automatic fine tuning unit 32.

02/04 '01 MON 16:19 [TX/RX NO 8916] 6- The output of the video audio VIF unit 26 is fed two video buffer units 34, 35. The first video unit buffer 34 buffers the signal and outputs the buffered version of the signal. A second video buffer unit 35 outputs an inverted signal with respect to its input and acts to correct any inversion of the input signal.

The video buffer outputs are forwarded to composite sync processing units 38, 39 which extract the sync signal eg. 40 from the video signal for separate processing. The sync signal is also forwarded to identical sync drop out detector unit 42, 44 which determines when the sync pulse is missing and outputs a sync drop out pulse eg. 45 when a missing sync pulse has been detected. The output of the sync drop out detectors is forwarded to an auto detector unit 48 which detects whether a normal or scrambled signal S" has been received and outputs a signal 49 for switching buffer 50 which selects between its two inputs being a normal video input 51 and a de-scrambled video input 52.

The output 54 of the video buffer 50 becomes the video output signal-56 after modulation by video and audio modulator 58. The video audio modulator 58 being conventional.

*Referring now to Fig. 3, the drop out pulse signals 43 in additional sync signals 40, 41 are forwarded a 25 composite and drop out sync processing unit 60. The unit acts to reconstruct the synchronisation signals which are output 61, 63 to a video processing circuit 64 which reconstructs the video signal by adding the missing synchronisation signals. A video selector 66 selects which of the input video signals 57, 58 are correct and the synchronisation remover circuit 69 removes synchronisation from the signals which is later added in via video processing circuit 64. A final buffer 72 buffers the video output signal to form subsequent video signal 52 which is fed to the switchingbuffer 50 of Fig.

1. The processed video signal 52 having correct synchronisation for the video signal.

Turning now to Fig. 4, there is illustrated one form of Spec: 2 4 9 08a suitable electrical circuitry of the sample and hold circuits 28, 30 of Fig. i. The sample and hold circuit is based around a feedback op-amp 80 which acts to integrate a signal difference during an active period.

In Fig. 5, there is illustrated one form of circuit which performs the combined function of video buffering of a normal 81 and inverted 82 video output signals given a video input signal 83.

In Fig. 6, there is illustrated one form of circuitry to implement the composite sync processing circuit 38, 39 of Fig. 1 in addition to the sync dropout detection 42, 44 of Fig. 1. The video input 90 is processed so as to produce a video output signal 91 in addition to a horizontal sync circuit 92 with the horizontal sync circuit 92 being oo utilised in feedback loop 93 to process the input video S"The sync dropout detector 42, 44 monitors the horizontal sync output 92 and produces an output signal 95 when the horizontal sync signal is found to be missing.

Turning to Fig. 7, there is illustrated one form of suitable implementation of the auto detector circuit 48 and switching buffer 50 of Fig. i. The auto detector utilises the sync dropout detection inputs for determining which of switches 98, 99 should be activated so as to switch either normal video or inverted video to video output 100.

In Fig. 8 there is illustrated one form of circuit implementation of the circuitry described with reference to Fig. 3. The horizontal sync dropout signal 110 is the first processed to clean it up before being utilised to control the selection of a video input for amplification by an amplification stage 112, the amplifier being entirely conventional. The output of amplifier stage 112 is buffered 113 before being fed to a timer circuit 115 which determines the length of time for the amplifier, the output being again buffered 116 before being again utilised to filter out the horizontal sync signal 118 via switch 119, the output of switch 119 being active high when sync is required. The output of switch 119 is forwarded to inverter 121 which, is active high when sync is not required. This is combined 122 Spec:24908a -8with a regenerated sync signal output from inverter 124 so as to form a composite sync signal 125. The composite sync output is forwarded to a video processing circuit which combines the composite sync signal 125 with a video input to produce video output 128 which is returned to the circuit of Fig. i.

The forgoing circuit illustrates merely one example implementation of the present invention and it would be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiment without departing from the spirit or scope of the invention as broadly described. The present embodiment is, therefore, to be considered in all respects to be illustrative and o 15 not restrictive.

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a Spec:24908a

Claims

1. An apparatus for decoding an encoded video signal to produce a normal video signal, said normal video signal including a sync signal and a video information signal, said encoded video signal being encoded by at least intermittently inverting a normal video signal and by at least intermittently omitting sync pulses from a sync signal of the normal video signal, said apparatus comprising: tuner means for selecting a desired video signal from a video signal input; signal processing means connected to said tuner means for eliminating unwanted transients in said desired video signal so as to produce a filtered video signal; video buffer means connected to said signal processing means and adapted to produce a non-inverted video signal and an inverted video signal from said filtered video signal; sync extraction means connected to said video buffer means for extracting a non-inverted sync signal from the non-inverted video signal and for extracting an inverted sync signal from the inverted video signal; sync drop out detection means connected to said sync extraction means for determining when sync pulses are 25 missing from the non-inverted sync signal and the inverted sync signal, for producing a first dropout pulse signal when a sync pulse is missing from the non-inverted sync signal, and for producing a second dropout pulse signal when a sync pulse is missing from the inverted sync signal; signal selection means, the signal selection means *including an output, and the signal selection means being arranged to receive the non-inverted video signal and the inverted video signal from the video buffer means and to transfer the non-inverted video signal to the output when the video information signal in the non-inverted video signal is of a positive polarity, and to transfer the °nverted video signal to the output when the video information signal in the inverted video signal is of a positive polarity; video information signal extraction means for extracting a video information signal from the output of the signal selection means; sync signal reconstitution means arranged to generate a reconstituted sync signal using the non-inverted sync signal extracted by the sync extraction means, the inverted sync signal extracted by the sync extraction means, the first dropout pulse signal and the second dropout pulse signal; signal combining means arranged to combine the video information signal extracted by the video information signal extraction means with the reconstituted sync signal generated by the sync signal reconstitution means to thereby produce a decoded video signal having a decoded sync signal and a decoded video information signal; and switching buffer means adapted to detect whether said desired video signal is in an encoded or non-encoded form using said first and second dropout pulse signals and to select said filtered video signal or said decoded video signal for output using said detection as to whether said desired video signal is in an encoded or non-encoded form.

2. An apparatus as claimed in claim 1 wherein said signal processing means includes a sample and hold circuit which samples an inputted signal over a first interval of time (sampling time) and outputs the sampled signal for a second interval of time (holding time).

3. An apparatus as claimed in claim 2 wherein said sample and hold circuit outputs a substantially constant signal during said holding time and, during said sampling time, outputs a signal that starts at a previous holding time value and changes at a predetermined rate so as to reduce the difference between the circuit output value and circuit input value until either the end of the sampling ST period or the output value is substantially equal to the /-input period. -11

4. An apparatus as claimed in claim 3 wherein said rate is substantially constant.

An apparatus as claimed in any preceding claim further comprising a second sample and hold circuit utilised to filter said desired video signal to produce an output utilised by an automatic gain control circuit so as to maintain automatic gain control.

6. An apparatus for decoding an encoded video signal substantially as hereinbefore described with reference to the accompanying drawings.

7. A method of decoding an encoded video signal substantially as hereinbefore described with reference to the accompanying drawings. g *o.