AU721666B2

AU721666B2 - Switching regulator, method, and control circuit therefor

Info

Publication number: AU721666B2
Application number: AU65669/96A
Authority: AU
Inventors: Lawrence Joseph Borle
Original assignee: POWERSEARCH Ltd; Curtin University of Technology
Current assignee: POWERSEARCH Ltd; Curtin University of Technology
Priority date: 1995-09-22
Filing date: 1996-09-17
Publication date: 2000-07-13
Anticipated expiration: 2016-09-17
Also published as: AU6566996A

Description

P/00/Oi 28/5/91 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

CO MPLETE-SPECIFI CATION STAN DARD-PATENT C. 0 a*

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C C *0.e C Name of Applicant: Actual Inventor(s): Address for service is: POWERSEARCH LIMIT7ED, CURTIN UNIVERSITY OF TECHNOLOGY AND LAWRENCE JOSEPH BORLE LAWRENCE JOSEPH BORLE WRAY ASSOCIATES 239 Adelaide Terrace Perth, WA 6000 Attorney code: WR Invention Title: "SWITCHING REGULATOR, METHOD, AND CONTROL

CIRCUIT-THEREFOR"

Details of Associated Provisional Application No(s): PN5582 The following statement-is-al-ull -description-of-thlis-invention, including the-best method of performing it known-to-me:-

A

-2- This invention relates to switching regulators for use in switching power converters or power supplies, and particularly a technique for controlling the switching action in a switching regulator.

In current controlled power converters, power flow is controlled by forcing the current in an inductance (hereafter referred to as the inductor) to follow a reference current. This can be achieved by duty-cycle modulating the voltage across the inductor so that the average voltage results in the desired current flow. The prime purpose of a current control method is to force the current in the converter to match a specific desired value represented by a reference current.

An ideal current control method would accurately follow the reference current with zero average current error (hereinafter ZACE) in each switching period. A current control with the ZACE characteristic will force the area of any one excursion (example: to match the area of the previous excursion in the opposite direction. This will result in an average current error of zero for the 15 period of the two excursions, which is one switching period I ie(t).dt 0, about a predetermined reference current level).

The advantages of using a ZACE type current control method in an ac-dc PWM converter include: low order current harmonics in the inductor can be effectively 20 eliminated, even in the presence of line voltage harmonics, or dc link voltage harmonics; the ac current can be controlled independently of DC link voltage variations, within the constraints of a minimum link voltage; and the transient response is the fastest possible for the given power 25 circuit topology; l power flow control is achieved by forcing the current to follow a generated current reference waveform, which can have real, reactive, and harmonic content, each of which are directly and independently controllable.

-3- Of the many current control methods that have been proposed in the past, some have the ZACE characteristic. Perhaps the most well known is hysteresis current control, as described in United States patent specification US5045991, which entails controlling the current between two reference values, one higher than the actual desired value, and the other lower than the actual desired value.

This basic method has the advantage of being simple and robust, but it has a widely varying switching frequency. In many power converter applications, a varying switching frequency may cause problems in the operation of certain loads. While an absolutely fixed switching frequency may not be necessary, in many applications, it is certainly desirable to restrict the switching frequency to a predictable and confined band.

Many methods of adapting hysteresis current control to a fixed switching frequency have been proposed. These methods vary the hysteresis band continuously so as to maintain a constant switching period. One way is to use the measured circuit voltages and the known inductance to continuously calculate a hysteresis band which should deliver a fixed switching frequency.

This technique is described in "Frequency Stabilisation and Synchronisation of Free Running Current-Mode-Controlled Converters", authored by R Redl and N O0 Sokal, IEEE Power Electronics Specialists Conference, 1986, pp 519-530.

This technique can be prone to error as the inductance value changes, and it lacks the robustness of a technique which relies solely on the current error signal, in view of difficulties with trying to predict or measure voltage levels and inductance values.

e* It has been considered that for a converter to be robust and simple, it would be 25 preferable for a current control method to use the current error signal alone in the determination of switching instants. One such method, described in "Improved Current Control Technique of VSI PWM Inverters with Constant Modulation Frequency and Extended Voltage Range", authored by L Malesani et al, IEEE Transactions on Industry Applications, Vol 27 No. 2 pp 365-369, Mar/Apr 1991, describes generating a varying hysteresis band using a phase- -4locked-loop. In some applications, it has been found that this method may not be completely successful in maintaining a fixed switching frequency.

Slope-generated hysteresis is another fixed switching frequency hysteresis method which uses the slopes of the error current waveform to calculate the appropriate hysteresis band. This was presented by the inventor and C V Nayar in a paper titled "ZACE Current Controlled Power Flow for AC-DC Power Converters", at the 1994 IEEE Power Electronics Specialists Conference proceedings pp 539-545. This method has the disadvantage that it differentiates the current error signal to derive the slopes (rates of change) used in the calculation of the required hysteresis band. This differentiation is susceptible to noise, so the output must be filtered. The result is that the effect of changes in the slope are delayed, and the switching frequency band is wider than might otherwise be achievable. Furthermore, the differentiation and calculations required take considerable circuitry to achieve.

Non-hysteresis type current control methods which are intended to achieve a ~ZACE type control with a fixed switching frequency have also been proposed.

.";"Average Current Control" (ACC) is perhaps the best of such methods. ACC is *oo* described in a paper authored by W Tang et al, titled "Small-Signal Modelling of :Average Current-Mode Control", IEEE Trans Power Electronics, vol 8 no. 2 pp 112-119. However, a control method according to this technique must filter the S*i error signal at a frequency well below the switching frequency so as to maintain coo° stability. The result is a reduced bandwidth but there is also a slower transient response.

o* o g. The present invention seeks to provide a ZACE type current control with optimal transient response (ie so that the transient response is limited only by the power circuit topology, and not by the current control technique) and a narrow switching frequency band, which uses only the current error signal in a relatively i inexpensive circuit to determine appropriate switching instants.

In accordance with one aspect of the present invention there is provided a control circuit for a switching regulator having at least one inductor, said control circuit comprising: a first input for receiving a current measurement signal proportional to the magnitude and direction of current in said at least one inductor, or proportional to the difference in current in any two of said at least one inductors; a reference current generating means for deriving a reference current signal representing the magnitude and direction of the desired current or current waveform in said inductor, or representing the difference in the desired current or current waveform in two said inductors; a processing means for receiving said current measurement signal and said reference current signal, and determining the timing of switching instances; and an output to control switching of said at least one inductor between a positive voltage (charging configuration while the current is positive) and a negative voltage state (discharging configuration while the current is positive) in response to said processing means; wherein said processing means determines the difference between said current measurement signal and said reference current signal to generate a current error signal representative of the difference or representative of the polarity of 20 the difference; and wherein said processing means includes timing calculation means for calculating timing of switching instances to achieve an average current error signal close to zero, based on timing of previous switching instances relative to zero crossing times of the current error signal during a previous excursion 25 Where the first input receives a current measurement signal proportional to the difference in current in two said inductors, a multiphase system is contemplated, where two of the phases are switched and the third phase is held as a standing phase. The standing phase is the phase whose voltage is opposite in polarity to both of the other phases, or generally opposite in polarity to both of the other phases and at least exceeding (either positively or negatively) the voltage of any f the other phases.

-6- Preferably said timing calculation means determines a next switching instant time relative to zero-crossing of said current error signal, based on a previous time of a previous said switching instant relative to zero-crossing of said current error signal.

Preferably said timing calculation means determines a next switching instant time relative to zero-crossing of said current error signal, based on the time of a previous said switching instant, relative to the time between zero-crossing times of the current signal immediately before and after said previous said switching instant.

The determination of timing for a next said switching instant from any zero crossing of the current error signal, may be based on switching instant timing relative to any previous excursion of the current error signal, but preferably for most accurate control is based on the switching instant timing relative to the immediate previous excursion of the current error signal. Basing the switching 15 instant timing relative to any excursion of the current error signal more than three switching periods of the current error signal previous to the instant under determination would be expected to produce a noticeable lag in reaction of the .*.control circuit to changing circuit parameters.

go Further, the determination of timing for a next said switching instant from any zero crossing of the current error signal, may be based on switching instant timing relative to any previous current error signal excursion either above or below zero, regardless of whether the switching instant under determination occurs during a positive or negative going excursion of the current error signal.

In one configuration of the control circuit where the next switching instant timing is being based on previous switching instant timing during a current error signal excursion in a half switching period ending at the most recent current error signal Szero crossing, or in a half period ending 1, 2, or 3 switching periods before the ost recent current error signal zero crossing, said timing calculation means tyjperates to switch a positive voltage across said inductor approximately when -7- S= "i and operates to switch a negative voltage across said inductor approximately when r where: -Tbf is the calculated time when switching is to occur after the current error signal has crossed zero falling, Taf is the measured time the current error signal was above zero after a said switching instant (above zero and falling), Ta is the measured time the current error signal was above zero in a previous excursion, Ts 2 is the desired time between successive current error signal zero crossings is the desired switching period), Tar is the calculated time when switching is to occur after the current error signal has crossed zero rising, Tbr is the measured time the current error signal was below zero after a said switching instant (below zero and rising), Tb is the measured time the current error signal was below zero in a previous excursion.

In an alternative configuration of the control circuit where the next switching instant timing is based on previous switching instant timing during a current error signal excursion in a half period ending one, three, five, or seven current error signal zero crossings before the most recent current error signal zero crossing, said timing calculation means operates to switch a negative voltage across said (TT

L

inductor approximately when and operates to switch a positive voltage across said inductor approximately when T -b p where: Tar is the calculated time when switching is to occur after the current error signal has crossed zero rising, "ITarp is the measured time the current error signal was above zero before a said

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-8previous switching instant (above zero and rising), Ta is the measured time the current error signal was above zero in a previous excursion, Tsw 2 is the desired time between successive current error signal zero crossings is the desired switching period), Tbf is the calculated time when switching is to occur after the current error signal has crossed zero falling, Tbfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and Tb is the measured time the current error signal was below zero in a previous excursion.

In either configuration it will be understood that the arrangements of the control circuit where the next switching instant timing is based on previous timings 1, 2, or 3 periods of the current error signal previous to the half period referred to above, are less preferred as increasing the delay between measurement and control is believed to increase the switching frequency band, and decrease the transient response.

Switching a positive voltage across the inductor causes a positive rate of change of current in the inductor, and conversely, switching a negative voltage across the inductor causes a negative rate of change of current in the inductor.

In a solely hardware based implementation, preferably said first input is connected to a first circuit for deriving said current measurement signal coco proportional to the magnitude and direction of the current in the inductor.

Preferably said output provides a binary signal which is to be used to control the switching of an active controlling device.

Preferably said active controlling device comprises a semiconductor switch or -witches.

-9- In accordance with a second aspect of the present invention there is provided a method of controlling a switching regulator having at least one inductor, comprising deriving a current measurement signal proportional to the magnitude and direction of current in said at least one inductor, or proportional to the difference in current in two of said at least one inductors; deriving a reference current signal representing the magnitude and direction of the desired current or current waveform in said at least one inductor, or representing the difference in the desired current or current waveform in two of said at least one inductors; determining the difference between said current measurement signal and said reference current signal to generate a current error signal representative of the difference; and calculating the timing of switching instances to control switching of said at least one inductor to achieve an average current error signal close to zero, based on timing of previous switching instances relative to zero crossing of the current error signal during a previous excursion.

::Preferably in the step of calculating said switching instances, a new time from zero-crossing of said current error signal to a said switching instant is calculated, 20 based on a previous time of a previous said switching instant relative to zerocrossing of said current error signal.

.e Preferably in the step of calculating said switching instances, a new time from S. zero-crossing of said current error signal to a said switching instant is calculated, 2 based on a previous time of a previous said switching instant relative to the time 25 between zero-crossing times of the current error signal immediately before and after said previous said switching instant.

As discussed in relation to the control circuit, the determination of timing for a next said switching instant from any zero crossing of the current error signal, may be based on switching instant timing relative to any previous excursion of the current error signal, but preferably for most accurate control is based on the switching instant timing relative to the immediate previous excursion of the current error signal. Basing the switching instant timing relative to any excursion of the current error signal more than three periods of the current error signal previous to the instant under determination would be expected to produce a noticeable lag in reaction of the control circuit to changing circuit parameters.

Further, the determination of timing for a next said switching instant from any zero crossing of the current error signal, may be based on switching instant timing relative to any previous current error signal excursion either above or below zero, regardless of whether the switching instant under determination occurs during a positive or negative going excursion of the current error signal.

Where a new switching instant is being determined based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1, 2, or 3 periods before the most recent current error signal zero crossing, in the step of calculating said switching instances, a positive voltage is switched to said o *inductor approximately when and a negative voltage is switched to said inductor approximately when Tr Twh whr-) e Tbf is the calculated time when switching is to occur after the current error 20 signal has crossed zero falling, Taf is the measured time the current error signal was above zero after a said :switching instant (above zero and falling), Ta is the measured time the current error signal was above zero, Ts, 2 is the desired time between successive current error signal zero crossings is the desired switching period), Tar is the calculated time when switching is to occur after the current error signal has crossed zero rising, i, -Tbr is the measured time the current error signal was below zero after a said 4 4, -11 switching instant (below zero and rising), Tb is the measured time the current error signal was below zero.

In an alternative form of the method where the next switching instant timing is being based on previous switching instant timing during a current error signal excursion in a half period ending one, three, five, or seven zero crossings before the most recent current error signal zero crossing, in the step of calculating said switching instances, a negative voltage is switched across said inductor approximately when T and a positive voltage is switched across said inductor approximately when T T where: Ta is the calculated time when switching is to occur after the current error signal has crossed zero rising, Tarp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising), Ta is the measured time the current error signal was above zero in a previous excursion, tsw 2 is the desired time between successive current error signal zero crossings (T 6 w is the desired switching period), Tb, is the calculated time when switching is to occur after the current error signal has crossed zero falling, 20 Tbfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), Tb is the measured time the current error signal was below zero in a previous excursion.

In either configuration it will be understood that the arrangements of the control circuit where the next switching instant timing is based on previous timings 1, 2, or 3 periods of the current error signal previous to the half period referred to f wA above, are less preferred as increasing the delay between measurement and i ontrol is believed to increase the switching frequency band.

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-12- Switching a positive voltage across the inductor causes a positive rate of change of current in the inductor, and conversely, switching a negative voltage across the inductor causes a negative rate of change of current in the inductor.

The invention will now be described in the following description of one specific embodiment thereof, in which: Figure 1 is a block diagram of a typical control loop using a current control method to regulate the current in an inner loop; Figure 2 is a typical example of a single phase ac-dc converter circuit used as a unity power factor rectifier, in which the current control method according to the invention can be utilised; Figure 3 is a graph showing the current error signal under ZACE control; Figure 4 is a graph showing the current error signal for the control circuit according to the embodiment; Figure 5 is a functional block diagram of a current control circuit according to the embodiment; Figure 6 is a graph showing the effect of a delay in implementing switching S° decisions in the current control circuit according to the embodiment; *nFigure 7 is a graph showing the simulated converter current, the reference current, and the current error signal; Figure 8 is a graph showing the harmonic spectrum of the simulated current; :o:Figure 9 is a graph showing the experimental current waveform; Figure 10 is a graph showing the average harmonic spectrum of the experimental current; 25 Figure 11 is a circuit schematic of a control circuit according to the embodiment; S- Figure 12 is a graph showing signal waveforms for the circuit of figure 11; Figure 13 is a circuit schematic of a single phase ac-dc converter; Figure 14 is a circuit schematic of a three phase ac-dc converter; SRA46, Figure 15 is a circuit schematic of a single phase boost rectifier, Figure 16 is a graph showing standing phases in a three phase ac-dc -13converter, and Figure 17 is a graph showing alternative standing phases in a three phase ac-dc converter.

The current control method according to the invention, hereafter referred to as ramptime current control, is a new technique for directly controlling the inductor current in switched power converters. It is a method producing zero average current error (ZACE) in each switching period and a controlled narrow switching frequency band. Ramptime current control was developed in an effort to find a ZACE method with a fixed switching frequency. The ZACE concept is illustrated in figure 3. Referring to figure 3, a current control with the ZACE characteristic will force the area of any one excursion of the current error signal (example: A-) to match the area of the previous excursion in the opposite direction. This will result in an average current error of zero for the period of the two excursions, which is one switching period. This control method uses the current error signal alone to determine switching instants, and maintains a narrow switching frequency band. This method is explained by reference to the current error signal in figure 4.

a: 0 Assuming the inductor has a fixed inductance, and there is negligible variance in both the power circuit voltages and the current reference signal within one 20 switching period, the current error signal will have two distinct, constant slopes over that switching cycle. If Ta is made equal to Tb, A+ will equal and the average value of the current error signal over that switching period will be zero.

,Hence, to maintain ZACE and a fixed switching frequency, the desired value of each half switching period is:

S:

T

(1) a ho 2 2 5 The key to Ramptime current control is that all switching decisions are timed i rom a recent and most preferably the most recent zero crossing of the current -14error signal. The controlled parameter is the current error signal. Each switching instant is chosen at the appropriate time after the last zero crossing of the current error signal so as to attempt to make the present excursion from zero last for exactly half the desired switching period. Referring to figure 4, Tar is chosen so that T, will equal and Tb is chosen so that Tb will equal T,/2.

The method of determination is simple geometry. To determine the desired Tb/, Ta and Ta, are each measured (indicated by during the previous current error signal excursion, and used in the formula in Tjr is determined in the same manner: (I (2) I- II--z r# A T (3) The implementation of ramptime current control is illustrated in the functional block diagram of processing means in the form of the control circuit shown in figure 5. The processing means receives input signal ES which is a binary signal indicating the polarity of the current error signal ER. The function of each of the blocks is as follows.

I AZT is an integrator to measure Ta, the duration of time when the current o o error signal ER is above zero.

INRT is an integrator to measure Taf, the duration of time when the current error signal ER is above zero and ramping downwards.

IAZR is an integrator for timing out Tbf, the duration of time after the current error signal ER has crossed zero moving downwards. At the end of the determined time Tbf, the power circuit is switched so that the current will ramp upwards.

.A IBZT is an integrator to measure Tb, the duration of time when the current error signal ER is below zero.

'PRT is an integrator to measure Tbr, the duration of time when the current error signal ER is below zero and ramping upwards.

IBZR is an integrator for timing out Tar, the duration of time after the current error signal ER has crossed zero moving upwards. At the end of the determined time Tar, the power circuit is switched so that the current will ramp downwards.

To implement ramptime current control, the power circuit is switched to supply a positive voltage across the inductor at the instant when equation 2 is satisfied, and is switched to supply a negative voltage across the inductor at the instant when equation 3 is satisfied.

The control circuit also comprises: means for deriving a current measurement signal i proportional to the magnitude and direction of the current in the inductor; 0 means for generating a reference current signal i* representing the magnitude and direction of the desired current or current waveform in the :inductor; means for generating a current error signal ER proportional to the difference between the current measurement signal and the reference current signal, where the maximum absolute value of the signal is limited to a certain value; means for measuring Ta, the duration of time when the current error signal ER is above zero (Functional block IAZ-); 25 0 means for measuring Taf, the duration of time when the current error signal ER is above zero and ramping downwards (Functional block INRT); means for determining Tbf, the duration of time after the current error signal ER has crossed zero moving downwards, at which time the binary output signal is set low, and the circuit is switched from the discharging configuration to the charging configuration which provides an output Q for the control of switching of the inductor (Functional block I'AZR and -16functional block QT); means for measuring Tb, the duration of time when the current error signal ER is below zero (Functional block IBz-); means for measuring Tbr, the duration of time when the current error signal ER is below zero and ramping upwards (Functional block IPRT); means for determining Tar, the duration of time after the current error signal ER has crossed zero moving upwards, at which time the binary output signal is set high, and the circuit is switched from the charging configuration to the discharging configuration (Functional block IBZR and also Functional block QT); means to switch the power circuit between appropriate configurations based on the value of the binary output signal.

Referring to figure 11 (divided into figures 11a, 1 lb, and 1 lc), the circuit diagram of an implementation of the current control circuit shown in figure 5, is illustrated.

The circuit comprises analog and digital circuitry, although it will be understood that portions of this control circuit could also be implemented using other circuitry including microprocessor based circuitry.

In describing the circuit in figure 11 each portion of the circuit is referenced to its respective functional block or signal in figure 5, where applicable.

The current measurement signal i, representing the magnitude and direction of the current in the inductor, is derived. The current measurement signal is readily :o°.°generated from a current measurement transducer having a bandwidth from dc :to above the switching frequency, with minimal phase shift. In the embodiment, the current measurement signal is generated using a commercially available hall 25 effect type transducer known as an LEM module (not shown) placed in close proximity to the inductor. Details of this are not shown in the circuit diagram. It will be understood that other techniques may be employed such as deriving the Scurrent measurement signal from the voltage developed across a low value ,7 jesistor connected in series with the inductor.

-17- The reference current signal representing the magnitude and direction of the desired current or current waveform in the inductor, is fed in from an external source. The reference current signal i* can be generated by whatever means is appropriate to achieve the power flow objectives of the converter. In the single phase ac-dc converter of the preferred embodiment, the reference current signal i* was sinusoidal at the fundamental frequency of the ac voltage. It was generated by a clocked output of a digital look-up table, followed by a low pass filter to remove the digital quantization steps. The clock frequency was a multiple of the frequency of a square wave synchronised with the fundamental component of the ac voltage using a phase locked loop.

A current error signal ER, proportional to the difference between the current measurement signal and the reference current signal is generated by subtracting the current measurement signal i from the reference current signal In three phase systems with a standing phase, the current error signal for the standing phase is subtracted from the current error signal for a controlled phase, giving a current error signal which is a difference current error signal, which can be used in the Ramptime control method. The current error signal is fed to the control circuit where indicated by ER in figure 1 la.

:0 o The following description of the circuit diagram of figures 1 la 11 b and 11 c will be better understood by following the timing waveforms in Figure 12. In this description /TR is held high, thereby eliminating its effect and the effect of the H S.o.

signal (see explanation later in relation to the H signal). The following table sets out the terminology used in figures 1 a 11 b and 11 c, and in the description:_

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TERM DESCRIPTION ER current error signal /ES (not ES) binary signal indicating the polarity of ER ES inverted /ES /ESD inverted ES .RAZ, ZT the output of integrator

I'AZT

the output of integrator IBZT -18- AZR the output of integrator IAZR /BZR the output of integrator IBZR NRT the output of integrator INRT /PRT the output of integrator IpRT /ZA control signal derived from /Q and /ES and used to zero /AZT Q output binary signal from functional block QT /Q inverted Q QD inverted /Q ZN control signal derived from Q (and H when required) to zero NRT /ZP control signal derived from Q (and H when required) to zero /PRT ZR output of variable gain opamp to set switching frequency (required to compensate for capacitor tolerances) ZB control signal derived from /Q and /ES to zero BZT /TR transient signal input (used to over-ride Ramptime and force hysteretic control if desired) H hysteretic control output Referring to figure 11a, the analog current error signal ER is fed into a comparator CA1 to generate binary signals ES /ES and /ESD indicating the polarity of the current error signal. As can be seen in figure 11a, both ES and /ESD are derived from /ES by schmidt trigger nand gates L1D and L1C *0 respectively, both in inverter configuration. ES and /ESD are fed into four integrators, which integrate for specific periods of time to give the output voltages indicated. Integrators A2A and A2B (shown in figure 11b) take their input from ES and integrators Al A and Al B (shown in figure 11 c) take their input from /ESD.

6* 9 10 Integrator A2A generates a voltage (/AZT) proportional to Ta, the duration of time when the current error signal is above zero within one switching period.

The output of integrator A2A begins ramping when the current error signal ER becomes positive, stops ramping when the current error signal ER becomes negative, and is zeroed by /ZA (output of Schmidt nand gate L2D) going low RA6T. when Q is switched low. Zener diode Z5 imposes a minimum value for /AZT for e eding to the circuitry which follows. Referring to figure 11c, Integrator A1B -19generates a voltage (NRT) proportional to Taf, the duration of time when the current error signal is above zero and ramping downwards. The output of integrator Al B begins ramping when Q is switched high, stops ramping when the current error signal ER becomes negative, and is zeroed by ZN going high when Q is switched low.

Integrator A2B (figure 11 b) generates a voltage (BZT) proportional to Tb, the duration of time when the current error signal ER is below zero. The output of integrator A2B begins ramping when the current error signal ER becomes negative, stops ramping when the current error signal ER becomes positive, and is zeroed by ZB going high when Q is switched high. Zener diode Z6 imposes a minimum value for BZT for feeding to the circuitry which follows.

Integrator A1A (figure 11 c) generates a voltage (PRT) proportional to Tbr, the duration of time when the current error signal ER is below zero and ramping upwards. The output of integrator A1A begins ramping when Q is switched low, 15 stops ramping when the current error signal ER becomes positive, and is zeroed t by /ZP going low when Q is switched high.

Integrator A2D (figure 11 b) generates a voltage ramp (AZR) proportional to the output of integrator A2A (/AZT) which is proportional to Ta. The output of integrator A2D begins ramping when ES becomes negative and is zeroed when 20 ES becomes positive.

0000 Integrator A2C generates a voltage ramp (BZR) proportional to the output of :ooo: integrator A2B (BZT) which is proportional to Tb. The output of integrator A2C oo begins ramping when ES becomes positive and is zeroed when ES becomes negative.

Op-amp A1D provides a variable gain to set the desired value of Tsw (the 4.A esired switching period) in equation and While this is normally required uto the large possible variance in actual circuit capacitor values, it could be omitted. The following discussion treats op-amp Al D as transparent, equivalent to a gain of 1. Referring to figure 11 c, the output binary signal Q is generated by comparator CA4 (part of functional block QT). One switching cycle is described here, beginning at a negative going transition of ES. The ramping voltage of integrator A2D (AZR) is compared to the held voltage of integrator A1 B (NRT).

When the two cross, the desired time period Tbf has elapsed, and Q is switched low. This results in the power circuit being switched from the negative voltage configuration to the positive voltage configuration, and ER should now begin ramping upwards. Integrator A1 B (NRT) is immediately zeroed and integrator A1A (PRT) begins ramping as described above. When the positive going transition of ES occurs, the output of integrator A1A (PRT) is held, and integrator A2C (BZR) begins ramping. When the two cross, the desired time period Tar has elapsed, and Q is switched high. This results in the power circuit being switched from the positive voltage configuration to the negative voltage configuration, and ER should now begin ramping downwards. The output of integrator A1 A (/PRT) is immediately zeroed and the output of integrator A 1B (NRT) begins ramping as described above. When the negative going transition of ES occurs, the output of integrator Al B (NRT) is held, and the control circuit has completed one full switching cycle.

The circuitry comprising components D33, D34, D35, D36, R33, R34, R35, and R36 is used solely to set minimum values of PRT and NRT. This ensures that the inputs to comparator CA4 can not both be zero, which would result in an indeterminate Q output. Components C13, D2, C15, 04, C20, D6, C23 and D8 are used only to ensure proper operation of their respective integrator zeroing 25 switches (MOSFETs T1, T2, T3, and Referring to figure 11 a, an addition to the basic ramptime circuitry is a hysteretic over-ride control circuit formed around comparator IC CA2 which can be implemented to impose a maximum current error signal excursion. This is useful Sin multi-phase converters with a standing phase system where the current error al presented to the controller is suddenly altered at each standing phase -21 transition, which would otherwise lead to transient current excursions of a short duration and low amplitude. This addition is not required for proper operation of the ramptime control, and in fact results in a temporary defeat of the ramptime control. The hysteretic over-ride is only intended to be used for a short time period, roughly equivalent to one switching period in duration. The hysteretic over-ride would not be required for single phase systems, and is not essential in three phase systems.

To effect the hysteretic over-ride, the current error signal is fed into comparator CA2 with a large amount of hysteresis. The output, a binary signal H, has transitions when the error signal passes the hysteresis level. If enabled by the "transient" signal TR, the negative going transition of H will result in the zeroing of PRT and the immediate, positive transition of Q, and the positive going transition of H will result in the zeroing of NRT and the immediate, negative transition of Q. Effectively, Q transitions will occur when the current error hysteresis level is reached.

Ramptime current control relies on an immediate implementation of switching decisions to achieve operation with zero average current error and fixed switching frequency. If the current reference is constant, and the implementation of switching decisions is immediate, ramptime current control would produce a fixed switching frequency. Since neither of these is the case in an actual converter, some variance in switching frequency occurs. Delays between the time the switching decision is made (including any pertinent delays in making the decision) and the actual turn on or turn off of the power switches will result in a minimal degradation in ZACE performance. This is illustrated in figure 6, where 25 the dotted line is the desired control response, and the solid line is the actual response with a 2 microsecond delay in implementation. It is apparent that the delayed switching results in an extended switching period, and hence a reduction in the actual switching frequency. More importantly, the different current slopes during the upper and lower switching instants result in an small 4\offset of the average current error from zero.

-22 The result of the above mentioned variances is asynchronous switching with a narrow switching frequency spectrum band. Any error in the upper switching instant (perhaps caused by noise) will not affect the ratio of Taf/Ta in figure 4 and hence the determination of Tbf will be unaffected. Once the zero crossing point has been reached, the control will continue operation oblivious to the disturbance, but with an apparently shifted clock. The overall result would be a solitary deviation of the average current error from zero for that switching period, and a deviation of that particular switching period from Tsw. Hence, ramptime control is stable and robust, being able to resume normal operation in the next half switching period after a disturbance. Under normal operation, each switching instant will be determined accurately, the average current error will be maintained very close to zero for each switching period, and the switching frequency will be contained in a narrow frequency band.

Ramptime current control, as applied to the single phase converter in figure 2, was simulated using the "Alternative Transient Program" (ATP), supplied by K.U.

Leuven EMTP Center (LEC), Belgium. With a line voltage of 240 volts, 50 Hz, and a dc link voltage of 400 volts, a reference current of 7.07 amps rms, was commanded. The target switching frequency was 5 kHz. Figure 7 shows the simulated converter current, the reference current, and the current error signal.

It is apparent that the current error is centered around zero, which is indicative of ZACE operation. The transient response is indicated at the start-up, where the current ramps up from zero to the crest value of 10 amps. The current harmonic spectrum up to the 120 harmonic (6 kHz) in figure 8 clearly shows no low order current harmonics, and a narrow switching frequency band.

25 A prototype, full-bridge insulated-gate-bipolar-transistor (IGBT) single phase ac- *OO° dc converter, as shown in figure 2, was built to test the ramptime current control method. In the control circuit developed for the prototype, the formulae for determining the switching instants were calculated in a circuit consisting of a mixture of analog and digital electronics, shown in figure 11. This was required /i I- since the time in which a calculation was required could be as short as a couple -23of microseconds. Since this current control method relies on measured ramp time durations in the previous half period to determine each switching instant, the initial switching instant may not be determined properly. Hence, on start-up a simple hysteresis control was used for the first 100 microseconds. It should be appreciated that other start-up methods, such as a fixed on-time could be utilised as an alternative.

The prototype converter operated at 216 VAc and 350 VDc., with a 3 kVA capability. The converter output current waveform with a sinusoidal input reference is shown in figure 9. The waviness observed in figure 9 is not apparent on an oscilloscope. It can be attributed to sampling aliasing, and is not due to current harmonics, as the spectrum in figure 10 testifies.

The converter current harmonic spectrum for low order harmonics (up to 1 kHz) is shown in figure 10. It is apparent that the largest harmonics, the third and fifth, are each roughly 55 dB below the fundamental, or roughly 0.2 of the fundamental. This can be attributed to delays in the implementation of switching decisions as discussed earlier, and a non-ideal current reference waveform.

Ramptime current control according to the invention has been shown to follow a sinusoidal reference with high fidelity. It is a "zero average current error" method with a narrow switching frequency. This method provides a higher bandwidth of 20 control with a narrow switching frequency band.

Ramptime current control can be used for accurate control of the current in any switched power converter with an inductor.

Ramptime current control can be applied to any uni-directional or bi-directional •ac to ac, ac to dc, or dc to dc single-phase or multi-phase power converter where it is desirable to control the current magnitude or current waveshape. The greatest expected use would be in unity power factor utility interfaces (grid A RAcJRA(- connected applications), in meeting real and reactive power requirements, and in -24active current harmonic filters.

One application of ramptime current control is the full bridge single phase ac-dc converter shown in Figure 13. Current reference waveforms which have been used include sinusoids at various phase relationships to the ac voltage. Two binary control output configurations are used. The first, equivalent to a standard diode bridge boost rectifier but with bidirectional capability, has S1 and S2 controlled by Q, with S1 on and S2 off when Q is high. S3 and S4 are switched according to the polarity of Vac; S3 is off and S4 is on when Vac is positive. The second configuration utilises the full bridge capability, with S1 and S4 on when Q is high, and S2 and S3 off when Q is high.

Another application of this current control is the full bridge three phase ac-dc converter shown in Figure 14. One method of controlling the current in this converter is to only switch two of the phases while the third phase is held as a standing phase. At any point in time, the standing phase is chosen as the phase whose voltage is alone in polarity (ie opposite in polarity to both of the other phases), as shown by the darkened portions 11 of the voltage waveforms shown in Figure 16. The choice of standing phase is not restricted to the phase whose S. voltage is alone in polarity, although this is the optimum choice for greatest controllability and transient response, and minimization of low order current harmonics. Alternatively, at any given instant in time, either of the two phases which are extremes in value can be chosen as the standing phase, as shown by the darkened portions 13 of the voltage waveforms in Figure 17. In other words, only the phase whose voltage is between the other two can not be chosen as a standing phase.

The configuration of the switches on the standing phase are set so that the midpoint of the switches is fixed to that same polarity side of the dc link as the polarity of the standing phase. For example, if the instantaneous voltage on phase a is negative while the instantaneous voltages on phase b and c are "is [ive, phase a would be the standing phase, and would be fixed to the negative side of the dc link. In this case, switch S2 would be held on and switch S1 held off. Each standing phase condition would be in effect for periods of roughly 60 degrees of the ac line cycle. The current in each of the inductors, and hence in the converter, is controlled by controlling the difference in current between each of the controlled phases and the standing phase. While a given inductor difference current is being controlled, the binary control output Q for that phase is used to control the status of the two complementary switches connected to that inductor, one switch being off while the other is on. In the above example, the current in Lb minus the current in La would be controlled to follow the difference in the respective reference currents using switches S3 and S4. Likewise the difference current between L, and La would be controlled to follow the respective reference current difference using switches S5 and S6.

Current reference waveforms which have been used include three phase sinusoids at various phase relationships to the ac voltage.

This current control could also be applied to the single phase boost rectifier shown in Figure 15. With a sinusoid in phase with Vac used as the current reference waveform, the boost rectifier would operate at a unity power factor.

o The binary control output would be used to turn S1 on during the charging period, and off during the discharging period.

The control circuit operates to provide a PWM binary output which can be used to control a switch or switches to control the current in an inductor in numerous other power conversion circuits. The important aspect is the method of control as applied to an inductor within the power circuit.

There are numerous other possible applications for this control circuit. While specific examples of applications are given here, they are not intended to limit the application for this control. It should be appreciated that the scope of the invention is not limited to the scope of the embodiment described herein.

Application of the ramptime current control method to switching regulator and y<4,ther applications will be readily apparent to a skilled addressee.

Claims

2. A control circuit as claimed in claim 1 wherein said timing calculation S ST ~means determines a next switching instant time relative to zero-crossing 62 of said current error signal, based on a previous time of a previous said
4- -27- switching instant relative to zero-crossing of said current error signal. 3. A control circuit as claimed in claim 1 wherein said timing calculation means determines a next switching instant time relative to zero-crossing of said current error signal, based on the time of a previous said switching instant, relative to the time between zero-crossing times of the current signal immediately before and after said previous said switching instant. 4. A control circuit as claimed in claim 3 wherein said timing calculation means determines the next switching instant timing based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1, 2, or 3 periods before the most recent current error signal zero crossing, and said timing calculation means operates to cause said output to switch a positive voltage across said inductor approximately when i ,and operates to cause said output to switch a negative voltage across said inductor approximately when where: Tb, is the calculated time when the switching is to occur after the current i: 20 error signal has crossed zero falling, Tat is the measured time the current error signal was above zero after a said switching instant (above zero and falling), Ta is the measured time the current error signal was above zero, T. is the desired time between successive current error signal zero 25 crossings (the desired switching period), o" Tar is the calculated time when the switching is to occur after the current error signal has crossed zero rising, Tb, is the measured time the current error signal was below zero after a ,O R44 said switching instant (below zero and rising), 28 Tb is the measured time the current error signal was below zero. A control circuit as claimed in claim 4 wherein said timing calculation means determines the next switching instant timing based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1 or 2 periods before the most recent current error signal zero crossing.
6. A control circuit as claimed in claim 4 wherein said timing calculation means determines the next switching instant timing based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending one period before the most recent current error signal zero crossing.
7. A control circuit as claimed in claim 4 wherein said timing calculation means determines the next switching instant timing based on previous switching instant timing during a current error signal excursion in a half 20 period ending at the most recent current error signal zero crossing. S8. A control circuit as claimed in claim 3 wherein said timing calculation means determines the next switching instant timing being based on 5 previous switching instant timing during a current error signal excursion in 25 a half period ending one, three, five, or seven zero crossings before the :o.•.most recent current error signal zero crossing, and said timing calculation means operates to cause said output to switch a negative voltage across said inductor approximately when T, and operates to T 2 cause said output to switch a positive voltage across said inductor -29- approximately when where: Tar is the calculated time when switching is to occur after the current error signal has crossed zero rising, Tarp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising), Ta is the measured time the current error signal was above zero in a previous excursion, Tw,, is the desired time between successive current error signal zero crossings (the desired switching period), Tbf is the calculated time when switching is to occur after the current error signal has crossed zero falling, Tbfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and Tb is the measured time the current error signal was below zero in a previous excursion.
9. A control circuit as claimed in claim 8 wherein said timing calculation means determines the next switching instant timing being based on previous switching instant timing during a current error signal excursion in a half period ending one, three, or five zero crossings before the most recent current error signal zero crossing. °go° S.10. A control circuit as claimed in claim 8 wherein said timing calculation 0o00 means determines the next switching instant timing being based on previous switching instant timing during a current error signal excursion in S.a half period ending one or three zero crossings before the most recent oo00 current error signal zero crossing.
11. A control circuit as claimed in claim 8 wherein said timing calculation \ST Fj means determines the next switching instant timing being based on previous switching instant timing during a current error signal excursion in t 30 a half period ending one zero crossing before the most recent current error signal zero crossing.
12. A control circuit as claimed in any one of the preceding claims wherein said first input is connected to a first circuit for deriving said current measurement signal proportional to the magnitude and direction of the current in the inductor.
13. A control circuit as claimed in any one of the preceding claims wherein said output provides a binary signal which is to be used to control the switching of an active controlling device.
14. A control circuit as claimed in claim 13 wherein said active controlling device comprises a semiconductor switch or switches. A method of controlling a switching regulator having at least one inductor, comprising deriving a current measurement signal proportional to the magnitude :and direction of current in said at least one inductor, or proportional to the difference in current in two of said at least one inductors; deriving a reference current signal representing the magnitude and direction of the desired current or current waveform in said at least one inductor, or representing the difference in the desired current or current waveform in two of said at least one inductors; 25 determining the difference between said current measurement signal and said reference current signal to generate a current error signal *o 0 representative of the difference; and calculating the timing of switching instances to control switching of said at least one inductor to achieve an average current error signal close to zero, based on timing of previous switching instances relative to zero ST crossing of the current error signal during a previous excursion. -31
16. A method as claimed in claim 15 where in the step of calculating said switching instances, a new time from zero-crossing of said current error signal to a said switching instant is calculated, based on a previous time of a previous said switching instant relative to zero-crossing of said current error signal.
17. A method as claimed in claim 15 where in the step of calculating said switching instances, a new time from zero-crossing of said current error signal to a said switching instant is calculated, based on a previous time of a previous said switching instant relative to the time between zero- crossing times of the current error signal immediately before and after said previous said switching instant.
18. A method as claimed in claim 17 where when a new switching instant is being determined based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1, 2, or 3 periods before the most recent current error signal zero crossing, in the *i step of calculating said switching instances, a positive voltage is switched to said inductor approximately when T and a negative voltage is switched to said inductor approximatewhen T= T where: Tb, is the calculated time when the switching is to occur after the current error signal has crossed zero falling, 25 Taf is the measured time the current error signal was above zero after a said switching instant (above zero and falling), C° Ta is the measured time the current error signal was above zero, TW is the desired time between successive current error signal zero crossings (the desired switching period), 4 Il 32 Tar is the calculated time when the switching is to occur after the current error signal has crossed zero rising, Tbr is the measured time the current error signal was below zero after a said switching instant (below zero and rising), Tb is the measured time the current error signal was below zero.
19. A method as claimed in claim 18 where when a new switching instant is being determined based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1 or 2 periods before the most recent current error signal zero crossing. A method as claimed in claim 18 where when a new switching instant is being determined based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing, or in a half period ending 1 period before the most recent current error signal zero crossing.
21. A method as claimed in claim 18 where when a new switching instant is being determined based on previous switching instant timing during a current error signal excursion in a half period ending at the most recent current error signal zero crossing.
22. A method as claimed in claim 17 where when the next switching instant *sea 25 timing is being based on previous switching instant timingduring a current error signal excursion in a half period ending one, three, five, or seven .zero crossings before the most recent current error signal zero crossing, in the step of calculating said switching instances, a negative voltage is switched across said inductor approximately when Tr, and T"T a positive voltage is switched across said inductor approximately when a 33 TlL where: -Tar,, is the calculated time when switching is to occur after the current error signal has crossed zero rising, Tarp is the measured time the current error signal was above zero before a said previous switching instant (above zero and rising), Ta is the measured time the current error signal was above zero in a previous excursion, Tw is the desired time between successive current error signal zero crossings (the desired switching period), Tbf is the calculated time when switching is to occur after the current error signal has crossed zero falling, Tbfp is the measured time the current error signal was below zero before a said previous switching instant (below zero and falling), and Tb is the measured time the current error signal was below zero in a previous excursion.
23. A method as claimed in claim 22 where when the next switching instant timing is being based on previous switching instant timing during a current error signal excursion in a half period ending one, three, or five zero crossings before the most recent current error signal zero crossing.
24. A method as claimed in claim 22 where when the next switching instant timing is being based on previous switching instant timing during a current *error signal excursion in a half period ending one, or three zero crossings 25 before the most recent current error signal zero crossing. 9
25. A method as claimed in claim 22 where when the next switching instant timing is being based on previous switching instant timing during a current error signal excursion in a half period ending one zero crossing before the most recent current error signal zero crossing. A -34-
26. A switching power supply incorporating a control circuit as claimed in any one of claims 1 to 14.
27. A control circuit for a switching power supply substantially as herein described in the description of the embodiment. 28 A method for controlling a switching power supply substantially as herein described in the description of the embodiment. Dated this NINTH day of MAY 2000. PowerSearch Ltd Lawrence J BORLE Curtin University of Technology Applicants Wray Associates Perth, Western Australia Patent Attorneys for the Applicant S s*e* see* s0 0 0* 0 0 0 OSSS