AU718822B2

AU718822B2 - Method and circuit configuration for power control with low switching surges for electrical loads

Info

Publication number: AU718822B2
Application number: AU78626/98A
Authority: AU
Inventors: Tobias Manfried Gerber
Original assignee: Leister Process Technologies
Current assignee: Leister Process Technologies
Priority date: 1997-10-30
Filing date: 1998-07-31
Publication date: 2000-04-20
Anticipated expiration: 2018-07-31
Also published as: EP0866392A1; CN1071514C; ATE171792T1; JPH11206017A; CN1218327A; CA2246776A1; AU7862698A; ES2127028T3; EP0866392B1; DK0866392T3; JP3041522B2; DE59700024D1

Abstract

The flicker free switching of electrical power to a system having two part loads is based upon generation of pulses (A,B,C) obtained from the half waves of the ac supply voltage. The switching system operates with a pulse width modulation such that load switching provides power consumptions of 8,18,33,60,93 and 100% in stages depending upon the pulse supply combinations.

Description

P/00/011 Regulation 3.2

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT

ORIGINAL

V Name of Applicant: Actual Inventor(s): Actual Inventor(s): TO BE COMPLETED BY APPLICANT -LHS L \TER 6 jO"O Tobias Manfried Gerber Address for Service: Invention Title: CALLINAN LAWRIE, 711 High Street, Kew, 3101, Victoria, Australia "METHOD AND CIRCUIT CONFIGURATION FOR POWER CONTROL WITH LOW SWITCHING SURGES FOR ELECTRICAL

LOADS"

The following statement is a full description of this invention, including the best method of performing it known to me:- 31/7/98LP9988.CS,

IA/

1A The present invention concerns a method and a circuit configuration for power control with low switching surges for electric loads that are divided electrically into at least two partial loads, whereby to achieve the required heating power they are distributed among the partial loads largely uniformly in a certain power range.

When electric loads on a power supply system, such as a public a.c. system, are varied, changes in line voltage occur due to the impedance of the supply lines. These voltage changes (also known as flicker) are perceived as problematical by people in certain frequency/voltage ranges and must therefore be kept within narrow limits (flicker level) according to IEC 1000-3-3 and IEC 1000-3-5 standards. If electric loads such as heating systems must be switched on and off frequently to achieve a good control characteristic, only limited load changes can be switched per unit of time. This is achieved by dividing the total load into individual, separate, partial loads which are not switched at the same time or by dividing the total load into power stages.

German Patent No. 3,601,555 C2 describes a controlling element for stepwise power switching of an electric flowtype heating element as a function of power demand, wherein for power control in a cycle comprising multiple system full waves, system half waves are more or less switched through to at least one heating element, and the same number of positive and negative half waves occur in the cycle. Therefore, several different control signal patterns which switch through corresponding system half wave patterns to an electric heating element as a function of the power demand are stored in an electronic memory, with each control signal of the respective pattern switching through a half wave or several successive system half waves to the electric heating element. Each system half-wave pattern is designed so that its short-term flicker level is 2 below the interference limit, and the system half-wave patterns are graduated with regard to electric power in that they comprise a different number of half waves switched through. For switching intermediate power stages in a cycle comprising multiple system half-wave patterns, system half-wave patterns of different loads are switched in succession. The object achieved according to the patent specification is that the required freedom from flicker in combination with sensitive control of heating power can be achieved by stipulating different system half wave patterns, each stored in direct-voltage-free control signal patterns, and by processing them in a fixed cycle.

.i German Patent No. 3,726,535 Al discloses a method of power control with low switching surges for electric loads, where the heating loads are divided electrically into at least two underloads, and the underloads of each load, optionally in at least three main power stages in a series connection, can be alternately switched to an a.c. system individually or in a parallel connection. Starting from one of the main power stages, it is switched to the next lower main power stage during at least one half wave in each cycle in a continuously repeating cycle of at least two a.c. half waves. The switching cycles used there each have a length of six half waves, which are switched according to power demand.

German Patent No. 10,504,470 Al describes an electric flowtype heating element, where the graduations in heating power are achieved in a known way by appropriate masking out of partial areas of the usually sinusoidal heating current. The heating current is switched in the zero crossings. With this electric flow-type heating element, the total heating current is divided among various heating elements, and the individual heating elements each have a different nominal heating power. By means of a control circuit, the respective heating power is switched to as many heating elements as possible. The heating power is graduated in 1/3 steps 1/3, 2/3 or 3/3) of the nominal heating power. The heating power or heating current is switched through to the heating elements during six system half waves, where a corresponding number of half waves, corresponding to the heating power, is switched as already described in UnexaminedGerman Patent No. 3,726,535 Al. Thus, at 1/3 power, the first and fourth half waves are switched, at 2/3 power the second, third and fourth and fifthhalf waves are switched, and at 3/3 power all the half waves are switched. To achieve the desired power, the individual heating stages which have a different nominal S power are switched in succession, paying attention to the fact that all three loads are allocated uniformly with a heating stage before the next higher heating stage is connected at a partial load.

o..

With these known load sharing [methods], only one load can be switched directly. The load is distributed by fixed, Spower-proportional connection of partial loads and regulation over a partial load. With a heating system, especially involving the heating of air, for example, for hot air welding systems, or other welding equipment and hot air equipment, this leads to different temperatures in the different load ranges, because the power output of the partial loads may differ by up to 100%. Great temperature and load differences lead to material stresses and premature aging of heating elements.

According to the state of the art, power stages can be achieved by controlling individual half, waves, where this pulse pattern control can be used only for loads up to approximately 2.5 kW on the basis of the standard for the flicker rate, If larger loads must be controlled, mostly complicated and expensive electric circuits are necessary.

As a rule, the pulse patterns are set randomly in succession according to the power demand, so the switching I- -4surge load to be expected in the system cannot be determined clearly.

Therefore, the object of the present invention is to propose a possibility for controlling loads that permits flicker-free switching within the given standard of a multitude of partial loads, where the partial loads are brought onto load uniformly at any power demand.

This object is achieved according to the present invention by a method of power control with low switching surges for electric loads which are divided electrically into at least two partial loads, whereby to achieve the required heating power, they are divided largely uniformly among partial loads in a prescribed power range, wherein: three separate pulse pattern sequences A, B and C are formed from three successive system half waves (pattern period), each corresponding to the respective system half wave, with rectification of *15 negative half waves; each pulse pattern sequence A, B and C switches at least one partial load over a predetermined period, with each pulse pattern A, B or C switching a maximum of one third of the rated power of a partial load according to the maximum number of pulses per predetermined period; and the respective partial load is switched by the number of pulses of the respective pulse pattern sequence A, B and/or C during this predetermined period by means of pulse width modulation of at least one pulse pattern *l sequence according to the total power demand over a selectable predetermined period.

25 With the method according to the present invention, three separate pulse pattern sequences A, B and C are formed from three successive system half waves which form a so-called pattern period, where said pulse pattern sequences correspond to the respective system half waves and their negative half waves are rectified. Each pulse pattern sequence A, B and C switches at least one partial load over a predetermined period, which is referred to as the PWM period, where each pulse pattern sequence A, B and C switches a 22/0200,td9988.spe4 -4a maximum of one third of the nominal power to a partial load, referred to below as the pulse pattern power, according to the maximum number of pulses per PWM period. Each partial load is thus switched by one or more pulse pattern sequences A, B and C according to the total power demand, so that at an output of 100% of the nominal power of the partial load, the partial load receives the maximum pulse pattern power of each pulse pattern sequence over the entire PWM period. Accordingly, the respective partial load receives one pulse pattern sequence at 1/3 of the nominal power and two pulse pattern sequences at 2/3 of nominal power. Furthermore, the respective partial load is switched over a preselectable PWM period by pulse width modulation a *i a. 22/02/00,td9988.spe,4 (PWM) of at least one pulse pattern sequence according to the total power demand, through the number of pulses of the respective pulse pattern sequence A, B and/or C during this PWM period. Through such pulse width modulation, which can be performed essentially like any pulse pattern sequence, the intermediate values between the above-mentioned 1/3, 2/3 and 3/3 stages can be set. Due to the division among the three pulse patterns, one third of the nominal power is switched to the respective partial load over a PWM period of one pulse pattern. In the actual switching operation of each pulse, however,' the full nominal power is always switched to the partial load. Switching is always done at 1/3 of double system frequency, whereas 1/3 of the half wave frequency is switched at one pulse pattern sequence.

The PWM period and the half-wave frequency are synchronized with the system frequency. It is also possible to subdivide a pattern period into multiples of three, but the basic principle is the same and can be reduced to three. On the whole, flicker and the temperature fluctuations of individual partial loads are reduced by the longer period fluctuations.

According to another embodiment of the invention, the number of switching stages of the partial loads can be adjusted through the number of pattern periods. Thus, the accuracy of the above-mentioned intermediate values which are produced by PWM can be influenced.

According to another especially preferred embodiment, pulse width modulation is performed with only. one pulse pattern sequence, for example, pulse pattern sequence A, where the pulse pattern sequence can be switched to any desired partial load. On exceeding the maximum pulse pattern power of this pulse pattern sequence A, B and/or C, the next free Translator's note: Translated without "die" jedoch immer die voile Nennleistung geschaltet" instead of "...wird die jedoch immer pulse pattern sequence, for example B or C, is switched with maximum pulse pattern power, and the number of pulses of pulse pattern sequence A is reduced according to the total power demand. This is accomplished such that the respective pulse pattern sequence receives the abovementioned maximum pulse pattern power (one third of the nominal power) of a partial load, and PWM is performed again with the reduced pulse pattern sequence A. This permits fine gradations in power and distribution to individual partial loads. To always distribute the power uniformly among the individual partial loads in setting the required power, according to another especially preferred embodiment, the next free pulse pattern sequence switched to another partial load is switched with maximum pulse pattern power to the partial load. The power to be switched is already distributed to various partial loads within one PWM period.

eeo* With regard to the simplest possible circuit design and lowest possible flicker rate, according to another embodiment the pulse pattern sequences and their connection to the partial loads are interchanged in cycles in order to set the required total power. This is accomplished such that first all the pulse pattern sequences A, B and C are allocated with maximum pulse pattern power before a pulse pattern sequence A, B or C is again allocated with connection of maximum pulse pattern power.

To further improve flicker rate, pulse-width-modulated pulse pattern sequence A is assigned to the next partial load, not yet pulse width modulated, in the following PWM period. Thus, the PWM in pulse pattern sequence A is routed from one partial load to the next partial load, and consequently each individual partial load in successive PWM periods receives at least part of the-required total power.

Consequently, there are no great power differences between the individual partial loads. In addition, this possibility permits a reduction in flicker rate and reliable compliance with the required flicker rate.

The latter is improved further in particular due to the fact that according to another embodiment, the PW-modulated pulse pattern sequence is assigned to the individual partial loads in succession with cyclic exchange, and at the same time the PW-modulated pulse pattern sequences of two successive PWM periods are arranged between the two PWM periods, symmetrical with the middle. This means that a PWmodulated pulse pattern sequence A at the beginning of a PWM period, for example, is arranged at the end of this pulse pattern sequence, mirrored in the next PWM period toward the middle between the two PWM periods. As already explained above, the pulse pattern sequence A in the first PWM -period has changed from one partial load to the next partial load in the next PWM period. This is always continued between two successive PWM periods, so that with even-numbered partial loads, a system period, after whose end the sequence of the load connection by the individual pulse pattern sequences begins again from the beginning, is derived from an even number of partial loads used, and with an odd number of partial loads, the system period is derived from double the number of partial loads. This prevents unwanted flicker in a special way, because no switching operation that would cause flicker for the line voltage is carried out when the PW-modulated pulse pattern sequence is switched from one partial load to the next. One partial load is merely switched off and at the same time the next partial load is switched on. Due to the cyclic exchange, the same process is also carried out with the pulse patterns receiving maximum pulse pattern power and the partial loads assigned to them in alternation.

The circuit configuration according to the present invention has a pattern generator for generating three separate rectified pulse pattern sequences B, C) from three successive system half waves and a controlling device per partial load to be controlled. At least one controlling device has at least one pulse width modulation generator (PWM generator) which generates a corresponding number of pulses of the respective pulse pattern sequence A, B and/or C over a predetermined period (PWM period) corresponding to the total power demand, and each controlling device has a corresponding number of comparators, where the total number of PWM generators and comparators is three per controlling device, and each PWM generator or comparator switches a maximum of one third of the nominal power to a partial load, and one of the pulse pattern sequences A, B or C can be switched with the maximum number of pulses per PWM period over each comparator in conjunction with the pattern generator over the duration of the PWM period. In addition, the circuit configuration has logic units for applying at least one pulse pattern sequence to the respective partial load according to the total power demand over a preselectable PWM period through the number of pulses of the respective pulse pattern sequence A, B and/or C during this PWM period, and it has a controlling element for activating the generators and comparators.

The invention thus makes it possible to control a plurality of single-phase and three-phase loads with low switching surges, where the current surge load of the system due to the connectable loads can be calculated accurately in advance. Through an appropriate choice of the individual switching stages and the pulses per unit of time, a loaddemand-compliant optimum for the given application case can be implemented reliably, taking into account the respective flicker standards. Power is divided uniformly among the partial loads, but it is no longer necessary to generate a new control method for each new power stage. The partial loads need not necessarily be equal, but equally large partial loads are helpful for the flicker rate. There is the option of a modular hookup. If another partial load is generated, it can be applied to the overall circuit system with only minor changes, without altering the principle of the method. The basic principle can also be applied to three-phase loads (in a star connection or a delta connection), where the particular features of the threephase system must be taken into account especially with delta-connected loads in a manner with which those skilled in the art are familiar to prevent any imbalance in the system. With multiple loads, star-connected loads behave like single-phase loads with regard to one phase. When using a circuit configuration oriented for two partial loads, this can be used for two single-phase loads or for three-phase loads for control with low switching surges.

This control is especially advantageous with (air) heaters, because all the partial loads are heated uniformly, and therefore the air temperature is not subject to great fluctuations from one partial load to the next. In addition, the windings are under low stress due to low .temperature differences due to the uniform control. At high powers, it is no longer necessary to make such high demands of the heating coil.

e• The present invention is explained in greater detail below n the basis of embodiments in combination with the accompanying drawings, which show: Figure 1: the pulse pattern division based on the system frequency; Figure 2: a pulse pattern for two loads with different power demands; Figure 3: a pulse pattern for three loads with different power demands and with a different number of pattern periods per PWM step in comparison with Figure 2; Figure 4: the distribution of the power demanded to comparator stages; the pulse duty factor for a PWM switching stage and for two PWM switching stages; Figure 5: a circuit configuration for two partial loads.

Figure 1 shows the pulse pattern division with an a.c. system W and pulse pattern sequences A, B, C assigned to the half waves of the a.c. system. The respective partial loads are controlled by means of these pulse pattern sequences A, B and C. Each pulse pattern sequence may be assigned to one or more partial loads to influence their switching operation. In the following embodiments, three system half waves and their assigned pulses of the individual pulse pattern sequences A, B, C form one pattern period.

Figure 2 shows the pulse pattern over essentially two PWM periods for five different load stages with 18%, 33%, 60% and 93% of the total nominal power of the two partial loads. In this embodiment, eight switching stages :0:00: were established per PWM period. At a maximum power of 33% 1/3) of the nominal power of a partial load, it follows from this that approximately 4% 20 of the nominal power can be switched per switching stage (33% 8 In addition, one pattern period 3 half waves) per PWM switching stage [is] selected. The number of available half waves within one PWM period is obtained from the following formula: number of switching stages x (number of pattern periods per switching stage x number of waves per pattern period).

In the embodiment according to Figure 2, this yields 24 half waves 8 x (1 x 3) within one PWM period. In this embodiment, each half wave is designated with the letters A, B or C for simplification. Since there are two loads, 22/02/0,td9988.spe, and thus there is an even number of loads, a total period consists of two PWM periods. After the total period, the process begins again from the beginning. For illustration purposes, the power increase obtained by connecting a pattern for the respective partial loads is given for each pattern period. The second pattern period is mirrored to the first pattern period, so that for the second pattern period accordingly, the switching stage values decrease toward the end of the second pattern period. The connection of the respective pulse of the pulse pattern A, B or C is represented by x's in this diagram.

In the embodiments, pulse pattern A is still pulse width modulated, while the other pulse patterns are either *switched on completely or switched off during the other S: pulse patterns over a PWM period. Due to the connection of Se: a pulse pattern, such as B, to a partial load over the entire length of the PWM period, the partial load receives 33% of the nominal power during this period of time.

To set a desired power demand, the required power must be distributed to the individual partial loads so that only one pulse pattern A, which is assigned to a partial load, is pulse width modulated, while all other pulse patterns S"are connected over the entire PWM period. On the example with a power demand of 18%, this yields the full connection of the second partial load by means of pulse pattern B during the first PWM period and the connection of the first partial load by means of pulse pattern A only during the first switching stage. This gives on the whole a power of 37%; distributed to two loads (average)i a total power of approximately 18% is calculated from this. After the first PWM period, the second partial load is allocated with pulse pattern A which is pulse width modulated, while the first partial load is allocated completely with pulse pattern B.

This cyclic exchange and mirroring at the middle between the two successive PWM periods serves to reduce flicker rate because it is impossible to detect on the system side that one partial load has been switched off and the other partial load is switched on instead, and it also serves to achieve a uniform distribution of power to the partial loads for the purpose of continuous heating. After the second PWM period, the system period is ended and the process begins again from the start. This principle is implemented in all the power demand examples illustrated.

At a power demand of only the first partial load receives the pulse pattern A in the first PWM period with pulse width modulation. The change to the second partial load then takes place in the second PWM period. The total power is 16% 2 8%.

At a power demand of 33%, pulse pattern sequence C is switched fully to the first partial load, and pulse pattern sequence B is switched to the second partial load in this embodiment. After the end of one PWM period, the assignment of partial loads to the pulse pattern sequences changes as shown in the figure.

At a power demand of 60%, the second partial load is completely allocated with pulse pattern sequence A and pulse pattern sequence B during the first PWM period, which yields a partial load allocation of 66%. The first partial load is completely allocated with pulse pattern sequence C, and PWM is performed at pulse pattern sequence A, yielding allocation of the first partial load. This gives a total of approximately 53% for the first partial load, so that this yields an approximate total load of 60% 66%) After the end of the first PWM period, the above-mentioned mirroring and reversal of connection are performed. Likewise with each additional PWM period.

Similarly, a total power of 93% is obtained from the pulse pattern sequences shown in Figure 2. The second partial load is then allocated 100% during the first PWM period, while the first partial load is allocated 66% by pulse pattern sequences B and C and 20% by PW-modulated pulse pattern sequence A. This yields approximately 93% for the total load (186% 2) Like Figure 2, Figure 3 shows a pulse pattern, but with three loads. In addition, in this embodiment, two pattern periods per switching. stage were selected. Furthermore, the switching stages' for pulse width modulation were also set at two, so this yields approximately 16% per switching stage (33% Consequently, one PWM period has 2 x (2 x 3) 12 half waves. In this embodiment, shown in Figure 3 for illustration purposes, three power demands of and 83% were selected. Just as before, pulse width modulation is performed only with pulse pattern sequence A, switching as described above from one partial load in the first PWM period to the second partial load in the next PWM period and then to the third partial load in the third PWM period. Here again, switching pulses of the pulse- pattern sequence of two successive PWM periods are symmetrical with the middle of two successive PWM periods in order to obtain switching values that are favorable for the flicker rate.

Owing to the odd number of loads, six PWM periods are Snecessary for a system period until the cycle begins again from the start. Owing to the selection of the number of pattern periods, a pulse pattern sequence with two pulses must be switched for the smallest power value. During the first PWM period, the other pulse pattern sequences B and C remain switched off, so that the pulse pattern sequence A occupies a power of approximately 16% on partial load i, while the other pulse pattern sequences occupy 0% on the two other partial loads. The average of this yields approximately The situation is similar with a power demand of 45%, where the first partial load is allocated with the complete pulse pattern sequence A in the first PWM period, in this case there is no PWM here. The second partial load is completely allocated with pulse pattern sequences A and B, and the third partial load is completely allocated with pulse pattern sequence C within one PWM period. This yields a 33% allocation of the first partial load, 67% of the second partial load and 33% of the third partial load, yielding a total value of approximately 44% for the three loads. After the first PWM period, there is again a cyclic exchange and mirroring with respect to the middle between two successive PWM periods, as explained repeatedly above.

However, due to the full allocation of the pulse pattern sequences, the mirroring is not manifested as clearly here as in the example with 5% power demand. In the second PWM W period, pulse pattern sequence A is switched to the second :I partial load, while pulse pattern sequence C, which was originally switched to the third partial load, is now switched to the first partial load. Accordingly, pulse pattern sequences A and B, which were originally switched to the second partial load, are now switched -to the third partial load. This cyclic exchange is continued from one PWM period to the next PWM period.

:..The power demand of 83% in Figure 3 is obtained accordingly, with an allocation of 66% in the first PWM period of the first partial load from pulse pattern sequences B and C and 16% for the PW-modulated pulse pattern sequence A, 100% for the second partial load and 66% for the third partial load from pulse pattern sequences A and C. This yields a total of 248% 16%) 100% which is approximately 83% when divided among three loads (248% In the subsequent periods, there is again a cyclic exchange of pulse pattern sequences among the partial loads. One system period is concluded after six PWM periods.

For implementation of the method according to the present invention, the demanded power is divided in comparator stages (comparators), and the individual comparators are always graduated in uniform power stages and remain active up to 100% power. The number of comparators depends on the division of the load, with the number of comparators obtained from the following equation: number of comparators 3 x (number of partial loads) i.

Figure 4a shows a diagram illustrating the division of the required power LA among five comparators which are necessary with two partial loads. It can be seen here that comparator I is connected at 17% and remains connected over the full power demand. The situation is similar for the other comparators II, III, IV and V.

Figure 4b shows the pulse duty factor T for a PWM switching stage, also with two loads, with regard to the power demand LA as an example. Synchronized with the system frequency, a PWM having the following properties is applied: I. The resolution and the smallest discrete step are 2/3 of the system frequency.

2. The fixed period length is an integral divisor of the [-system frequency by three.

3. The period is synchronized with the system frequency.

4. The PWM is linked to a pattern B or C).

5. Optionally either the even-numbered PWM periods are first connected and then disconnected and then in the odd-numbered PWM periods first the .off component and then the switching component are driven or vice versa.

Thus the pulse duty factors between the switching component and the off component are the same in the even-numbered and odd-numbered PWM periods, as already shown in Figures 2 and 3 and explained above.

6. The pulse duty factor (modulation) of the PWM depends on the number of partial loads to be controlled. If 16 multiple, separately driven power controllers are used, this yields a pulse duty factor, as shown in the figure with two loads, of: power demand 3 x number of power controllers.

Figure 4b shows that at a power demand of 17%, the pulse duty factor is 100%, at this power, a different pulse pattern sequence is completely switched to a partial load.

Figure 5 shows a block diagram of the design of a control circuit for two loads L1 and L2, which are operated as power controllers over bidirectional triode thyristors (not shown), for example. The system frequency of the a.c. system is picked off S and sent over a pulse former 1 with a double system frequency to a pattern generator 2 and with 2/3 the system frequency to a PWM generator 3.

Comparators K I to K V according to Figure 4a are parallel to PWM generator 3.

15 Thus, number 4 denotes comparator K II, which connects at 1/3 power, number denotes comparator K IV which connects at 2/3 power, number 6 denotes ocomparator K I which connects at 1/6 power, reference number 7 denotes comparator K III which connects at half power, and reference number 8 denotes comparator K V which connects at 5/6 power. The output of PWM generator 3 0 together with output A of pattern generator 2, which [generates] pulse pattern sequence A, is applied to an AND element 9. The output of comparator K Ill, ooeo which is designated with number 4, together with pattern sequence B delivered by pattern generator 2 at output B, is applied to AND element 10, and the output of comparator K IV, designated with reference number 5, together with pulse pattern sequence C delivered at output C of pattern generator 2, is applied to AND element 11. The outputs of the AND elements are linked to OR element 15 and sent in parallel to an AND element 18 or 20. The situation is similar with comparators K I, K III and K V, which are designated with reference numbers 6, 7 and 8, which are applied together with pulse pattern 2/10198GC9988.SPE,1 6 sequences C, A and B to AND elements 12, 13 and 14. The outputs of these AND elements 12, 13, 14 are sent to an OR element 16, and its output is applied in parallel to AND elements 19 and 21. To implement the cyclic exchange described above, a signal of PWM generator 3 which changes every second PWM period is applied to an inverter stage 17, and its output signal is applied to AND elements 19 and In addition, this signal delivered by PWM generator 3 is sent without inversion to AND elements 18 and 21. The outputs of AND elements 18 and 19 are linked via OR element 22, and the outputs of AND elements 20 and 21 are linked via OR element 23, and the respective outputs are sent to a corresponding load controller for the respective load. By means of controlling element 24, the power demand is sent to PWM generator 3 or comparators 4 through 8, which are activated accordingly.

As already explained in conjunction with Figures 2 and 3, PWM modulation is performed only with pulse pattern sequence A and is linked to AND element 9. Above a power demand of comparator K I with reference number 6 is activated, and pattern sequence C is switched through.

Until the next comparator is connected, pulse width modulation is again performed over PWM generator 3 together with pulse pattern sequence A. At a power demand of >33%, comparator K II, which is labeled with reference number 4, is activated, so that pulse pattern B is switched through.

For all subsequent intermediate ranges, PWM is performed with pulse pattern A, as explained above, and comparator K III, which is labeled with reference number 7 accordingly, is activated at a power demand ito switch through pulse pattern sequence A; comparator K IV, which is labeled with reference number 5, is activated at a power demand to switch through pulse pattern sequence C; and comparator K IV [sic; which is labeled with reference number 8, is activated at a power demand to switch through pulse pattern sequence B.

Figure 4c shows the power demand LA and output power AL of two different control paths I and II, indicated with dotted lines in Figure 5, where control path I is formed by comparators 6, 7 and 8, and control path II is formed by PWM generator 3 and comparators 4, 5. Figure 4c shows the division of the output power among the pulse patterns in accordance with the power demand.

It can be seen' from this embodiment that the following system is obtained in general in controlling loads: i. Exactly as many control paths must be established as there are loads to be controlled.

2. The first control path consists of two comparators and one PWM.

3. Each additional control path consists of three comparators.

4. Each comparator and PWM is assigned to one pulse pattern.

Each control path is assigned to one load for one PWM period. In the next PWM period, the control of the next partial load is switched further.

6. The PWM is linked to only one pulse pattern, namely A here.

7. A continuous pulse pattern is assigned to each additional control path control path II: pulse pattern B; control path III: pulse pattern C; control path IV: pulse pattern A; control path V: pulse pattern B; 8. After distribution of the pulse patterns to each control, operation is continued with the first control path. The goal is to allocate three pulse patterns A, B, C to each control path.

9. The comparators are graduated as described in conjunction with Figure 4a, and are distributed among the control paths in ascending order, like the pulse 19 patterns. The comparators are linked to the pulse patterns in such a way that one pulse pattern is always switched in the order A, B, C, A, B, C, A, with an increase in power demand.

By means of this invention, a plurality of loads can be switched in a power range of approximately 2 kW while maintaining the respective standard for flicker. The design of the electronic circuit is simpler, the smaller the number of switdhing stages provided in one PWM period available for PWM. In one embodiment, a PWM with 32 switching stages and one pulse pattern per switching stage is implemented. With two partial loads, this yields a PWM period of 96 half waves and a system period of 192 half waves.

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Claims

1. A method of power control with low switching surges for electric loads which are divided electrically into at least two partial loads, whereby to achieve the required heating power, they are divided largely uniformly among partial loads in a prescribed power range, wherein: three separate pulse pattern sequences A, B and C are formed from three successive system half waves (pattern period), each corresponding to the respective system half wave, with rectification of negative half waves; each pulse pattern sequence A, B and C switches at least one partial load over a predetermined period, with each pulse pattern A, B or C switching a maximum of one third of the rated power of a partial load according to the maximum number of pulses per predetermined period; and the respective partial load is switched by the number of pulses of the respective pulse pattern sequence A, B and/or C during this predetermined period by means of pulse width modulation of at S15 least one pulse pattern sequence according to the total power demand over a selectable predetermined period.

2. The method according to Claim 1, wherein the number of switching stages of the partial loads is set on the basis of the number of pattern periods within a predetermined period.

3. The method according to Claim 1 or Claim 2, wherein that pulse width modulation is performed with only one pulse pattern sequence (A) switching a partial load, and on exceeding the maximum pulse pattern power S of this pulse pattern sequence the next free pulse pattern sequence (B or C) is switched with the maximum pulse pattern power, and the number of 25 pulses of pulse pattern sequence A is reduced with pulse width modulation according to the total power demand.

4. The method according to Claim 3, wherein the next free pulse pattern sequence switched to another partial load is switched with the maximum pulse pattern power of the partial load.

5. The method according to Claim 4, wherein the pulse pattern sequences and their connection to the partial loads are interchanged in cycles RAito adjust the required total power in such a way that first all pulse pattern 22/02/00,td9988.spe,20 -21- sequences A, B and C are assigned to the maximum pulse pattern power before a pulse pattern sequence A, B or C is again assigned to connection of the maximum pulse pattern power.

6. The method according to any one of Claims 3 to 5, wherein in the subsequent pulse width modulation period, the pulse width-modulated pulse pattern sequence is assigned to the next partial load, which is not yet pulse width modulated.

7. The method according to Claim 6, wherein the pulse width- modulated pulse pattern sequence is assigned to the individual partial loads in succession with a cyclic exchange and, at the same time, pulse width- modulated pulse pattern sequences of two successive pulse width modulation periods are arranged between the two pulse width modulation periods and symmetrically with the center.

8. A circuit configuration for power control with low switching surges for electric loads which are divided electrically into at least two partial loads, with the latter being distributed largely uniformly among the partial loads in a prescribed power range to achieve the required heating power, said circuit configuration including: a pattern generator for generating three separate rectified pulse pattern sequences B, C) from three successive 20 system half waves; one control device per partial load to be controlled, a.o. wherein at least one control device has at least one pulse width modulation generator which generates a corresponding number of pulses of the respective l• pulse pattern sequence A, B and/or C in conjunction with the pattern generator over a predetermined period according to the total power demand, 25 and each control device has a corresponding number of comparators with the total number of pulse width modulation generators and comparators per control device being three, and each pulse width modulation generator or comparator switches a maximum of one third of the rated power of a partial load, and one of the pulse pattern sequences A, B or C can be switched with the maximum number of pulses per pulse width modulation period over each comparator in conjunction with the pattern generator for the duration of the A.1ulse width modulation period, logic elements for applying at least one pulse 22/02/00,td9988.spe,21 4 I -22- pattern sequence to the respective partial load according to the total power demand over a preselectable pulse width modulation period through the number of pulses of the respective pulse pattern sequence A, B and/or C during this pulse width modulation period, and a controlling element for activating the generators and comparators.

9. A method of power control, as claimed in claim 1, substantially as described herein with reference to the accompanying drawings. A circuit configuration for power control, as claimed in claim 8, substantially as described herein with reference to the accompanying drawings. DATED this 22nd day of February, 2000. LEISTER PROCESS TECHNOLOGIES By their Patent Attorneys: CALLINAN LAWRIE 0 t J~ 22/02/00,td9988.spe,22