AU7188191A - Circuit arrangement of a cellular processor - Google Patents

Circuit arrangement of a cellular processor

Info

Publication number
AU7188191A
AU7188191A AU71881/91A AU7188191A AU7188191A AU 7188191 A AU7188191 A AU 7188191A AU 71881/91 A AU71881/91 A AU 71881/91A AU 7188191 A AU7188191 A AU 7188191A AU 7188191 A AU7188191 A AU 7188191A
Authority
AU
Australia
Prior art keywords
circuit arrangement
cellular processor
cellular
processor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU71881/91A
Inventor
Tamas Legendi
Jozsef Toth
Antal Zsoter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CELLWARE KFT
Original Assignee
CELLWARE KFT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CELLWARE KFT filed Critical CELLWARE KFT
Publication of AU7188191A publication Critical patent/AU7188191A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
AU71881/91A 1990-02-01 1991-02-01 Circuit arrangement of a cellular processor Abandoned AU7188191A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HU90629A HU900629D0 (en) 1990-02-01 1990-02-01 Cicuit arrangement for inhomogen operating processors with homogen structure and cellular building
HU629/90 1990-02-01

Publications (1)

Publication Number Publication Date
AU7188191A true AU7188191A (en) 1991-08-21

Family

ID=10950535

Family Applications (1)

Application Number Title Priority Date Filing Date
AU71881/91A Abandoned AU7188191A (en) 1990-02-01 1991-02-01 Circuit arrangement of a cellular processor

Country Status (3)

Country Link
AU (1) AU7188191A (en)
HU (1) HU900629D0 (en)
WO (1) WO1991011770A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4308178C2 (en) * 1993-03-15 1995-09-07 Mir Patent Lizenzverwertungen Homogeneous computer structure
GB2370380B (en) * 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
GB2391083B (en) * 2002-07-19 2006-03-01 Picochip Designs Ltd Processor array
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835729A (en) * 1985-12-12 1989-05-30 Alcatel Usa, Corp. Single instruction multiple data (SIMD) cellular array processing apparatus with on-board RAM and address generator apparatus
JPS6364178A (en) * 1986-08-29 1988-03-22 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Image processing system
DE3629918A1 (en) * 1986-09-03 1988-03-10 Siedenburg Kurt Richard Dipl I Computer network
US4933895A (en) * 1987-07-10 1990-06-12 Hughes Aircraft Company Cellular array having data dependent processing capabilities
US5093781A (en) * 1988-10-07 1992-03-03 Hughes Aircraft Company Cellular network assignment processor using minimum/maximum convergence technique
US5001631A (en) * 1988-10-07 1991-03-19 Hughes Aircraft Company Cellular network assignment processor using randomly triggered adaptive cell thresholds

Also Published As

Publication number Publication date
HU900629D0 (en) 1990-04-28
WO1991011770A1 (en) 1991-08-08

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