AU699580B2 - Photonic switching matrix - Google Patents

Description

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ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention T itle: "PHOTONIC SWITCHING MATRIX" The following statement is a full description of this invention, including the best method of performing it known to us:- C0,2 7 0 4 3 0 j JUN195 *--74C i~T~i~tsu i i i, This invention relates to a photonic switching matrix designed to implement a multistage connection network, for point-to-point and point-to-multipoint connections.

It switches data in the form of cells of fixed length, which are multiplexed by means of asynchronous time division multiplexing.

Australian patent No. 640552 describes a photonic switching matrix including: several wavelength converters located respectively at the matrix inputs to allocate a wavelength to each cell applied to the matrix input.

an optical buffer memory common to all matrix outputs, to store each cell during a time which can be selected between 0 and k.T. where k is an integer o and T, is the duration of a cell, called cell period. This buffer memory including: 9 n optical diffusers, each with an input making up a buffer memory input, and with outputs.

"1E optical combiners, each with n inputs and one output.

(k+1 optical gates, each connecting the output of one of the diffusers to one of their combiners' inputs, and each providing for the selection of a delay value.

1) delay lines respectively providing delays from 0 to each *5 having an input respectively connected to a combiner output, and one output making up an output of the buffer memory.

a space routing stage including a filter associated with each matrix output, such that only cells of a given wavelength may be allowed to travel to a given output.

some control facilities to control wavelength converters and buffer memory delay selection gates as a function of routing information which indicates, for each cell, the matrix output to which this cell is assigned, and to select the storage time each cell is to be stored in the buffer memory.

Each storage time is selected such that a queue is formed for each output, to prevent conflict between two cells to be switched to the same output. In this known matrix, delay selection for each cell is carried out the moment this cell is applied to the matrix input, since the optical gates selecting this delay are located upstream of the 3 delay lines which will actually implement the delay selected. When, during the same cell period, several cells arrive at different inputs and are intended for the same matrix output, the control facilities select different delays such that cell transmission to the relevant outputs is spread over time. A queue is formed for each output, by allocating a unique delay to each cell intended for this output, this delay corresponding to the cell position in the queue. The control facilities allocate each cell with a delay value between 0 and k.T c Since each cell arriving on an input is likely to be intended for any of the n outputs, the control facilities must be aware of the storage capacity of the n output queues, before making a decision with regard to allocating a delay to this cell. To simplify optical gate addressing, the control facilities are centralised and manage the set of n output queues. The greater the number of inputs and outputs the more cumbersome the management.

The purpose of the present invention is to propose a photonic switching matrix :15 structure designed to ease the management of the n output queues in order to simplify the implementation of the matrix control facilities.

According to the invention there is provided a photonic switching matrix S including n inputs and n outputs, for switching data in the form of cells of fixed Sduration, referred to as the cell period, the cells being multiplexed by means of asynchronous time division multiplexing, said matrix including: n wavelength converters situated at respective ones of the inputs of the matrix, for allocating n distinct wavelengths to the cells applied to respective ones of the n inputs of the matrix; an optical buffer memory common to all of the outputs of the matrix, for storing each cell for a selectable duration selected from the range 0 to k.Tcj, where k is an integer and where TC is the cell period; a space routing stage including a tunable filter for each output of the matrix, so that only cells of a given wavelength are allowed to pass to a given output; control means for controlling the tunable filters as a function of routing information indicating the destination output of the matrix for each cell; AL and selection means for selecting the storage duration for which each cell is tored in the buffer memory, so as to constitute a queue for each output, thereby -i 4 avoiding conflict between a plurality of cells having the same destination output, wherein the common optical buffer memory includes: means for supplying k+l copies of each cell with k+l distinct delays; and means for then selecting a copy from the k+l delayed copies of each cell, for each destination output.

The switching matrix thus characterised may be fitted with some control facilities including n identical control devices, associated with the n matrix outputs, and selecting one wavelength and one delay per cell, independently for each matrix output.

This structure allows the implementation of modular control facilities, made up of n identical and independent modules managing only one output queue. Therefore, it has the advantage of providing for a much simpler implementation of the control facilities. Furthermore, it is fully compatible with the set-up of point-to-multipoint 4*6 connections.

According to a preferred method of implementation, each control device :15 associated with one output (S1 to S16) is fitted with: some means (RD, CE, CO, RS, MED, A) of detecting at the matrix inputs (El to El 6) each cell intended for this output, and determining the matrix input to which it has been applied and deducing therefrom a wavelength for this cell.

some means (PE, MSL, MSR) of storing the wavelength and delay allocated to each cell, and deducing therefrom the delay to be applied to the next cell intended for this output.

and some means (PL) of reading from the storage means (PE, MSL, MSR), the wavelength and delay allocated to a cell, for each cell period.

In order that the invention may be readily carried into effect, embodiments thereof will now be described in relation to the accompanying drawing, in which: Figure 1 is the synoptic diagram of an example of implementation of the matrix in accordance with the invention.

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Figure 2 is the synoptic diagram of a control device included in this example of implementation and corresponding to one output.

The example of implementation shown in figure 1 contains a single switching matrix, which may be a component of a stage within a connection network containing several switching matrices. In this example, the number of matrix inputs and outputs is equal to 16. The number of cells which can be stored in each queue is set by the number of delays which can be performed. The number k may be equal to 16 for instance. The article "Buffer Sizing in an ATM Switch for both ATM and STM Traffics" International Journal of Digital and Analog Cabled Systems vol 2, p 2 4 7 2 5 2 (1986) shows that an output buffer memory with a storage capacity of 16 cells per output, yields a cell loss rate equal to 1010. A given loss rate can be achieved by selecting another number k.

This example of implementation includes: 16 inputs El to El 6 16 outputs S1 to S16 16 passive couplers CP1 to CP1 6 having a port connected to one of the inputs El to El 6 respectively, and having two outputs.

16 wavelength converters WC1 to WC16, respectively transmitting over fixed .b20 and separate wavelengths Il1 to 116, each having an input connected to a first 6u~* output of one of the couplers CP1 to CP1 6 respectively.

an optical combiner C1 with 16 inputs respectively connected to an output of each of the wavelength converters WC1 to WC16.

a set FB of optical delay lines with one input connected to one output of combiner C1 and with k outputs supplying for each given cell applied at the input, k+ 1 copies of the same cell which are respectively delayed by O.To, 1 .T 2.T, where T, is the cell period.

16 delay selection modules MS1 to MS16 respectively associated with outputs S1 to S16, each being made up of 16 optical gates. Module MS1 for instance being made up of gates G1 to G16. Each module including k inputs respectively connected to k outputs of the delay line set FB, 16 control inputs respectively controlling the 16 optical gates, and one output common to the 16 optical gates.

I_ L 6 16 control devices DC1 to DC1 6 respectively associated with the 16 outputs S1 to S1 6 and operating independently from one another. Each device including 16 inputs connected to a bus B with 16 conductors respectively connected to the second outputs of couplers CP1 to CP1 6, and including 16 first outputs connected to the 16 control inputs of one of the delay selection modules MS1 to MS1 6, associated with the same matrix output.

16 filter modules TF1 to TF16 respectively associated with outputs S1 to S1 6, each module having one input respectively connected to the output of one of the selection modules MS1 to MS16, one output respectively connected to one of the matrix outputs S1 to S16, and 16 control inputs respec ively connected to 16 Buit second outputs of one of the control devices DC1 to DC1 6, associated with the same matrix output.

y 4 "All filter modules TF1 to TF1 6 are identical and are equivalent to a filter which can be tuned on 16 preset wavelengths. For instance, module TF1 includes: a spectral demultiplexer DM1 with an input making up the input of module FT1, and 16 outputs respectively restoring the cells carried over the wavelengths 11 to 116.

16 optical gates P1 to P16, each with one input respectively connected to 20q one of the 16 outputs of demultiplexer DM1, one control input making up one of the 16 control inputs of filter module TF1; and one output.

ls' an optical combiner C2 with 16 inputs respectively connected to the outputs Sof the 16 gates P1 to P16, and with one output making up the output of module TF1 which is connected to switching matrix output S1.

According to a preferred method of implementation, the delay line set FB is made up of optical fibre sections whose respective lengths provide propagation times equal to O.Tc, 4.Tr, or These optical fibre sections are connected so as to form a tree structure whereby the branches respectively lead to the k+1 outputs of set FB. Depending on the branch used, a cell may be subjected to all delay values O.T 1.Te, 3.Tc, 1).Te, in this instance I being an integer such that this last delay value is at least equal to k.T.

The 16 passive couplers CP1 to CP16 are used to sample on each input a -1 ~-T~pl I~I-L:_SSbJSa II 7 fraction of the optical signal energy such that each of the 16 control inputs DC1 to DCn may read the header of all cells applied to all switching matrix inputs El to El 6 in view of appropriately routing each cell to its intended destination output S1 to S16.

The same cell may be intended for several outputs when dealing with a point-tomultipoint connection.

The optical signals applied to inputs El to El 6 may be of any wavelength. The converters WC1 to WC16 allocate to each cell a wavelength II to 116 which is fixed and separate for each input El to El 6. Each filter module TF1 to TF1 6 is tuned to a wavelength selected among the wavelengths II to 116. Each module TF1 to TF1 6 is controlled by wavelength selection signals SL supplied by the second outputs of the control device DC1 to DC1 6 associated with this filter module. Hence a carrier with a wavelength Ij carries all cells applied to a given input Ej and is routed towards the 0 •o output(s) for which the filter module is tuned on wavelength Ij.

.o1s Delay line set FB systematically supplies k+ 1 delayed copies for each cell applied at its input. If this cell is intended for a single output, say S1 for instance, delay selection module MS1 is controlled by control module DC1 to select one copy out of the k delayed copies. Delay selection signals SR supplied by the first outputs of control device DC1 enable a single gate out of gates G1 to G1 6 and inhibit the other gates. In a point-to-multipoint connection, several outputs being the destination of the same cell, several delay selection modules operate in parallel and each selects a delayed copy.

Figure 2 represents the synoptic diagram of an example of the control device associated with one of the outputs, for instance device DC1 associated with output S1.

This device performs both routing of cells intended for output S1 and queue management to access this output S1 when several cells intended for this output arrive simultaneously on several inputs El to El 6. In this example of implementation DC1 includes: a set RD of sixteen 13-bit registers with 16 data inputs respectively connected to 16 parallel conductors on bus B, one 13-bit output, one read address input, i and one write control input receiving a clock signal H1. f- C~ 8 a 1 3-bit register RS designed to store the routing header and fitted with one input connected to the output of set RD, one 1 -bit output supplying an indicator BD indicating the type of connection, and one output supplying a 1 2bit word.

a memory MED storing specific routing labels called broadcasting labels, with one address input connected to the output of register RS supply'ng 12 bits, a read clock input receiving a clock signal H2, and a data output supplying a 5-bit word.

a router A including: two inputs, a first input being connected to the data output of memory MED and a second input being directly connected to 4 6«*044 bits of the 12-bit output of register RS; one control input connected to the 1-bit

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8 output of register RS; and one output.

a logic comparator CO having a first input connected to the output of router A, a second input receiving a 4-bit binary word AD(S1) which is the identity of output S1; and one output supplying a binary signal.

a wavelength selection memory MSL having: one data input, one write address input, one read address input, and one data output, the latter making up the 16 second outputs of control device CD1 which supply the 16 wavelength 20, selection signals SL.

a delay selection memory MSR having: one data input, one write Ilo" *address input, one read address input, and one data output, the latter making a a up the 16 first outputs of control device CD1 which supply the 16 delay selection signals SR.

a scanning counter CE with a clock input receiving a clock signal H3 and an output supplying a binary word EX to the address input of register set RD and to the data input of memory MSL.

a write pointer counter PE with a clock input connected to the output of comparator CO and an output connected to the data input and to the write address input of memory MSR and to write address input of memory MSL.

a read pointer counter PL with a clock input receiving a clock signal H4, and an output connected to the read address inputs of memories MSL and MSR.

aa a sequencer SQ supplying all clock signals Hi, H2, H3, H4 of control device DC1.

During each clock pulse, bus B supplies in serial form on each of its 1 6 conductors, a cell received by one of its 16 inputs El to El 6 respectively. Clock Hi controls the successive writing of 1 3 cell header bits in each register of the RD set.

Among these 13 bits, one bit BD indicating the type of connection is used to differentiate a point-to-point from a point-to-multipoint connection; the other 12 bits have different functions depending on the type of connection: either they cre made up of 3 fields of 4 bits making up 3 routing labels used in this example to select one output out of 16 in three successive stages of a connection network.

or they are made up of a single field of 12 bits designating one point-toj *multipoint connection out of a preset set of point-to-multipoint connections, each connection being in a tree structure connecting one matrix input to a certain number of matrix outputs.

Bit BD indicating the type of connection, controls router A to apply to I comparator CO: either the 4-bit word supplied by register RS output and representing the *2 identity of one of switching matrix outputs S1 to S1 6, when dealing with point-topoint connection.

or a series of several 5-bit words successively supplied by the data output of memory MED and representing the identities of outputs S1 to S16 to which the same cell is intended, when dealing with point-to-multipoint connection.

The number of binary words supplied by memory MED in response to a routing label representing a point-to-multipoint connection is at the most equal to 16 since the matrix considered contains only 16 outputs. Sequencer SQ supplies a series of 16 pulses of signal H2 to read 16 output identities successively. One of the 5 bits supplied by memory MED is used to designate the words which designate none of the i outputs, when the number of destination outputs is smaller than 16.

Comparator CO compares the output identity it receives on its first input with the identity AD(S1) of output S1, since in this example control device DC1 is associated with output S1. Each time comparator CO detects equality between the identities present on its first and second inputs, it supplies a logic signal to write pointer PE to increment its contents by one unit.

The value supplied via pointer PE output consists of both the delay value to be applied to a cell before it reaches output S1, and the write address where this delay value must be written in memory SR. Furthermore, this value consists of the write address where must be written in memory MSL, a binary word indicating the wavelength corresponding to the input from which this cell came. This binary word is supplied by scanning counter CE.

Scanning counter CE is a 4-bit binary counter. It supplies a binary word EX used for successively read addressing the 16 registers with the register set RD, during J each cell period. The word EX is also used to designate the matrix input which I received the cell whose header is stored in the register being read and belonging the RD set. Wavelength selection memory MSL is address by word EX, to supply a I word SL indicating the wavelength allocated to this input for this cell. It supplies a 16- S' bit binary word where only one bit has the value 1 and the other 15 bits have the value 0, in order to supply 16 wave selection signals which tune filter module TF1 to 0 .2 the wavelength corresponding to the input identified by binary word EX.

According to an alternate implementation, scanning counter CE may be replaced with a 4-bit pseudo-random number generator, to scan the 16 registers t within the RD set with an equiprobability without using a fixed sequence.

Figures 1 and 2 synoptic diagrams do not show any optical amplifier.

Nevertheless, optical amplifiers may be provided in several areas of the switching matrix to compensa+e optic signal attenuation, According to another alternate implementation, filter modules TF1 to TF6 may consist of optical filters which can be electrically and continuously tuned within the wavelength range I1 to 116.

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Claims (4)

1. A photonic switching matrix including n inputs and n outputs, for switching data in the form of cells of fixed duration, referred to as the cell period, the cells being multiplexed by means of asynchronous time division multiplexing, said matrix including: n wavelength converters situated at respective ones of the inputs of the matrix, for allocating n distinct wavelengths to the cells applied to respective ones of the n inputs of the matrix; an optical buffer memory common to all of 'ihe outputs of the matrix, for storing each cell for a selectable duration selected from the range 0 to k.Tcj, where k is an S integer and where TC is the cell period; a space routing stage including a tunable filter for each output of the matrix, so that only cells of a given wavelength are allowed to pass to a given output; S control means for controlling the tunable filters as a function of routing information 15 indicating the destination output of the matrix for each cell; and selection means for selecting the storage duration for which each cell is stored in the buffer memory, so as to constitute a queue for each output, thereby S avoiding conflict between a plurality of cells having the same destination output, wherein the common optical buffer memory includes: means for supplying k+l copies of each cell with k+l distinct delays; and means for then selecting a copy from the k+l delayed copies of each cell, for each destination output.

2. A matrix as claimed in claim 1, wherein the means for controlling the tunable filters and for selecting the storage duration include n identical control devices respectively associated with the n outputs of the matrix, and selecting a wavelength and a delay for each cell independently for each output of the matrix.

3. A switching matrix as claimed in claim 2, wherein each control device associated with an output includes: means for detecting each cell having that output as its destination output at the inputs of the mctrix; and for determining that input of the matrix to which the cell is applied and for deducing therefrom a wavelength for the cell; RA1 storage means for storing the wavelength and the delay allocated to each cell, I /9 E~narmrannn~~__ s and for deducing therefrom the delay to be applied to the next cell to have that output as its destination output; and means for reading, from the storage means, the wavelength and the delay allocated to a cell, for each cell period.

4. A photonic switching matrix, substantially as herein described with reference to Figures 1 2 of the accompanying drawings. 0 DATED THIS FIFTEENTH DAY OF OCTOBER 1998 ALCATEL N.V. 4 0 0 0t*#, 0* I -Pz L- ABSTRACT A photonic switching matrix including 16 wavelength converters (WC1 to WC16) located at the matrix inputs. an optical buffer memory common to all outputs to store each cell during a time which can be selected between 0, T, 2.T k.Tc where k is an integer and T. is the cell period. This buffer memory consisting of a set (FB) of delay lines supplying k+1 copies of the same cell, with k+ 1 separate delay values, and a set of 16 delay selection modules (MS1 to MS16). 16 control devices (DC1 to DC16) respectively associated with the 16 matrix outputs (S1 to S16) and operating independently from one another thanks to the S delay selection performed downstream of delay line set (FB). 16 filter modules (TF1 to TF 6) respectively associated with the 16 matrix outputs (S1 to S16), each module having one input respectively connected to one output of one of the selection modules (MS1 to MS1 6). *t Applicable to ATM telecommunications networks. V" 4 4