AU691369B2 - A method and device for call delay variation control for constant bit rate traffic - Google Patents

Description

S F Ref: 319780

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT

ORIGINAL

o e o o i o Name and Address of Applicant: NEC Corporation 7-1, Shiba Minato-ku Tokyo

JAPAN

Tatsuo Nakagawa Actual Inventor(s): Address for Service: Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia A Method and Device for Cell Delay Variation Control for Constant Bit Rate Traffic o Invention Title: The following statement is a full description of this invention, including the best method of performing it known to me/us:- 5845 pi A METHOD AND DEVICE FOR CELL DELAY VARIATION CONTROL FOR CONSTANT BIT RATE TRAFFIC BACKGROUND OF THE INVENTION i. Field of the Invention: The present invention relates to a control method and device for absorbing Cell Delay Variation (CDV) for Constant Bit Rate (CBR) traffic which is outputted to •toe the user's side in a User Network Interface (UNI) of an .:Asynchronous Transfer Mode (ATM) network.

10 2. Description of the Related Art: ooQ In an ATM network, when transmitting to the receiving side using cells of constant bit rate such as speech which are generated at a constant interval, Cell Delay Variation (CVD) may occur in which the constancy ee S 15 of cell interval is disrupted as a result of traversing the network. The causes for this phenomenon include: variation during conversion to cells; variation due to waiting to avoid collision with other cells within the network; and variation due to trasmitting FIFO memory.

No problem is caused when the cells arrive at constant intervals on the receiving side, but the above-described distortion of intervals causes both early and late arrival when returning the received cells to voice and prevents voice playback.

C I IC 2 One countermeasure in the prior art involves using a buffer for absorbing CDV when receiving ATM cells at a user's terminal, storing for a set time interval, and adding an additional delay to absorb CDV while maintaining CBR quality.

Japanese Patent Laid-open No. 130133/93 proposes a method for communicating a traffic parameter when connecting from a private network to an ATM network.

According to this method, delay variation characteris- 10 tics (the degree of variation) in multiplexing or .switching of a cell stream belonging to a Virtual ooeo e Channel (VC) or Virtual Path (VP) generated from the ooee sender's terminal side in the ATM network is predetermined on the sender's terminal side of the ATM network, and taking this effect into account, a source traffic parameter is communicated from the sender's terminal e o S" and exchanged. On the ATM network of the next stage, control of band assignment to a VC or VP or stream monitoring control is executed based on the parameter communicated and exchanged from the sender's terminal side of the ATM network. As a result, cell stream control that includes delay variation and cell transmission quality can be guaranteed on the next-stage ATM network without need for directly considering the effect of delay variation within the ATM network on the sender's terminal side.

3 Japanese Patent Laid-open No. 235448/91 discloses a method for maintaining quality of both CBR and Variable Bit Rate (VBR) by controlling VBR traffic according to the presence or absence of CBR traffic. This method employs a plurality of first storage means for storing inputted CBR cells, second storage means for storing inputted VBR cells, a bus in which cells outputted by the first and second storage means are multiplexed and transmitted, a concurrence means for deciding the order eo 10 of priority of cell output from the plurality of first storage means, and control means for controlling the first and second storage means such that preference is o e oo given to cells in the first and second storage means and outputted to the bus; the control-means giving preference to cells of the first storage means when it :detects that cells are stored in both the plurality of o first and second storage means, and the cells stored in the first storage means being outputted to the bus after adjustment of mutual order of preference by the concurrence means.

These methods of the prior art either do not control CDV with respect to the terminal, or, if CDV with respect to the terminal i5 controlled, require that a terminal have buffers for use in absorbing CDV.

The above-described prior art further necessitates the provision of memory for, for example, FIFO memory 4 at the user's terminal, and further, require cell storage and the conferring of additional delay. This control of additional delay complicates terminal control and results in costly terminals.

SUMMARY OF THE INVENTION In view of the drawbacks of the above-described prior art, the object of the present invention is to absorb CDV caused when a CBR traverses an ATM network without providing buffers for absorbing CDV at the 1 0 receiving terminal.

The present invention is a CDV control system for oe CBR traffic characterized in having shaping means for storing CBR cells for shaping CBR traffic at the output section of an ATM switch; cell storage time monitor 15 means for monitoring the time elapsed from the start of as storage in the shaping means up to a fixed time interval and outputting a start output instruction which communicates that a fixed time has elapsed; and shaping control means for receiving the start output instruction and executing CBR traffic shaping.

In addition, the present invention is a CDV control method for CBR traffic characterized in that, when executing CBR traffic shaping at the output section of an ATM switch, an input CBR cell stream is sequentially stored and CBR traffic shaping is executed based on exceeding a set time interval beginning from the start of storage.

According to one aspect of the present invention there is provided a Cell Delay Variation (CDV) control system for Constant Bit Rate (CBR) traffic comprising: shaping memory means for sequentially storing CBR cells of an input CBR traffic stream and shaping CBR traffic at an output section of an ATM switch; cell storage time monitor means for monitoring the elapsed time from the start of storage of each of said CBR cells in said shaping memory means, said monitor means providing a start output instruction which communicates that a fixed time corresponding to the maximum permissible CDV of a receiving terminal has elapsed; and shaping control means for executing CBR traffic shaping by sequentially outputting said CBR cells from said shaping memory means at uniform intervals in the same order in which said cells were stored in said shaping memory means upon receiving said start output instruction from said monitor means.

According to a further aspect of the present invention there is provided a Cell Delay Variation (CDV) control method of constant bit rate (CBR) traffic when executing CBR traffic shaping at an output section of an ATM switch, comprising the steps of: sequentially storing CBR cells from an input CBR traffic stream in a first-infirst-out FIFO memory; e •monitoring the elapsed time from the start of storage of each of said CBR cells in said FIFO memory; *performing CBR traffic shaping by sequentially outputting said CBR cells at uniform intervals from said FIFO memory when said elapsed time exceeds a set time S0" interval corresponding to the maximum permissible CDV of a receiving terminal.

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The above and other objects and features of the present invention will become more apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the construction of an embodiment of the present invention; Fig. 2 shows the configuration of an ATM network [nA\libppJOO868:JJP 6 in which the embodiment of the present invention is applied; and Fig. 3 illustrates the operation of the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained hereinbelow with reference to the accompanying figures.

*Goo Fig. 1 is a block diagram showing the construction e. *o of an embodiment of the present invention. Here, refer- 10 ence numeral 5 indicates the output of an ATM switch m o (ATM switching system), an input CBR cell stream in which CDV is distorted by traversing a network.

Reference numeral 1 indicates a shaping FIFO memory for traffic shaping provided for absorbing burst character- 15 istics of the input CBR cell stream 5 generated by the

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ATM switch, and reference numeral 2 indicates a shaping control circuit for controlling cell output from the shaping FIFO memory 1 to the terminal's permissible rate. Reference numeral 3 indicates a storage time monitoring circuit which monitors the time elapsed from the start of storage by the shaping FIFO memory 1 and outputs a start output instruction 4 to the shaping control circuit 2 when the elapsed time exceeds a fixed value. Regarding this fixed value, because the maximum value of cell delay variation generated by the ATM 7 network is guaranteed, this variation time is used as the additional delay in monitoring elapsed time. Reference numeral 6 indicates the output CBR cell stream wherein the magnitude of the burst characteristics and the distortion of CDV contained in the input CBR cell stream 5 has been controlled to within the permissible range of the terminal. The operation of the present embodiment based on the above construction will next be explained.

9*° Fig. 3 illustrates the operation of the present embodiment. A CBR call begins from the terminal to the ATM network side, and upon the start of input of the input CBR cell stream 5 shown in Fig. the input CBR cell stream 5 is sequentially stored within shaping FIFO memory i, but a start output instruction 4 is not outputted from the storage time monitor circuit 3 until the time interval of cell storage exceeds a fixed time (in this case, The shaping control circuit 2 thereeee• fore does not operate and the output CBR cell stream 6 is not outputted, only the additional delay being performed on the input CBR cell stream 5 at the FIFO memory 1 as shown in Fig. When the time elapsed from the beginning of storage in the shaping FIFO memory 1 exceeds a fixed time, the storage time monitor circuit 3 outputs a start output instruction 4, and the shaping control circuit 2 instructs the shaping FIFO 8 memory 1 to start cell output as shown in Fig. 3(c).

However, when the storage time exceeds the fixed time and a start output instruction 4 is outputted from the storage time monitor circuit 3, the start output istruction is not canceled. Because the delay variation time guaranteed by the ATM network is stored, the shaping FIFO memory 1 is not emptied. By this operation, the CDV distortion of a subsequently inputted oooo input CBR cell stream 5 is absorbed by the additional 6o** 1 0 delay due to the depth of the shaping FIFO memory 1 and the amount of cells stored in the shaping FIFO memory 1i, and the CDV distortion is smoothed by the shaping control circuit 2 and continuously outputted at a uniform interval as the output CBR cell stream 6.

Next will be explained the determination of the parameters for executing shaping by the shaping control circuit 2 and cell storage in uniform amounts in the shaping FIFO memory 1 when the storage time monitor a circuit 3 outputs the start output instruction 4.

Fig. 2 is a block diagram showing the configuration of an ATM network in which the embodiment of the present invention is applied. In this figure, reference numeral 21 indicates an input ATM cell stream from the terminal. Simultaneously with the start of a CBR call, as control information, the ATM network is notified of the maximum permissible rate and permissible CDV on the -9terminal side. Reference numeral 22 indicates an input interface which carries out processing of header exchange as well as the maximum permissible rate and permissible CDV for ATM cell switching. Reference numeral 27 indicates the processing result, i.e., information such as the maximum permissible rate and permissible CDV, which is communicated to the output interface 25. As the output interface, reference numeroooe al 25 includes the construction of the embodiment shown 'ae 1 0 in Fig. 1 having operation as explained in the embodiment, the maximum permissible rate sent from the input °je.

interface 22 being communicated to the shaping control circuit 2 and used as a shaping parameter, and similarly, the permissible CDV being communicated to the 15 storage time monitor circuit 3 and used as the monitor i time for outputting the start output instruction 4.

a Reference numeral 23 indicates an ATM switch that carries out switching of ATM cell streams from other ATM switches as well as ATM cell streams from other terminals. Consequently, an ATM cell stream 24 having burst characteristics and CDV distortion (including input CBR cell stream 5) is outputted. Reference numeral 26 indicates an output ATM cell stream (including output CBR cell stream 6) in which burst characteristics and CDV distortion have been absorbed to within permissible terminal limits by the output interface 10 Thus, according to the present invention, because the ATM network side has the traffic characteristics communicated by the terminal, the terminal need not include surplus buffer memory for absorbing burst characteristics or CDV.

Furthermore, according to vhe present invention, CDV in CBR traffic can be absorbed using the FIFO memory for traffic shaping inherent to an ATM switch, and the terminal does not require a buffer memory for f 10 this purpose.

It is to be understood, however, that although the characteristics and advantages of the present invention have been set forth in the foregoing description, the disclosure is illustrative only, and changes may be 15 made in the arrangement of the parts within the scope of the appended claims.

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Claims (4)

1. a Cell Delay Variation (CDV) control system for Constant Bit Rate (CBR) traffic comprising: shaping memory means for sequentially storing CBR cells of an input CBR traffic stream and shaping CBR traffic at an output section of an ATM switch; cell storage time monitor means for monitoring the elapsed time from the start of storage of each of said CBR cells in said shaping memory means, said monitor means providing a start output instruction which communicates that a fixed time corresponding to the maximum permissible CDV of a receiving terminal has elapsed; and shaping control means for executing CBR traffic shaping by sequentially outputting said CBR cells from said shaping memory means at uniform intervals in the same order in which said cells were stored in said shaping memory means upon receiving said start output instruction from said monitor means. 15

2. A Cell Delay Variation control system as recited in claim 2, wherein said shaping memory means comprises a first-in-first-out memory.

3. A Cell delay variation (CDV) control method of constant bit rate (CBR) traffic when executing CBR traffic shaping at an output section of an ATM switch, comprising the steps of: sequentially storing CBR cells from an input CBR traffic stream in a first-in- first-out FIFO memory; monitoring the elapsed time from the start of storage of each of said CBR cells in said FIFO memory; performing CBR traffic shaping by sequentially outputting said CBR cells at uniform intervals from said FIFO memory when said elapsed time exceeds a set time interval corresponding to the maximum permissible CDV of a receiving terminal.

4. A Cell Delay Variation (CDV) control system for Constant Bit Rate (CBR) traffic substantially as herein described with reference to figs. 1 to 3. DATED this Twenty-sixth Day of March 1998 NEC Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON In:\libppl00868:JJP A Method and Device for Cell Dela" riation Control for Constant Bit Rate .L affic ABSTRACT A system and method composed of a shaping FIFO memory is disclosed, that stores input CBR cells for shaping CBR traffic at the output section of an ATM switch. A storage time monitor circuit monitors the elapsed time from the start of storage in the shaping FIFO memory up to a fixed time interval and outputs a start output instruction when the elapsed time exceeds the fixed time interval. A shaping control circuit receives the start output instruction and executes CBR traffic shaping. *o a maa4538W