AU679973B2 - Synchronous digital exchange arrangement - Google Patents

Description

:I 1 i i t t 1 P/00/011 28/5/91 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT o* "SYNCHRONOUS DIGITAL EXCHANGE ARRANGEMENT" o a The following statement is a full description of "thisi nvention, including the best method of performing it known to us:- LI 'Ii 2 This invention relates to a method and circuits necessary for the realization and programming of the connection function in a synchronous equipment.

In recent years the international scenario for telecommunications has radically been changed by the introduction of the Synchronous Digital Hierarchy

(SDH).

As specified in CCITT recommendations G.781, G.782, G.783, in the equipment of such hierarchy, such as ADM (Add Drop Multiplexer) or DXC (Digital Cross Connect), two processing functions are contemplated, called HPC (Higher order Path Connection) and LPC (Lower order Path Connection), respectively. Such functions must perform a flexible reassign of the higher and lower order virtual containers, respectively. In this way the exchange operations between tributaries can be distributed over the entire network and not localised in big switching exchanges. In this new situation, it is necessary to have matrices with a complexity higher than the previous plesiochronous multiplexers; these devices are further requested a low transit time and a high reconfiguration speed.

oo" In the following, reference will be made to a connection matrix, rearrangeably not latching between 16 input STM-1 (Synchronous Transport o° Module level 1) frames and 8 output STM-1 frames with an exchange capacity So- up to 1,008 synchronous tributaries at 2,048 Mb/s at the input and 504 at the output (VC12 Virtual Container 12), realized on a sole device (the ASIC called MATISSE "MATISSE" is a trademark of the Applicant) developed in accord to the architecture and with the circuits of the present invention. ASIC 0 MATISSETM is the basic block for the 16 x 16 matrix used, in an ADM system, at STM4 level (622 Mb/s).

The processed frames are described in CCITT recommendations G.707, G.708 and G,709 relative to European SDH; the device operates upon them the HPC and LPC functions described in the CCITT recommendations G. 781, G.782 and G.783, A characteristic feature of the method lies in that both the input frames and the output frames are synchronized each other.

The most direct architecture for realizing such a matrix consists in L 3 utilising a large dimension memory (RAM) element characterized by sixteen write gates and 8 read gates, independent each from another. Such an approach is equivalent, in classic theory, to a unique connection stage capable of exchanging all tributaries contained in the input frames to generate the eight output frame. This is a strictly not-latching structure, which, however, has great drawbacks since RAMs of the type described above are not immediately available. It is thus necessary to "customise" the storage element; it follows that its flexibility and reusability are necessarily limited because of long development times and high costs.

It is an object of the present invention to provide a system which is not subject to the same drawbacks of the aforementioned prior art systems and nevertheless is particularly simple, effective and reliable.

Another object of the invention is to provide a system having a structure that is compact, easy to realize, inexpensive to manufacture and that features high performances.

The use of a memory so dimensioned as to retain exclusively the data interested in the exchange permits a connection matrix of this type to be S remarkably compacted and made realizable.

According to the invention, there is provided a circuit arrangement for the 0. 00 realization of a connection matrix amongst tributaries, of the type comprising a V. 0.

S first space stage, a second time stage, and a third space stage wherein said second time stage includes a data storage so dimensioned as to store exclusively data concerned with the exchange.

:Y According to a further aspect of the invention there is provided, a method of realizing a connection matrix among tributaries, comprising the steps of S- individuating data concerned with exchange; rotating data concerned with exchange; sequentially storing data in a buffer; transferring data concerrned with exchange from said buffer to said data storage; and routing data concerned with exchange towards the output.

In the proposed architecture a multistage connection type has been contemplated, in which the main modular element consists in a space-timespace matrix.

L The first space stage has the function of adapting the incoming data stream to obtain a sequential fill of an elastic memory, forming the next time stage. A characteristic feature of this stage is the extraction from the possible inputs of all, and only, data necessary for the reconstruction of the output frames, thus limiting the capacity of exchange requested to the second stage.

The second stage has the function of exchanging the time position of the tributaries sequentially introduced in any way into the output frame. It is comprised of a sequential write and programmable read out memory.

The third stage, if necessary, individuates data to be forwarded towards several outputs when the second stage has an output capacity greater than one frame.

The present invention therefore provides a connection architecture which is simple, modular, rearrangeably not latching both for point-to-point and for point-to-multipoint connections, and introduces the circuits for its setting up. A preferred, but not exclusive, application of the invention can be found in devices (preferably gate arrays) capable of realizing the HPC and LPC functions, without distinction. In this manner a considerable increase in integration is allowed ~likewise decreasing the power used, the room taken up, the equipment manufacturing cost, while increasing the reliability thereof.

The present invention further provides a method of reconfiguring fastly and easily such devices without introducing interrupts on unexchanged data, A detailed description of an embodiment of the invention is made hereinafter with reference to the attached drawings wherein: Figure 1 is a block diagram of the cross connection architecture for the realization of a 16 x 8 matrix in accordance with the present invention; Figure 2 illustrates the nominal format of the frames processed in the realization mentioned above (Figure 1); S Figures 3 and 4 are detailed block diagrams of the circuitry forming the architecture of Figure 1; and Figures 5 and 6 are detailed block diagrams of the devices that, in accordance with the present invention, translate and make it i

A

c I available the cross-connection information provided by the microprocessor in the form processed by the circuitry of Figures 3 and 4.

In all figures it is emphasized the path of data stream (DT-IN and DT- OUT) and of the cross-connection prearrangement (PD-WRITE and PD-READ).

In such a realization the dimensions of the first space stage are exclusively bound to the number of inputs For the time stage, standard RAMs available in LSI100K technology and characterized by the presence of a sole write port and two independent read ports, have been used; by using these RAMs at a frequency of 38.88 MHz, the actual read ports become four. The connection matrix is thus organized in a set of 16 x 4 independent modules; the use technology allows the implementation of only two modules in a sole device thus realizing the 16 x 8 matrix illustrated in Figure 1.

Each basic 16 x 4 module is characterized by: a) a functional block, labelled WRITE, whose circuits extract and write into an elastic memory the data to be exchanged by exchanging the connection information contained into a write control memory WCM; b) am elastic memory DATA-RAM, suitably dimensioned (a memory of thirty seven, 16-byte words in the realization described herein), characterized by a write port and two independent read ports on which the tributary 0.

S flows to be cross-connected are retained; o oJl 04 c) a functional block, labelled READ, whose circuits insert the bytes contained in the elastic READ, whose circuits insert the bytes contained in the elastic memory, into the four outcoming frames in the order and e-0, position specified by a read control memory RCM.

Moreover, the blocks common to the two basic modules are highlighted in Figure 1: d) a timing unit, labelled MASTER COUNTER, that scans the operation of othe entire device; e) an input interface, labelled SAMPLE, whose circuits realize the nibble/byte conversion of the input flows; f) an interface MPIF to microprocessor, characterized by the presence of 6 memories WSPM and RSPM.

The frames processed by the above-mentioned device are illustrated in Figure 2; they are organized in nine 5-sector rows; a first sector, having width of 18 time slots, is significant when higher path tributaries are transported; the other four sectors, having 63 time slots each, accurately repeat the same sequence of tributaries which can be higher or lower patch tributaries; in detail, the number of tributaries is 63 in case of the TU12s, 21 of the TU2s, 3, of the TU3s or AU3s, and 1 of the AU4. The maximum resolution necessary in case of mixed loads is therefore equal to 81 time slots, 18 for the first sector, and to 63 for the others.

The cross connection process is scanned by the STM-1 frame timing, generated by block labelled MASTER COUNTER in Figure 1; the latter provides the time base to all circuits of the device by identifying time slots processed with a first count module 18 and thereafter four counts module 63.

The sixteen incoming flows enter the device as nibbles at a frequency of 38.88 Mb/s, all isochronous with an external multiframe synchronism. The nibble/byte conversion occurs inside the common block SAMPLE of Figure 1.

"P Being synchronized with such flows, the circuits forming block WRITE i extract the bytes necessary for the reconstruction of the four output frames and 20* write them to data storage in a suitable location.

i 0 All the operations are realized on the basis of what is contained in the 81word control memory WCM cyclically scanned with a timing bound to the input STM-1 frames. Every word is formed by a 16-bit mask, whose analysis allows individuation of position and number of tributary flows to be processed. In fact, s the bits are rigidly associated with the input frames and their value marks out the presence, in the time slot in question, of the bytes to be written into data storage, from a minimum of zero to a maximum of sixteen.

The convention used for this device is the following: if bit i 1 corresponding byte to be exchanged if bit i 0 corresponding byte not valid.

The write operation occurs in an interval having a length equivalent to one time slot, at a frequency of 19.44 MHz. To simulate a sequential filling 71 7 of the data storage, which should occur at a frequency sixteen times higher, the bytes concerned with the exchange are at first positioned one beside another, then they are suitably rotated until a temporary buffer is filled, and lastly they are written into memory.

Block WRITE is detailed in Figure 3. The circuits forming the selection and order stage of the flows to be cross connected are: a) a concentrator, CONC-left and CONC-right, with the respective control block, SIG-CONC-left and SIG-CONC-right; b) a rotator ROT and the respective control block SIG-ROT; c) a temporary buffer BUFT and the respective control block SIG-BUFT.

Moreover, the following are represented: d) a counter CNTBF providing the fill status of the temporary buffer; e) a counter CNTWADD generating the write address for the data storage.

The concentrator has the function of positioning, one beside another, the useful bytes individuated among the sixteen present at the input of block WRITE during each time slot. This operation is realized by two twin circuits, CONCright and CONC-left, that process the input flows 0 to 7 and 8 to 15, separately and in an opposite way. The corresponding control signals are generated in block SIG-CONC-right and SIG-CONC-left, by directly processing the information 20: contained in the write control word.

S° In particular, the circuits of block SIG-CONC-right individuate the position of the eventual 1's present inside the least significant byte of this word (associated with the frames 0 to 7) and act upon the corresponding block in such a way that the flows to be exchanged are displaced toward position 7 strictly respecting their order. Similarly, block SIG-CONC-left individuates the position of the eventual 1 's inside the most significant byte (associated with frames 8 to 15) and generates signals for block CONC-left, moving the useful flows toward position 8, strictly respecting their reciprocal order also in this circumstance.

Appearing at the output of the structure is a 16-bit pattern whose data to f be extracted are concentrated toward the center and certainly close irrespectively of their starting frame. The position K of the first valid bit, if any, 8 has a value certainly comprised between 0 and 8; in particular it satisfies the relation K=8-N where N is the number of 1's in the first half of the control mask.

The function of the next block, the rotator, is to rotate the group thus obtained so as to fill in an orderly manner the temporary buffer that precedes the write into data storage and that may contain a number of significant bytes, left out during the write cycle relative to the preceding time slot.

The rotator is capable of realizing all the possible rotations of 16 elements, at powers-of-two steps. The rotation phase "phrot" which drives the described structure is generated by block SIG-ROT; since the position of data extracted at the output of the concentrator is not univocally determined, it must Sooo000 take the fill state "phbf" of the temporary buffer provided by counter CNTBF and the value of K, into account.

De 15 Therefore, the rotation phase satisfies the relation °o phrot K phbf mod 16 and acts directly on circuits forming the analysed block.

The presence of the temporary buffer allows the use of an elastic storage with a sole write port, notwithstanding the structure is capable of processing up °20 to 16 flows during each time slot.

DO 0 Indeed this block is constituted by two stages to avoid the loss of useful D 0"o flow.

The first stage is a simple delay line of the rotor output data; instead, the second stage is filled in an orderly manner from position 0 to position 15. In fact it is possible to retain, for each byte, the value already written previously or to choose between the data of the output of the rotator ("direct line") and the i data at the output of the first level ("delay line"). The signals controlling these operations are generated in block SIG-BUFT and are tied to the present "phbf" and future "fphbf" value of the buffer fill-phase, both provided by block CNTBF.

The proposed solution has many advantages. In fact, through a very dimple architecture, the sequential filling of data storage is simulated and this e allows the optimisation of dimensions. Moreover, a constant arrangement of 7 c' 'IT Ol 9 the processed flows is assured, which remarkably simplifies the matrix configuration (the first extracted byte is always retained in position 0 and so on). An immediate consequence of what has just been pointed out is that the overall amount of data memory used in each elementary module is tied to the number of frames generated at the output, i.e. four, and not to the number of inputs, i.e. sixteen.

The data storage is composed of a triple bank: one corresponds to the first area in the nominal frame of Figure 2 and is therefore so dimensioned as to retain a maximum of 72 bytes; the other two correspond to the other four areas, they are so dimensioned as to contain 252 bytes and are read out and written alternately.

Since the maximum number of bytes that can be written during each time slot is sixteen, the data storage is organized in words having this size; on the whole, it is constituted by thirty seven 16-byte rows: two 1 6-row banks, a smaller one of 5 rows.

In the MATISSETM ASIC, four 37 x 32 bit RAMS (three ports a write one Sand two independent read ones) are used for each elementary module. This subdivision is exclusively tied to the maximum size of the RAMs available in the technology used for realizing the gate array. Indeed they are treated as a sole '2 elastic memory instead of four distinct memories.

o The scanning of the input frames by the MASTER COUNTER, that provides the timing signals for all the circuits of the device, allows the individuation of the memory bank on which data to be exchanged are retained.

Inside it the write address is obtained whenever the content of the temporary buffer is transferred into the memory.

So The cross connect operation is completed by the circuits of functional block READ shown in Figure 1. Their function is to realize the correct allocation of tributaries inside the four STM-1 output frames on the basis of the information contained in a control memory RCM of eighty one, 32-bit words, 8 S3U]: bits for each flow processed.

As already described, all tributaries processed are contained in a data memory constituted by three banks rigidly individuated by STM-1 frame timing.

Therefore, it follows that the addressing can be realized through the use of 8 bits only; four bits constitute the read address for a bank of the data storage and four bits are necessary for individuating, through a 16:1 mux st,,qc, the correct byte among the sixteen bytes available.

The read-out of the control memory RCM is scanned by the timing of the output frame, similar to the input frame but with a fixed delay of 63 timeslots; in this manner write and read out never overlap in the data storage.

As pointed out several times in the present description, the two output ports of the data storage are used at a nibble frequency, 38.88 MHz. Each time slot of the output frame is divided into two intervals, inside each of which two output frames are processed. This entails the need of a circuit that realizes the equation of the four frames and at the same time the byte/nibble conversion.

The circuits forming the functional block READ are shown in detail in Figure 4 and are: a) block SEL whose function is to select in each half-period the portion of the control word corresponding to the two output flows processed at the same time; b) block MUXOUT that, for each output port, individuates the correct byte among the sixteen bytes available at the output; S c) block EQUAL that equalizes the delays between the two frames processed during the first half-period and the two processed during the subsequent one (further realizing the nibble/byte conversion).

The core of operation of this connecting architecture is therefore the 25. presence of the two control memories whose time slot-after-time slot scanning allows the extraction, on the "write-side", of the bytes to be written into data storage in an orderly manner and, on the "read side", their correct individuation, in accordance with the procedure analyzed previously.

The change of a connection or the setting up of a new one for the device operation purposes, entails the modification of the position of the bytes retained in data storage since the filling up of the latter occurs in a sequential manner, This entails the need of a complete re-write of the read control memory; indeed 11 every row of it contains the position in the memory of the byte to be allocated in the time slot corresponding to the output frame.

The solution for translating the cross connection information from the format provided by the microprocessor to the form elaborated by the circuits of the device is described hereinafter.

The interface micro receives a connection map to be set up by the following format: "from time slot #a of frame #b to time slot #c of frame and elaborates it so as to repeat the correct image of the write and read control memories in two auxiliary memories hereinafter denoted by WSPM and RSPM respectively. Only when this phase is terminated, the content of the last memories is transferred into the operative control RAMs of one of the two modules, suitably specified, by exploiting the timing of the STM-1 frame.

It is important to point out that the configuration of the device would require about 200 ms should the elaboration of the connection map be wholly :o demanded to the microprocessors, while with the used structure this time is reduced to a value on the order of 1 ms (DMA transfer time).

Figure 5 shows the set of circuits that realize the above-mentioned operations.

The cross connection information is thus sent to the device in the form of a list whose maximum length is 1296 bytes. It is organized in 324 rows each constituted of four fields: a °FROM-STM, FROM-TSLOT, TO-STM, TO-TSLOT.

In particular: FROM-STM indicates the STM-1 flow, amongst the sixteen possible S ;'flows, from which the byte to be processed is to be extracted; FROM-TSLOT indicates the number of time slots of the input frame; TO-STM indicates the output STM-1 flow, amongst the four possible ones, in which the processed byte is to be inserted; TO-TSLOT indicates the number of time slots of the output frame.

The circuits forming the block MPIF operate by elaborating the connection 12 list one row at a time (on-line). The timing necessary for the operation of the entire structure is provided by block CNT4MP, that controls the acquisition of the bytes constituting each quartet of the list. The first three are initially written in temporary registers TEMP-FROM-STM, TEMP-FROM-TSLOT, TEMP- TO-STM, and upon a suitable load command they are transferred into registers FROM-STM, FROM-TSLOT, TO-STM; the last byte is directly retained in TO-

TSLOT.

The content of these registers is processed within an elaboration interval comprised between two adjacent loading signals.

Given the correspondence existing between the rows of the control memories and the time slots of the frame processed by the gate array, the values of registers FROM-TSLOT and TO-TSLOT constitute the write addresses for memories WSPM and RSPM respectively.

Each row of memory WSPM is obtained by processing the information contained in the first two fields of each quartet.

The first one indicates the number of the flow from which the byte to be So processed is extracted, the value being comprised between 0 and 15. A suitable decoder DECODFROM transforms this information, expressed over four bits, into a 16-bit mask with an in the wanted position.

The spare memory for the reading is indeed constituted by four 81 x 8 RAMs, each being associated to an output frame.

Block DECODTO, on the basis of the value of the third field of each quartet, activates the corresponding write-enable.

The content of each row if it indicates the position in which the byte to 25. be inserted in the corresponding time slot of the associated output frame, is found in the data storage.

Since the behaviour of the internal circuits of the device already analyzed in the foregoing pages, assures an ordered filling of the data storage (the byte corresponding to the first 1 of the write mask is retained in position 0 and so on), this value is obtained by a counter, the block ADDER. In case of point-topoint connections, the write of each quartet of the list determines an increase of it, which must be inhibited in the presence of a point-to-multipoint I- /2 13 connection. In this circumstance, in fact, it is the same useful byte that is addressed in correspondence to several frames or time slots.

During each processing period, the interface circuits retain memory of input frame and time slot processed during the preceding interval (registers OLD-FROM-STM and OLD-FROM-TSLOT). Therefore they are able to establish if one is in the presence either of point-to-point or point-to-multipoint connections without the need for the microprocessor to provide additional information. However, every row of the connection list must be complete and, therefore, the first two fields must be repeated for all the required connections.

The implementation of the method requires that the list transmitted by the microprocessor is in an increasing order with respect to the field FROM- TSLOT and, inside it, with respect to the field FROM-STM. The establishment of a new connection or the change of an already existing one needs the retransmission and re-processing of the entire table, since the position of the bytes processed inside the data storage can be altered (rearrangeably not latching connection matrix).

Therefore, the analyzed device realizes indifferently the HPC and LPC a a functions contemplated in CCITT Recommendations G.781, G.782, G.783; in fact, the processed connection map does not go into the question of the tributary effectively exchanged, but it is given in terms of "from time slot to time slot". When the field FROM-TSLOT goes from a value less than 17 to a value greater than 18 (which corresponds to the passage between the first and the second area of the STM-1 frame) the counter providing the value to be written into the read memory must be set to zero. In fact, in this circumstance processed bytes fill different banks of the data storage as seen previously.

S The write of the auxiliary memories is always preceded by an initialization step that initialises a void connection map.

Every row in the write memory is brought to the value "all Os" (no byte to be processed); every row in the read memory is brought to the value "all is" (all the output frames are unequipped). In this phase, the write circuits are concealed while counter CNT81MP is active which provides the write addressed of the storages allowing the initialization of all rows thereof.

I

3 14 The timing signals necessary for the operation of the structure are still provided by block CNT4MP; instead the concealment signals are generated in block INIT.

The (re) configuration operation of the device is always activated by the microprocessor which can stop it at any time. Once concluded, in the auxiliary memories there is contained a copy of the new connection map ready to be transferred into the operative memories of one of the two elementary modules of the device. The mechanism for updating the operative memory with the content of the auxiliary memories is based upon the timing of the STM-1 frame.

As it has been pointed out several times, the control memories are read on a regular basis to provide during each time slot the cross connection information necessary to the operation of the internal blocks of the gate array.

The possibility of updating their content is restricted to the first two areas of the STM-1 frame since only in correspondence therewith all the rows are o. scanned.

During the first two areas of the input frame the content of the write *4 4* S auxiliary memory is transferred into the corresponding operative RAM according to what is represented in Figure 6; while the content of the ith row is made available, the one of (i-2)sd row is updated. As a result, the internal circuits of the device start to process the new cross connection map only in correspondence with the third area of the input frame.

The updating of the read control RAM occurs with the same procedure but it follows the timing of the output STM-1 frame. The delay between the two operations, equal to 63 time slots, assures the continuity of connections not concerned with changes. The transfer operation is anyway activated by a command from microprocessor which can stop it at any time.

p 4 Naturally, it is to be borne in mind that the instructions described above are solely illustrative of the applications of the principles of the present invention. Numerous other arrangements can be used by those skilled in the art without departing in any way from the spirit and the scope of the present invention.

1~

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Claims (22)

1. A connection matrix circuit arrangement for a plurality of tributaries, the matrix comprising a first space stage, a second time stage, and a third space stage wherein said second time stage includes a data storage so dimensioned as to store exclusively data involved in an exchange of data between tributaries.

2. An arrangement as claimed in claim 1, wherein said first space stage comprises: means for concentrating input data flow from the plurality of tributaries, means for rotating data concerned with the exchange, and data storage means for sorting data involved in the exchange.

3. An arrangement as claimed in claim 1, further comprising an interface for communicating with the outside.

4. An arrangement as claimed in claim 3, wherein said interface is able to interpret the information relative to the connection matrix reconfiguration, received at an input.

5. An arrangement as claimed in claim 4, wherein information relative to the S, connection matrix reconfiguration includes information in the form "from time slot No.A of frame No. B to time slot No. C of frame No. D"

6, A method of realizing a connection matrix for use in the arrangement of claims 1 to 5, the method comprising the steps of selecting data involved in o 20 the exchange; rotating data involved in the exchange; sequentially storing data in a buffer; transferring data involved in the exchange from said buffer to said data storage means; and routing data involved in the exchange towards the output.

7. A method as claimed in claim 6, wherein data involved in the exchange are identified and selected by processing separately a first part of the input data flows and a second part of the input data flows.

8. A method as claimed in claim 6, wherein data involved in the exchange are identified and selected, said data are rotated and said data are stored by analyzing a write control word, whose bits are associated with a corresponding input frame.

9 A method as claimed in claims 6 or 8, wherein said control word is a 16- bit word.

I 1 ~L-re~ll g 16 A method as claimed in claim 6, wherein data involved in the exchange are routed toward the output by analyzing a read control word.

11. A method as claimed in claim 10, wherein said control word is a 32 bit word.

12. A method as claimed in claim 6, wherein the data storage means includes two or more read ports and wherein the number of output transmitted data flows is increased by multiplexing in time the read ports of the data storage means.

13. A method as claimed in claim 6, wherein said connection matrix is additionally re-configured in responce to read and write control words.

14. A method as claimed in claim 13, wherein information relating to the connection matrix reconfiguration received at the input is interpreted.

A method as claimed in any one of claims 8 to 11, wherein the storage of the read and write control words are compiled initially in corresponding auxiliary storages and subsequently transferred to corresponding operative control storage.

16. A method as claimed in any one of claims 8 to 15, wherein the control words are read out from their respective storages in accordance with the natural times of the format of the processed data flows. O4 20

17. A method as claimed in any one of claims 8 to 11, or claim 15, wherein a copy of the operative control storage is contained in the auxiliary storage.

18. A method as claimed in claim 15, wherein the control words contained in said auxiliary storage are transferred into said operative control storage by using the natural times of the processed data flow.

19. A circuit arrangement as claimed in any one of claims 1 to 5, wherein the data storage means includes two or more read ports and wherein the number of output transmitted data flows is increased by multiplexing in time the read ports of the data storage means.

A circuit arrangement as claimed in any one of claims 1 to implemented as an integrated circuit. -1

21. A connection matrix circuit arrangement substantially as herein described Swith reference to Figures 1 6 of the accompanying drawings. L -J 17

22. A method of interconnecting a plurality of tributaries substantially as herein described with reference to the accompanying drawings. DATED THIS TWENTY-NINTH DAY OF APRIL 1997 ALCATEL N.V 0 *0 4 4 o qof 9 N T ABSTRACT In the most recent years the introduction of the Synchronous Digital Hierarchy (SDH) has made it necessary to have connection matrices with a higher degree of complexity with respect to the previous plesiochronous multiplexers with a low transit time and a high reconfiguration rate. The present invention provides a simple, modular, rearrangeably not- latching connection architecture both for point-to-point connections and for point-to-multipoint connections, and introduces the circuits for its setting up. The essential features of the devices realized with such architecture are the compactness and the integration to the end of cost reduction and easiness of realizing large connection matrices through the use of several samples of the same. The present invention further provides a method for fastly and easily reconfiguring such devices, without introducing interruptions on unexchanged data. 0 tI 0 0a P o 0o O 0* Stto 0 o 0