AU669579B2 - Clock signal extraction - Google Patents

Description

y P/00/011 28/5/91 Rogulation 3,2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention Title: "CLOCK SIGNAL EXTRACTION" The following statement is a full description of this invention, including the best method of performing it known to us:lit'.i

I

i I Ii i I ii 2 This invention relates to a system for extracting the clock signal from an N-Mbit/s flow, in particular in a digital cross connection equlpment which processes a 155 Mbit/s NRZ (No Return to Zero) signal.

In realizing apparatus in which signals of the CMI or RZ (Return to Zero) type are entered, often the need arises of using an NRZ signal inside the apparatus to reduce the band problems of the components used therein, These problems are particularly present in digital cross connection equipment in which a great number of flows is obviously present.

In these systems (in particular 155 Mbit NRZ) long sequences of all l"s or all O's (about a hundred on an average: CCITT Rec. G.958) can be encountered.

Therefore the problem to be solved consists in assuring the survival of the extracted clock signal (hence use of a high-Q filter, typically 07 600) and in assuring the phase constancy (accuracy in the phase shifter calibration).

One solution uses a saw (Surface Acoustic Wave) filter. Just to clear up, I.44 in figure 1 a solution is represented where IL and IL' indicate the two line interfaces relative to the exchange matrix MS (represented in duplicate, even if it may be simpler).

Sl° Each clock regenerator RK', associated with a section of matrix MS comprises a filter SAW (resp. SAW') with Q>800, comprised between 800 and 1000, downstream of a phase regulator RF (respectively RF') and an amplifier A (respectively

I

This solution is structurally complex and expensive in particular because of SAW 'ilters.

I'i Another conventional solution (represented as an example in figure 2) uses an oscillator 0 whose frequency is close to the nominal one 155 4t~1 4 Mbit/s), on which the natural frequency and phase can be adjusted on the desired values through suitable calibrations.

In figure 2, SQ indicates the clipper associated with oscillator 0 represented as consisting essentially of transistor T13 with a three-turn inductor and fixed and variable capacitors. The drawback of this second solution is due to the difficulty in controlling the natural oscillation of oscillator 0 that affects f

IV

I

3 directly the phase-drift in case of long sequences of O's or l's.

It is an object of the present invention to provide a clock regenerator In a system of the type mentioned at the outset 155 Mbit/s NRZ) which is free from the abovi-mentioned drawbacks and nevertheless is particularly simple, effective, reliable and very low cost.

The regeneration circuit in accordance with the invention is capable of providing high performances, comparable with those obtainable through the use os the SAW filter but without the relative structural complexity and high cost, as well as performances better than circuit of figure 2 substantially at parity of costs.

The circuit in accordance with the inventions is characterized by the combination of a very low cost filter, in particular an LC filter with Q 30 also acting as a phase regulator and a fifth-harmonic quartz AT which is easily accessible and commercially convenient as well, with Q 10,000.

In figure 3, RF indicates now a phase regulator having substantially the ~structure of oscillator 0 of figure 2, but it is simpler having eliminated inductor L S and capacitors C132 and CV17, no longer necessary.

4444 The signal from output 100 of RF is now fed to quartz Q3 whose output i 1 is supplied to clipper SQ which comprises now a pair of transistors TR5 and TR14 acting as a differential amplifier like in figure 2; the desired clock signal CK is obtained on CKDB and CKDBN.

From diagrams shown in figures 4, 5 and 6 an analysis of circuit of figure 44 3 is deduced.

The excitation signal at ECL level obtained from NRZ data, is applied to 5 the circuit through a resistor that drives in current the filter LC tuned on the frequency to be extracted. The resistive impedance presented at resonance by such filter, added to the one of the polarization inductance of the clipper differential downstream of the circuit, is placed in series with the quartz resonating at the same frequency, thus reducing its Q from 10,000 to about 1,0ooo0.

The result is a sole filter with a Q of value suitable to the use.

An embodiment of such circuit is represented in figure 3, while figures 4 L i n i ii aw«8^- *ifn^«..mi.iniiiiiiiiT <i mm i.iiiiWii.ii.ni.i...i.ii>ii.iNM« «^.fcai.aa«-^sfe 4 ans 5 show the amplitude (AM) and phase (FA) behavious in function of the frequency.

The damping of the extracted clock at the transient "presence/absence" of transitions on the input NRZ signal is represented in figure 6.

i i ii .4 4$ 4 4 I i 1

Claims (4)

1. A system for regenerating a clock signal from an N-Mbit/s no return to zero flow in a digital cross connection equipment, said system comprising a phase regulator and a fifth harmonic quartz which act to filter the nominal frequency of the clock signal.

2. A system as claimed in claim 1, wherein the flow is 155 Mbit/s and the quartz works at this same frequency which corresponds to its fifth harmonic,

3. A system substantially as herein described with reference to Figures 3 6 of the accompanying drawings. DATED THIS THIRTEENTH DAY OF MARCH 1996 ALCATEL N.V. 4 St 4 4 4 RA T I 1 'NT 1 L L 01 ABSTRACT A system for regenerating the clock signal from an M-Mbit/s NRZ flow comprises a phase regulator and a quartz that acts as a filter of the nominal frequency of the extracted clock. In a preferred embodiment at 1 55 Mbit/s the quartz works at the fifth harmonic. 4f~4 8488 S. 8 @808 8080 8 6W 88 0 888849 8 S

84. 88 88 5 S 0 8888 8 88 84 8 8 844*80 8 8 8888 8 88 o9 8 84 a 88 8 V