AU6503596A - Port and link identification - Google Patents

Port and link identification

Info

Publication number
AU6503596A
AU6503596A AU65035/96A AU6503596A AU6503596A AU 6503596 A AU6503596 A AU 6503596A AU 65035/96 A AU65035/96 A AU 65035/96A AU 6503596 A AU6503596 A AU 6503596A AU 6503596 A AU6503596 A AU 6503596A
Authority
AU
Australia
Prior art keywords
port
link identification
identification
link
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU65035/96A
Inventor
Stephen A. Caldara
Stephen A. Hauser
Thomas A. Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascom Nexion Inc
Original Assignee
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascom Nexion Inc filed Critical Ascom Nexion Inc
Publication of AU6503596A publication Critical patent/AU6503596A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • H—ELECTRICITY
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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/4608—LAN interconnection over ATM networks
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    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU65035/96A 1995-07-19 1996-07-18 Port and link identification Abandoned AU6503596A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US001498 1995-07-19
PCT/US1996/011963 WO1997004569A1 (en) 1995-07-19 1996-07-18 Port and link identification

Publications (1)

Publication Number Publication Date
AU6503596A true AU6503596A (en) 1997-02-18

Family

ID=38659726

Family Applications (1)

Application Number Title Priority Date Filing Date
AU65035/96A Abandoned AU6503596A (en) 1995-07-19 1996-07-18 Port and link identification

Country Status (3)

Country Link
JP (1) JPH11510329A (en)
AU (1) AU6503596A (en)
WO (1) WO1997004569A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3735513B2 (en) 2000-05-22 2006-01-18 埼玉日本電気株式会社 Mobile communication system, base station demodulator and base station demodulator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321695A (en) * 1991-05-01 1994-06-14 Hewlett-Packard Company Port arrival identification for computer network packets
JPH07118717B2 (en) * 1993-01-05 1995-12-18 日本電気株式会社 Multi-protocol packet network configuration method

Also Published As

Publication number Publication date
JPH11510329A (en) 1999-09-07
WO1997004569A1 (en) 1997-02-06

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