AU6502796A - Serial control and data interconnect system using a crossbar switch and a multipoint topology - Google Patents

Serial control and data interconnect system using a crossbar switch and a multipoint topology

Info

Publication number
AU6502796A
AU6502796A AU65027/96A AU6502796A AU6502796A AU 6502796 A AU6502796 A AU 6502796A AU 65027/96 A AU65027/96 A AU 65027/96A AU 6502796 A AU6502796 A AU 6502796A AU 6502796 A AU6502796 A AU 6502796A
Authority
AU
Australia
Prior art keywords
crossbar switch
interconnect system
serial control
data interconnect
multipoint topology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU65027/96A
Other languages
English (en)
Inventor
Stephen A. Caldara
Stephen A. Hauser
Thomas A. Manning
Robert B. Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascom Nexion Inc filed Critical Ascom Nexion Inc
Publication of AU6502796A publication Critical patent/AU6502796A/en
Abandoned legal-status Critical Current

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    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
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    • H04L2012/5681—Buffer or queue management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5682—Threshold; Watermark
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU65027/96A 1995-07-19 1996-07-18 Serial control and data interconnect system using a crossbar switch and a multipoint topology Abandoned AU6502796A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US001498 1995-07-19
PCT/US1996/011946 WO1997004397A1 (en) 1995-07-19 1996-07-18 Serial control and data interconnect system using a crossbar switch and a multipoint topology

Publications (1)

Publication Number Publication Date
AU6502796A true AU6502796A (en) 1997-02-18

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ID=38659714

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Application Number Title Priority Date Filing Date
AU65027/96A Abandoned AU6502796A (en) 1995-07-19 1996-07-18 Serial control and data interconnect system using a crossbar switch and a multipoint topology

Country Status (3)

Country Link
JP (1) JPH11510012A (ja)
AU (1) AU6502796A (ja)
WO (1) WO1997004397A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934305B1 (en) 1999-01-15 2005-08-23 Cisco Technology, Inc. Method and apparatus for detecting errors in a backplane frame
US7293090B1 (en) 1999-01-15 2007-11-06 Cisco Technology, Inc. Resource management protocol for a configurable network router
US6724757B1 (en) * 1999-01-15 2004-04-20 Cisco Technology, Inc. Configurable network router
US6982974B1 (en) 1999-01-15 2006-01-03 Cisco Technology, Inc. Method and apparatus for a rearrangeably non-blocking switching matrix
US9287208B1 (en) * 2014-10-27 2016-03-15 Intel Corporation Architecture for on-die interconnect

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3974343A (en) * 1975-01-10 1976-08-10 North Electric Company Small modular communications switching system with distributed programmable control
US4821034A (en) * 1987-02-06 1989-04-11 Ancor Communications, Inc. Digital exchange switch element and network
DE69123663T2 (de) * 1990-08-31 1997-06-26 Ibm Kanäle in einem Rechnerein-Ausgabesystem
US5506956A (en) * 1993-04-07 1996-04-09 Sprint Communications Company L.P. Error correction and channel restoration apparatus for T1 digital links
US5524113A (en) * 1993-08-30 1996-06-04 Washington University ATM switch interface

Also Published As

Publication number Publication date
WO1997004397A1 (en) 1997-02-06
JPH11510012A (ja) 1999-08-31

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